Prosecution Insights
Browse Companies Examiners Firms Draft Your Response
Office Actions › Texas Instruments Incorporated › 18822571
Last updated: July 17, 2026
Application No. 18/822,571

CACHE CONTROL CIRCUIT WITH FETCH HYSTERESIS

Non-Final OA
Filed
Sep 03, 2024
Priority
Dec 20, 2016 — continuation of 10/209,887 +3 more
Examiner
OTTO, ALAN
Art Unit
Tech Center
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
66%
Grant Probability
Favorable
1-2
OA Rounds
1y 6m
Est. Remaining
84%
With Interview

Interview Optional

— +17.9% interview lift. Examiner has a relatively high allowance rate (66%); +17.9% interview lift. A written response may suffice.
Based on 371 resolved cases, 2023–2026

Examiner Intelligence

OTTO, ALAN View full profile →
Grants 66% — above average
66%
Career Allowance Rate
246 granted / 371 resolved
+6.3% vs TC avg
Strong +18% interview lift
Without
With
+17.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
13 currently pending
Career history
392
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
83.8%
+43.8% vs TC avg
§102
12.8%
-27.2% vs TC avg
§112
1.9%
-38.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 371 resolved cases

Prosecution Timeline

Sep 03, 2024
Application Filed
May 21, 2026
Non-Final Rejection mailed (current)

Precedent Cases

Applications granted by this same examiner with similar technology

18/830,242
Patent 12664092
METHOD AND SYSTEM FOR MANAGING CACHE DATA BASED ON SCORE
1y 9m to grant Granted Jun 23, 2026
18/477,378
Patent 12625779
AUTOMATED RECONSTRUCTION AND ATTRIBUTION OF DATA MODIFICATIONS
2y 7m to grant Granted May 12, 2026
18/094,994
Patent 12608136
FLASH MEMORY SCHEME CAPABLE OF CONTROLLING FLASH MEMORY DEVICE AUTOMATICALLY GENERATING DEBUG INFORMATION AND TRANSMITTING DEBUG INFORMATION BACK TO FLASH MEMORY CONTROLLER WITH MAKING MEMORY CELL ARRAY GENERATING ERRORS
3y 3m to grant Granted Apr 21, 2026
18/822,415
Patent 12602324
STORAGE CONTROLLER, MEMORY MANAGEMENT METHOD AND STORAGE DEVICE
1y 7m to grant Granted Apr 14, 2026
18/581,944
Patent 12591367
TECHNIQUES FOR LOG ORDERING TO OPTIMIZE WRITE LATENCY IN SYSTEMS ASSIGNING LOGICAL ADDRESS OWNERSHIP
2y 1m to grant Granted Mar 31, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
66%
Grant Probability
84%
With Interview (+17.9%)
3y 5m (~1y 6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 371 resolved cases by this examiner. Grant probability derived from career allowance rate.

Ready to respond to this office action?

IP Author drafts your complete OA response — amendments, arguments, and claim strategy — in minutes, not days.

Start Drafting Your Response →

Data sourced from USPTO Patent File Wrapper (daily) and Office Action Archive (weekly). Analysis generated by IP Author.

Data: USPTO Patent File Wrapper (daily) • Office Action Archive (weekly) • 89M+ prosecution events

© 2026 IP Author — Browse Office Actions • Examiners • Companies • Firms

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month