DETAILED ACTION
This Office Action is in response to the Application filed on 09/03/2024.
Currently, claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/15/2024 and 12/30/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the Examiner.
Claim Objections
Claims 1, 8, and 15 are objected to because of the following informality:
In claims 1, 8, and 15, “source drain” should read “source/drain”
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15 recites the limitation “the backside dielectric”. There is insufficient antecedent basis for this limitation in the claim. Therefore, the claim has an indefinite scope. For the purpose of examination, this limitation will be read as: “a backside dielectric”
Claims 16-20 are also rejected under 112(b) as they depend on base claim 15.
Claims 17 and 18 recite the limitation “a backside dielectric layer”. It is unclear if the backside dielectric layers of claims 17 and 18 are the same layer or a different layer as the backside dielectric of claim 15. Therefore, the claim has an indefinite scope. For the purpose of examination, the backside dielectric layers of claims 17 and 18 will be interpreted as a separate layer than the backside dielectric of claim 15.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YU et al. (US Pub. No. 2022/0069117)
Regarding independent claim 1, Yu teaches a nanosheet (¶ [0003] teaches that Yu’s device can be a nanosheet transistor) semiconductor structure (Fig. 18A) comprising: a placeholder (Fig. 18A, 238, ¶ [0028]) directly beneath (the Examiner notes that the orientation of Yu’s device in Fig. 18A is upside-down compared to Applicant’s device) a source/drain region (Fig. 18A, 238, 242D, ¶¶ [0028] & [0030]); a backside contact structure (Fig. 18A, 270, ¶ [0041]) adjacent to the placeholder; and a backside spacer layer (Fig. 18A, 276, ¶ [0042]) surrounding the placeholder (Fig. 18A, 276 at least partially surrounds 238) and partially surrounding a top portion (Fig. 18A, 270-1, ¶ [0043], 276 surrounds 270-1 except for the bottom most surface of 270-1 in contact with 266, see Fig. 16A) of the backside contact structure.
Regarding claim 2, Yu teaches the semiconductor structure according to claim 1, and Yu teaches that the backside spacer layer (Fig. 18A, 276, ¶ [0042]) surrounds sides and a bottom of the placeholder (Fig. 18A, 238, ¶ [0028], 276 surrounds sides and a top surface of 238. The Examiner notes that the orientation of Yu’s device in Fig. 18A is upside-down compared to Applicant’s device).
Regarding claim 3, Yu teaches the semiconductor structure according to claim 1, and Yu teaches that the backside spacer layer (Fig. 18A, 276, ¶ [0042]) physically separates a backside dielectric layer (Fig. 18A, 278, ¶ [0042]) from a gate (Fig. 18A, 250, ¶ [0034]).
Regarding claim 4, Yu teaches the semiconductor structure according to claim 1, and Yu teaches that the backside spacer layer (Fig. 18A, 276, ¶ [0042]) conformally contacts a top surface (Fig. 18A, 276 contacts a bottom surface of 278. The Examiner notes that the orientation of Yu’s device in Fig. 18A is upside-down compared to Applicant’s device) of a backside dielectric layer (Fig. 18A, 278, ¶ [0042]).
Regarding claim 5, Yu teaches the semiconductor structure according to claim 1, and Yu teaches that vertical pillars (Figs. 16A & 18A, upper vertical portions of 264 appear to be substantially aligned with 236, ¶ [0040]) of a backside dielectric layer (Figs. 16A & 18A, 264, ¶ [0040]) are substantially aligned with inner spacers (Figs. 16A & 18A, 236, ¶ [0027]).
Regarding claim 6, Yu teaches the semiconductor structure according to claim 1, and Yu teaches that the backside contact structure (Fig. 18A, 270, ¶ [0041]) comprises a top portion (Fig. 18A, 270-1, ¶ [0043], the Examiner notes that the orientation of Yu’s device in Fig. 18A is upside-down compared to Applicant’s device) having a first lateral dimension (Fig. 18A, W1, ¶ [0043]) and a bottom portion (Fig. 18A, 270-2, ¶ [0043]) having a second lateral dimension (Fig. 18A, W2, ¶ [0043]).
Regarding claim 7, Yu teaches the semiconductor structure according to claim 6, and Yu teaches that a top of the bottom portion (Fig. 18A, 270-2, ¶ [0043]) of the backside contact structure (Fig. 18A, 270, ¶ [0041]) is above (Fig. 18A, a bottommost surface of 270-2 is below a topmost surface of 238, the Examiner notes that the orientation of Yu’s device in Fig. 18A is upside-down compared to Applicant’s device) a bottom of the placeholder (Fig. 18A, 238, ¶ [0028]).
Regarding independent claim 15, Yu teaches a nanosheet (¶ [0003] teaches that Yu’s device can be a nanosheet transistor) semiconductor structure (Fig. 18A) comprising: a placeholder (Fig. 18A, 238, ¶ [0028]) directly beneath (the Examiner notes that the orientation of Yu’s device in Fig. 18A is upside-down compared to Applicant’s device) a source/drain region (Fig. 18A, 238, 242D, ¶¶ [0028] & [0030]); a backside contact structure (Fig. 18A, 270, ¶ [0041]) adjacent to the placeholder (Fig. 18A, 276 at least partially surrounds 238); and a backside spacer layer (Fig. 18A, 276, ¶ [0042]) surrounding the placeholder (Fig. 18A, 276 at least partially surrounds 238), wherein protruding portions of a backside dielectric (Fig. 18A, bottom portions of 278, ¶ [0042]) are substantially aligned with nanosheet channels (Fig. 18A, 2080, ¶ [0033]).
Regarding claim 16, Yu teaches the semiconductor structure according to claim 15, wherein the backside spacer layer (Fig. 18A, 276, ¶ [0042]) surrounds sides and a bottom of the placeholder (Fig. 18A, 238, ¶ [0028], 276 surrounds sides and a top surface of 238. The Examiner notes that the orientation of Yu’s device in Fig. 18A is upside-down compared to Applicant’s device).
Regarding claim 17, Yu teaches the semiconductor structure according to claim 15, wherein the backside spacer layer (Fig. 18A, 276, ¶ [0042]) conformally contacts a top surface (Fig. 18A, 276 contacts a bottom surface of 278. The Examiner notes that the orientation of Yu’s device in Fig. 18A is upside-down compared to Applicant’s device) of a backside dielectric layer (Fig. 18A, 278, ¶ [0042]).
Regarding claim 18, Yu teaches the semiconductor structure according to claim 15, and Yu teaches that vertical pillars (Figs. 16A & 18A, upper vertical portions of 264 appear to be substantially aligned with 236, ¶ [0040]) of a backside dielectric layer (Figs. 16A & 18A, 264, ¶ [0040]) are substantially aligned with inner spacers (Figs. 16A & 18A, 236, ¶ [0027]).
Regarding claim 19, Yu teaches the semiconductor structure according to claim 15, and Yu teaches that the backside contact structure (Fig. 18A, 270, ¶ [0041]) comprises a top portion (Fig. 18A, 270-1, ¶ [0043], the Examiner notes that the orientation of Yu’s device in Fig. 18A is upside-down compared to Applicant’s device) having a first lateral dimension (Fig. 18A, W1, ¶ [0043]) and a bottom portion (Fig. 18A, 270-2, ¶ [0043]) having a second lateral dimension (Fig. 18A, W2, ¶ [0043]).
Regarding claim 20, Yu teaches the semiconductor structure according to claim 19, and Yu teaches that a top of the bottom portion (Fig. 18A, 270-2, ¶ [0043]) of the backside contact structure (Fig. 18A, 270, ¶ [0041]) is above (Fig. 18A, a bottommost surface of 270-2 is below a topmost surface of 238, the Examiner notes that the orientation of Yu’s device in Fig. 18A is upside-down compared to Applicant’s device) a bottom of the placeholder (Fig. 18A, 238, ¶ [0028]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-14 are rejected under 35 U.S.C. 103 as being obvious over YU et al. (US Pub. No. 2022/0069117) in view of YEUNG et al. (US Pub. No. 2025/0113513).
Regarding independent claim 8, Yu teaches a nanosheet (¶ [0003] teaches that Yu’s device can be a nanosheet transistor) semiconductor structure (Fig. 18A) comprising: a placeholder (Fig. 18A, 238, ¶ [0028]) directly beneath (the Examiner notes that the orientation of Yu’s device in Fig. 18A is upside-down compared to Applicant’s device) a source/drain region (Fig. 18A, 238, 242D, ¶¶ [0028] & [0030]); a backside contact structure (Fig. 18A, 270, ¶ [0041]) adjacent to the placeholder; and a backside spacer layer (Fig. 18A, 276, ¶ [0042]) surrounding the placeholder (Fig. 18A, 276 at least partially surrounds 238).
However, Yu does not explicitly teach that a backside spacer layer (Fig. 2N-3, 168, ¶ [0135]) directly contacting bottommost surfaces (Fig. 2N-3, portions of 168 at least partially contact the bottom surfaces of 108_1) of bottommost nanosheet (Fig. 2N-3, 108_1, ¶ [0039]) channels.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yu’s device to include an additional semiconductor layer in contact with the backside liner according to the teaching of Yeung (Fig. 2N-3) in order to reduce resistance of back end of line layers (Yeung ¶ [0033]).
Regarding claim 9, Yu modified by Yeung teaches the semiconductor structure according to claim 8, and Yu teaches that the backside spacer layer (Fig. 18A, 276, ¶ [0042]) surrounds sides and a bottom of the placeholder (Fig. 18A, 238, ¶ [0028], 276 surrounds sides and a top surface of 238. The Examiner notes that the orientation of Yu’s device in Fig. 18A is upside-down compared to Applicant’s device).
Regarding claim 10, Yu modified by Yeung teaches the semiconductor structure according to claim 8, and Yu teaches that the backside spacer layer (Fig. 18A, 276, ¶ [0042]) physically separates a backside dielectric layer (Fig. 18A, 278, ¶ [0042]) from a gate (Fig. 18A, 250, ¶ [0034]).
Regarding claim 11, Yu modified by Yeung teaches the semiconductor structure according to claim 8, and Yu teaches that the backside spacer layer (Fig. 18A, 276, ¶ [0042]) conformally contacts a top surface (Fig. 18A, 276 contacts a bottom surface of 278. The Examiner notes that the orientation of Yu’s device in Fig. 18A is upside-down compared to Applicant’s device) of a backside dielectric layer (Fig. 18A, 278, ¶ [0042]).
Regarding claim 12, Yu modified by Yeung teaches the semiconductor structure according to claim 8, and Yu teaches that vertical pillars (Figs. 16A & 18A, upper vertical portions of 264 appear to be substantially aligned with 236, ¶ [0040]) of a backside dielectric layer (Figs. 16A & 18A, 264, ¶ [0040]) are substantially aligned with inner spacers (Figs. 16A & 18A, 236, ¶ [0027]).
Regarding claim 13, Yu modified by Yeung teaches the semiconductor structure according to claim 8, and Yu teaches that the backside contact structure (Fig. 18A, 270, ¶ [0041]) comprises a top portion (Fig. 18A, 270-1, ¶ [0043], the Examiner notes that the orientation of Yu’s device in Fig. 18A is upside-down compared to Applicant’s device) having a first lateral dimension (Fig. 18A, W1, ¶ [0043]) and a bottom portion (Fig. 18A, 270-2, ¶ [0043]) having a second lateral dimension (Fig. 18A, W2, ¶ [0043]).
Regarding claim 14, Yu modified by Yeung teaches the semiconductor structure according to claim 13, and Yu teaches that a top of the bottom portion (Fig. 18A, 270-2, ¶ [0043]) of the backside contact structure (Fig. 18A, 270, ¶ [0041]) is above (Fig. 18A, a bottommost surface of 270-2 is below a topmost surface of 238, the Examiner notes that the orientation of Yu’s device in Fig. 18A is upside-down compared to Applicant’s device) a bottom of the placeholder (Fig. 18A, 238, ¶ [0028]).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2026/0040657 by Na et al discloses a semiconductor device.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub No. 2025/0311349 by Huang et al discloses a semiconductor device.
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/R.P.S./
Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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