Detailed Action
Claims 1-20 are pending. No claims have been cancelled or withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 09/03/2024 and 04/18/2025 appear to be in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) (1, 3, 6-10) and (11, 13, 16-20) is/are rejected under 35 U.S.C. 103 as being unpatentable over OOWADA (US 20220101926 A1) in view of AWAN (US 20190370501 A1).
Regarding claim 1, OOWADA teaches:
A memory system (OOWADA [0033] “FIG. 1 is a block diagram of one embodiment of a memory system 100 that implements the proposed technology, including the proposed erased process.”)
comprising: a nonvolatile memory that includes a plurality of first storage areas each configured to store user data (OOWADA [0002] Users of non-volatile memory can program (e.g., write) data to the non-volatile memory and later read that data back. For example, a digital camera may take a photograph and store the photograph in non-volatile memory.”, [0037] “In many systems, the non-volatile memory is addressed internally to the storage system using physical addresses associated with the one or more memory die. However, the host system will use logical addresses to address the various memory locations. This enables the host to assign data to consecutive logical addresses, while the storage system is free to store the data as it wishes among the locations of the one or more memory die.” [0086] “In some embodiments, controller 120 receives host data (also referred to as user data or data from an entity external to the memory system)”);
and a controller configured to: acquire first information related to the number of program/erase cycles for at least one of the plurality of first storage areas (OOWADA [0032] “In one embodiment, a control circuit connected to a group of non-volatile memory cells is configured to erase the group of non-volatile memory cells… The switching from applying erasing to subsets of the non-volatile memory cells separately to concurrently applying erasing to all non-volatile memory cells of the group is based on a metric indicative of the amount of use of the memory cells. For example, the switching can be based on the number of iterations of the erase process (also known as loop count), the magnitude of the erase voltage, the number of program/erase cycles, or other metric.”);
in response to acquisition of the first information, execute a data erase operation on each of the plurality of first storage areas (OOWADA [0032] “The switching from applying erasing to subsets of the non-volatile memory cells separately to concurrently applying erasing to all non-volatile memory cells of the group is based on a metric indicative of the amount of use of the memory cells. For example, the switching can be based on the number of iterations of the erase process (also known as loop count), the magnitude of the erase voltage, the number of program/erase cycles, or other metric.”); in response to completion of the data erase operation, acquire second information related to the number of program/erase cycles for the at least one of the plurality of first storage areas (OOWADA [0123] “Step 1302 is performed when the memory is new and has experienced less program/erase cycles (i.e. beginning of life or BOL). The population of memory cells may be a block, multiple blocks, a die, a portion of a block, or other grouping. In step 1304, the memory system performs a second method of erase for the same population of memory cells. Step 1304 is performed when the memory has experienced many (e.g., >3K) program/erase cycles (i.e. middle of life [MOL] or end of life [EOL]). The first method of erase is different than the second method of erase.”);
Further regarding claim 1, OOWADA does not explicitly teach, but in a related art AWAN teaches:
and generate an erase certificate that includes the first information and the second information (AWAN [0034] “At step 330, in response to erasing the content, the device may generate and issue a certificate of erasure. For example, in a storage device, a root key for the storage device may be used to generate and issue a certificate indicating that the content was successfully erased. It is appreciated that in some embodiments, other keys stored on the device may be used to generate and issue the certificate.”)
Since OOWADA and AWAN are from the same field of endeavor as both are directed to secure memory functions, which is within the same field of endeavor as the claimed invention, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify and combine the teachings of OOWADA by incorporating the teachings of AWAN into OOWADA. The motivation to combine is to improve secure erasure and verification thereof. (OOWADA [AB]; AWAN [AB]). One of ordinary skill in the art would appreciate certificating the successful erasure of data through a cryptographic erase process in accordance with an erase command would thereby include confirmation for compliance of said process. As demonstrated by OOWADA, the number of erase cycles can determine a particular erase process. In certifying such an erasure process, it would be obvious for one of ordinary skill in the art to include erase cycle information as authentication information within an erase certificate, such as taught by AWAN, especially when the mode of erasure process is determined by said erase cycle information.).
Regarding claim 3, OOWADA-AWAN teaches:
The memory system according to claim 1, wherein the controller is configured to: in response to receiving a first request from a first host, acquire the first information (OOWADA [0002-0003] “Users of non-volatile memory can program (e.g., write) data to the non-volatile memory and later read that data back… All or portions of the non-volatile memory can also be erased. For example, if data becomes stale or is no longer needed, the portion of the non-volatile memory storing the stale or no-longer-needed data can be erased so that the portion of the non-volatile memory can be available for storing new data. Alternatively, the erasing can be used to write data; for example, program from a first state to a second state and erase back to the first state (or between more than two states).”, [0032] “In one embodiment, a control circuit connected to a group of non-volatile memory cells is configured to erase the group of non-volatile memory cells… The switching from applying erasing to subsets of the non-volatile memory cells separately to concurrently applying erasing to all non-volatile memory cells of the group is based on a metric indicative of the amount of use of the memory cells. For example, the switching can be based on the number of iterations of the erase process (also known as loop count), the magnitude of the erase voltage, the number of program/erase cycles, or other metric.”), the first request requesting the data erase operation on the plurality of first storage areas and generation of the erase certificate (OOWADA [0003] “All or portions of the non-volatile memory can also be erased.” AWAN [0034] “Once the device, e.g., storage device, a smart phone, etc., is manufactured, an authorized user may wish to erase the content for various reasons, e.g., data being compromised, in military applications, under certain stringent regulations regarding personally identifiable information, recycling the device, etc. At step 310, a signal is received indicating that a content or a portion thereof is to be erased. At step 320, in response to receiving a signal indicating that the content is to be erased, erasing the content. At step 330, in response to erasing the content, the device may generate and issue a certificate of erasure. For example, in a storage device, a root key for the storage device may be used to generate and issue a certificate indicating that the content was successfully erased.”); in response to the acquisition of the first information, execute the data erase operation on each of the plurality of first storage areas (OOWADA [0032] “The switching from applying erasing to subsets of the non-volatile memory cells separately to concurrently applying erasing to all non-volatile memory cells of the group is based on a metric indicative of the amount of use of the memory cells. For example, the switching can be based on the number of iterations of the erase process (also known as loop count), the magnitude of the erase voltage, the number of program/erase cycles, or other metric.”); in response to the completion of the data erase operation, acquire the second information (OOWADA [0123] “Step 1302 is performed when the memory is new and has experienced less program/erase cycles (i.e. beginning of life or BOL). The population of memory cells may be a block, multiple blocks, a die, a portion of a block, or other grouping. In step 1304, the memory system performs a second method of erase for the same population of memory cells. Step 1304 is performed when the memory has experienced many (e.g., >3K) program/erase cycles (i.e. middle of life [MOL] or end of life [EOL]). The first method of erase is different than the second method of erase.”); and generate the erase certificate that includes the first information and the second information (AWAN [0034] “Once the device, e.g., storage device, a smart phone, etc., is manufactured, an authorized user may wish to erase the content for various reasons… At step 310, a signal is received indicating that a content or a portion thereof is to be erased. At step 320, in response to receiving a signal indicating that the content is to be erased, erasing the content. At step 330, in response to erasing the content, the device may generate and issue a certificate of erasure. For example, in a storage device, a root key for the storage device may be used to generate and issue a certificate indicating that the content was successfully erased.” One of ordinary skill in the art would appreciate that memory lifecycle information indicating the confirmation of erasure would be obvious to include within an erasure certificate. OOWADA demonstrates the number of erase cycles as relevant information for erasure confirmation and implementation, and thus one of ordinary skill in the art would be motivated to include the number of erase cycles within an erasure certificate, such as taught by AWAN, to certify the selectively implemented methods of erasure, such as taught by OOWADA’s selection of erasure methods within [0123].).
Regarding claim 6, OOWADA-AWAN teaches:
The memory system according to claim 1, wherein the first information includes a sum of the numbers of program/erase cycles for the respective first storage areas before the data erase operation is executed, and the second information includes a sum of the numbers of program/erase cycles for the respective first storage areas after the data erase operation is completed (OOWADA [0123] “Step 1302 is performed when the memory is new and has experienced less program/erase cycles (i.e. beginning of life or BOL). The population of memory cells may be a block, multiple blocks, a die, a portion of a block, or other grouping. In step 1304, the memory system performs a second method of erase for the same population of memory cells. Step 1304 is performed when the memory has experienced many (e.g., >3K) program/erase cycles (i.e. middle of life [MOL] or end of life [EOL]). The first method of erase is different than the second method of erase.”).
Regarding claim 7, OOWADA-AWAN teaches:
The memory system according to claim 1, wherein the first information includes the number of program/erase cycles for each of the first storage areas before the data erase operation is executed, and the second information includes the number of program/erase cycles for each of the first storage areas after the data erase operation is completed (OOWADA [0123] “Step 1302 is performed when the memory is new and has experienced less program/erase cycles (i.e. beginning of life or BOL). The population of memory cells may be a block, multiple blocks, a die, a portion of a block, or other grouping. In step 1304, the memory system performs a second method of erase for the same population of memory cells. Step 1304 is performed when the memory has experienced many (e.g., >3K) program/erase cycles (i.e. middle of life [MOL] or end of life [EOL]). The first method of erase is different than the second method of erase.”).
Regarding claim 8, OOWADA-AWAN teaches:
The memory system according to claim 1, wherein the first information includes at least one of a maximum value and a minimum value of the numbers of program/erase cycles for the respective first storage areas before the data erase operation is executed, and the second information includes at least one of a maximum value and a minimum value of the numbers of program/erase cycles for the respective first storage areas after the data erase operation is completed (OOWADA [0131] “If not all memory cells of all NAND strings have successfully passed erase verification then in step 1714 it is determined whether the number of iterations of the erase process has reached the maximum number of iterations (i<iMax). If the number of iterations (i) of the erase process has reached the maximum number of iterations (iMax), then the erase has failed (1716). In one embodiment, iMax=6. In one embodiment the value of iMax is stored in parameters 318 (see FIG. 2). If the number of iterations of the erase process has not reached the maximum number of iterations, then the erase process continues at step 1718 during which the erase voltage signal VERA is stepped up to the next magnitude.”).
Regarding claim 9, OOWADA-AWAN teaches:
The memory system according to claim 1, wherein at least one of the first information and the second information further includes one or more parameters related to a degree of wear-out of the nonvolatile memory (OOWADA [0123] “Step 1302 is performed when the memory is new and has experienced less program/erase cycles (i.e. beginning of life or BOL). The population of memory cells may be a block, multiple blocks, a die, a portion of a block, or other grouping. In step 1304, the memory system performs a second method of erase for the same population of memory cells. Step 1304 is performed when the memory has experienced many (e.g., >3K) program/erase cycles (i.e. middle of life [MOL] or end of life [EOL]). The first method of erase is different than the second method of erase.”.
Regarding claim 10, OOWADA-AWAN teaches:
The memory system according to claim 1, wherein the nonvolatile memory includes a plurality of blocks, and each of the first storage areas includes one or more blocks on which the data erase operation is executable in parallel, among the plurality of blocks (OOWADA [0123] “Step 1302 is performed when the memory is new and has experienced less program/erase cycles (i.e. beginning of life or BOL). The population of memory cells may be a block, multiple blocks, a die, a portion of a block, or other grouping. In step 1304, the memory system performs a second method of erase for the same population of memory cells. Step 1304 is performed when the memory has experienced many (e.g., >3K) program/erase cycles (i.e. middle of life [MOL] or end of life [EOL]). The first method of erase is different than the second method of erase.”).
Regarding claim 11, OOWADA-AWAN teaches:
A memory system (OOWADA [0033] “FIG. 1 is a block diagram of one embodiment of a memory system 100 that implements the proposed technology, including the proposed erased process.”) comprising: a nonvolatile memory that includes a plurality of first storage areas each configured to store user data(OOWADA [0002] Users of non-volatile memory can program (e.g., write) data to the non-volatile memory and later read that data back. For example, a digital camera may take a photograph and store the photograph in non-volatile memory.”, [0037] “In many systems, the non-volatile memory is addressed internally to the storage system using physical addresses associated with the one or more memory die. However, the host system will use logical addresses to address the various memory locations. This enables the host to assign data to consecutive logical addresses, while the storage system is free to store the data as it wishes among the locations of the one or more memory die.” [0086] “In some embodiments, controller 120 receives host data (also referred to as user data or data from an entity external to the memory system)”); and a controller configured to: in response to a command from a host, execute a data erase operation on each of the plurality of first storage areas(OOWADA [0002-0003] “Users of non-volatile memory can program (e.g., write) data to the non-volatile memory and later read that data back… All or portions of the non-volatile memory can also be erased. For example, if data becomes stale or is no longer needed, the portion of the non-volatile memory storing the stale or no-longer-needed data can be erased so that the portion of the non-volatile memory can be available for storing new data. Alternatively, the erasing can be used to write data; for example, program from a first state to a second state and erase back to the first state (or between more than two states).”, [0032] “In one embodiment, a control circuit connected to a group of non-volatile memory cells is configured to erase the group of non-volatile memory cells…”, [0037] “Processor 156 performs the various controller memory operations, such as programming, erasing, reading, as well as memory management processes.”); in response to completion of the data erase operation, acquire information related to the number of program/erase cycles for at least one of the plurality of first storage areas(OOWADA [0123] “Step 1302 is performed when the memory is new and has experienced less program/erase cycles (i.e. beginning of life or BOL). The population of memory cells may be a block, multiple blocks, a die, a portion of a block, or other grouping. In step 1304, the memory system performs a second method of erase for the same population of memory cells. Step 1304 is performed when the memory has experienced many (e.g., >3K) program/erase cycles (i.e. middle of life [MOL] or end of life [EOL]). The first method of erase is different than the second method of erase.”); and generate an erase certificate that includes at least the information (AWAN [0034] “At step 330, in response to erasing the content, the device may generate and issue a certificate of erasure. For example, in a storage device, a root key for the storage device may be used to generate and issue a certificate indicating that the content was successfully erased. It is appreciated that in some embodiments, other keys stored on the device may be used to generate and issue the certificate.” The reasons for combination described within the rejection of claim 3 is similarly applied.).
Regarding claim 13, OOWADA-AWAN teaches:
The memory system according to claim 11, wherein the controller is configured to: in response to receiving a first request from a first host, execute the data erase operation, the first request requesting the data erase operation on the plurality of first storage areas OOWADA [0002-0003] “Users of non-volatile memory can program (e.g., write) data to the non-volatile memory and later read that data back… All or portions of the non-volatile memory can also be erased. For example, if data becomes stale or is no longer needed, the portion of the non-volatile memory storing the stale or no-longer-needed data can be erased so that the portion of the non-volatile memory can be available for storing new data. Alternatively, the erasing can be used to write data; for example, program from a first state to a second state and erase back to the first state (or between more than two states).”, [0032] “In one embodiment, a control circuit connected to a group of non-volatile memory cells is configured to erase the group of non-volatile memory cells…”, [0037] “Processor 156 performs the various controller memory operations, such as programming, erasing, reading, as well as memory management processes.”) and generation of the erase certificate; and in response to the completion of the data erase operation, generate the erase certificate(AWAN [0034] “At step 330, in response to erasing the content, the device may generate and issue a certificate of erasure. For example, in a storage device, a root key for the storage device may be used to generate and issue a certificate indicating that the content was successfully erased. It is appreciated that in some embodiments, other keys stored on the device may be used to generate and issue the certificate.” One of ordinary skill in the art would appreciate certificating the successful erasure of data through a cryptographic erase process in accordance with an erase command would thereby include confirmation for compliance of said process. As demonstrated by OOWADA, the number of erase cycles can determine a particular erase process. In certifying such an erasure process, it would be obvious for one of ordinary skill in the art to include erase cycle information as authentication information within an erase certificate, such as taught by AWAN, especially when the mode of erasure process is determined by said erase cycle information.).
Regarding claim 16, OOWADA-AWAN teaches:
The memory system according to claim 11, wherein the information includes: a sum of the numbers of program/erase cycles for the respective first storage areas before the data erase operation is executed; and a sum of the numbers of program/erase cycles for the respective first storage areas after the data erase operation is completed (OOWADA [0123] “Step 1302 is performed when the memory is new and has experienced less program/erase cycles (i.e. beginning of life or BOL). The population of memory cells may be a block, multiple blocks, a die, a portion of a block, or other grouping. In step 1304, the memory system performs a second method of erase for the same population of memory cells. Step 1304 is performed when the memory has experienced many (e.g., >3K) program/erase cycles (i.e. middle of life [MOL] or end of life [EOL]). The first method of erase is different than the second method of erase.”).
Regarding claim 17, OOWADA-AWAN teaches:
The memory system according to claim 11, wherein the information includes: the number of program/erase cycles for each of the first storage areas before the data erase operation is executed; and the number of program/erase cycles for each of the first storage areas after the data erase operation is completed(OOWADA [0123] “Step 1302 is performed when the memory is new and has experienced less program/erase cycles (i.e. beginning of life or BOL). The population of memory cells may be a block, multiple blocks, a die, a portion of a block, or other grouping. In step 1304, the memory system performs a second method of erase for the same population of memory cells. Step 1304 is performed when the memory has experienced many (e.g., >3K) program/erase cycles (i.e. middle of life [MOL] or end of life [EOL]). The first method of erase is different than the second method of erase.”).
Regarding claim 18, OOWADA-AWAN teaches:
The memory system according to claim 11, wherein the information includes: at least one of a maximum value and a minimum value of the numbers of program/erase cycles for the respective first storage areas before the data erase operation is executed, and at least one of a maximum value and a minimum value of the numbers of program/erase cycles for the respective first storage areas after the data erase operation is completed(OOWADA [0131] “If not all memory cells of all NAND strings have successfully passed erase verification then in step 1714 it is determined whether the number of iterations of the erase process has reached the maximum number of iterations (i<iMax). If the number of iterations (i) of the erase process has reached the maximum number of iterations (iMax), then the erase has failed (1716). In one embodiment, iMax=6. In one embodiment the value of iMax is stored in parameters 318 (see FIG. 2). If the number of iterations of the erase process has not reached the maximum number of iterations, then the erase process continues at step 1718 during which the erase voltage signal VERA is stepped up to the next magnitude.”).
Regarding claim 19, OOWADA-AWAN teaches:
The memory system according to claim 11, wherein the information further includes one or more parameters related to a degree of wear-out of the nonvolatile memory (OOWADA [0123] “Step 1302 is performed when the memory is new and has experienced less program/erase cycles (i.e. beginning of life or BOL). The population of memory cells may be a block, multiple blocks, a die, a portion of a block, or other grouping. In step 1304, the memory system performs a second method of erase for the same population of memory cells. Step 1304 is performed when the memory has experienced many (e.g., >3K) program/erase cycles (i.e. middle of life [MOL] or end of life [EOL]). The first method of erase is different than the second method of erase.”.
Regarding claim 20, OOWADA-AWAN teaches:
The memory system according to claim 11, wherein the nonvolatile memory includes a plurality of blocks, and each of the first storage areas includes one or more blocks on which the data erase operation is executable in parallel, among the plurality of blocks (OOWADA [0123] “Step 1302 is performed when the memory is new and has experienced less program/erase cycles (i.e. beginning of life or BOL). The population of memory cells may be a block, multiple blocks, a die, a portion of a block, or other grouping. In step 1304, the memory system performs a second method of erase for the same population of memory cells. Step 1304 is performed when the memory has experienced many (e.g., >3K) program/erase cycles (i.e. middle of life [MOL] or end of life [EOL]). The first method of erase is different than the second method of erase.”).
Claim(s) (2, 4-5) and (12, 14-15) is/are rejected under 35 U.S.C. 103 as being unpatentable over OOWADA in view of AWAN as applied to claim 1 in further view of UMESAWA (US 20210223968 A1).
Regarding claim 2, OOWADA-AWAN teaches the memory system according to claim 1. OOWADA-AWAN does not explicitly teach, but in a related art UMESAWA teaches:
wherein the nonvolatile memory further includes a second storage area that stores a signature key (UMESAWA [0189] “The certificate issuing module 214 encrypts the calculated hash value 402 with a private key 404 to acquire the digital signature 403. The private key 404 is, for example, an RSA private key. The private key 404 may be stored in the secure microcomputer 7 before the shipment of the secure microcomputer 7 or may be generated by the secure microcomputer 7.”),
and the controller is further configured to: generate log data related to the executed data erase operation (UMESAWA [0082] “The certificate issuing module 214 assigns a digital signature to log data, which is generated when the cryptographic erase process is executed,”);
generate auxiliary information for managing the erase certificate (UMESAWA [0082] “The certificate issuing module 214 assigns a digital signature to log data, which is generated when the cryptographic erase process is executed”);
calculate a hash value of certification data that includes the first information, the second information, the log data, and the auxiliary information (UMESAWA [0189] “In addition, the host 2 decrypts the digital signature 403 assigned to the electronic certificate 500 with a public key 505 of the secure microcomputer 7 to calculate a hash value 504 (hereinafter, referred to as a second hash value 504).”; generate a digital signature for the certification data by using the hash value and the signature key (UMESAWA [0189] The certificate issuing module 214 calculates a hash value 402 of the erase log 401. The certificate issuing module 214 encrypts the calculated hash value 402 with a private key 404 to acquire the digital signature 403.); and generate the erase certificate that includes the certification data and the digital signature (UMESAWA [0034] “At step 330, in response to erasing the content, the device may generate and issue a certificate of erasure. For example, in a storage device, a root key for the storage device may be used to generate and issue a certificate indicating that the content was successfully erased. It is appreciated that in some embodiments, other keys stored on the device may be used to generate and issue the certificate.”).
Since OOWADA-AWAN and UMESAWA are from the same field of endeavor as both are directed to secure memory functions, which is within the same field of endeavor as the claimed invention, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to modify and combine the teachings of OOWADA-AWAN by incorporating the teachings of UMESAWA into OOWADA-AWAN. The motivation to combine is to improve secure erasure and verification thereof. (OOWADA [AB]; AWAN [AB]; UMESAWA [AB]).
Regarding claim 4, OOWADA-AWAN teaches the limitations of claim 3. OOWADA-AWAN in further view of UMESAWA teaches:
The memory system according to claim 3, wherein the controller is further configured to, in response to the generation of the erase certificate, transmit a response to the first request to the first host, the response indicating that the erase certificate has been generated (UMESAWA [0198] “The secure microcomputer 7 may transmit the electronic certificate 500 to which the digital signature 403 is assigned to, for example, the host 2.” One of ordinary skill in the art would appreciate that transmitting an erase certificate would inherently indicate that the erase certificate has been generated.).
Regarding claim 5, OOWADA-AWAN teaches the limitations of claim 1. OOWADA-AWAN in further view of UMESAWA teaches:
The memory system according to claim 1, wherein the controller is further configured to, in response to receiving a second request from a second host, transmit the erase certificate in a response to the second request to the second host, the second request requesting issuance of the erase certificate (UMESAWA [0200] “Note that the electronic certificate 500 may be issued by the memory controller 4 of the SSD 3. For example, when the SSD 3 is discarded, the memory controller 4 may erase the OTP key information 161 in response to receiving a key information erase command from the host 2. “, UMESAWA [0198] “Then, the secure microcomputer 7 issues the electronic certificate 500 to which the digital signature 403 is assigned (step S125). The secure microcomputer 7 may transmit the electronic certificate 500 to which the digital signature 403 is assigned to, for example, the host 2.”).
Regarding claim 12, OOWADA-AWAN in view of UMESAWA teaches:
The memory system according to claim 11, wherein the nonvolatile memory further includes a second storage area that stores a signature key (UMESAWA [0189] “The certificate issuing module 214 encrypts the calculated hash value 402 with a private key 404 to acquire the digital signature 403. The private key 404 is, for example, an RSA private key. The private key 404 may be stored in the secure microcomputer 7 before the shipment of the secure microcomputer 7 or may be generated by the secure microcomputer 7.”),
and the controller is further configured to: generate log data related to the executed data erase operation (UMESAWA [0082] “The certificate issuing module 214 assigns a digital signature to log data, which is generated when the cryptographic erase process is executed,”);
generate auxiliary information for managing the erase certificate (UMESAWA [0082] “The certificate issuing module 214 assigns a digital signature to log data, which is generated when the cryptographic erase process is executed”);
calculate a hash value of certification data that includes the information, the log data, and the auxiliary information (UMESAWA [0189] “In addition, the host 2 decrypts the digital signature 403 assigned to the electronic certificate 500 with a public key 505 of the secure microcomputer 7 to calculate a hash value 504 (hereinafter, referred to as a second hash value 504).”; generate a digital signature for the certification data by using the hash value and the signature key (UMESAWA [0189] The certificate issuing module 214 calculates a hash value 402 of the erase log 401. The certificate issuing module 214 encrypts the calculated hash value 402 with a private key 404 to acquire the digital signature 403.); and generate the erase certificate that includes the certification data and the digital signature (UMESAWA [0034] “At step 330, in response to erasing the content, the device may generate and issue a certificate of erasure. For example, in a storage device, a root key for the storage device may be used to generate and issue a certificate indicating that the content was successfully erased. It is appreciated that in some embodiments, other keys stored on the device may be used to generate and issue the certificate.”).
Regarding claim 14, OOWADA-AWAN in view of UMESAWA teaches:
The memory system according to claim 13, wherein the controller is further configured to, in response to the generation of the erase certificate, transmit a response to the first request to the first host, the response indicating that the erase certificate has been generated (UMESAWA [0198] “The secure microcomputer 7 may transmit the electronic certificate 500 to which the digital signature 403 is assigned to, for example, the host 2.” One of ordinary skill in the art would appreciate that transmitting an erase certificate would inherently indicate that the erase certificate has been generated.).
Regarding claim 15, OOWADA-AWAN in view of UMESAWA teaches:
The memory system according to claim 11, wherein the controller is further configured to, in response to receiving a second request from a second host, transmit the erase certificate in a response to the second request to the second host, the second request requesting issuance of the erase certificate (UMESAWA [0200] “Note that the electronic certificate 500 may be issued by the memory controller 4 of the SSD 3. For example, when the SSD 3 is discarded, the memory controller 4 may erase the OTP key information 161 in response to receiving a key information erase command from the host 2. “, UMESAWA [0198] “Then, the secure microcomputer 7 issues the electronic certificate 500 to which the digital signature 403 is assigned (step S125). The secure microcomputer 7 may transmit the electronic certificate 500 to which the digital signature 403 is assigned to, for example, the host 2.”).
CONCLUSION
The prior art of record and not relied upon is considered pertinent to the applicant’s disclosure:
SANUKI; Tomoya US 20240428875 A1 CHIP HEAT TREATMENT SYSTEM ([AB] “A system includes a rack, a heat treatment device configured to perform a heat treatment, one or more conveyance devices, and a host. The host is configured to determine a target memory chip to be subjected to the heat treatment by the heat treatment device among memory chips in a plurality of drives mounted on the rack, and disable communication with a target drive on which the target memory chip is mounted. The host is configured to control the conveyance devices to dismount the target drive from the rack, detach a component including the target memory chip from the target drive, convey the detached component to the heat treatment device, reattach the component including the target memory chip that has undergone the heat treatment to a drive, and mount the drive with the component including the target memory chip that has undergone the heat treatment on the rack.”)
DONGIEUX; Raynor US 20210182240 A1 INFORMATION DELETION ASSURANCE SYSTEM USING DISTRIBUTED LEDGER ([AB] “The technology disclosed herein facilitates the providing assurance for deletion of information from client systems using a distributed ledger network. One or more implementations disclosed herein provide using a user interface (UI) client to allow users to upload and delete information and a rest application programming interface (API) communicatively connected to the distributed ledger network logs the uploading and/or deletion of the information.”)
Chandramouli; Subramanyam US 20070150645 Method, System And Apparatus For Power Loss Recovery To Enable Fast Erase Time ([AB] “Data loss or system corruption due to a power loss in non-volatile memory may be prevented by tracking block status information in block headers and/or in a mini-array comprised of non-volatile memory cells. The block status may be tracked and managed during block allocate, deallocate, and erase operations in order to allow the memory to remain coherent if a power failure occurs.”
Takizawa; Kazutaka US 20180286485 A1 MEMORY SYSTEM CONTROLLING DATA ERASE FOR NONVOLATILE MEMORY AND CONTROL METHOD FOR ERASING DATA ([AB] “According to one embodiment, a memory system includes a memory and controller. The controller repeatedly performs an erase voltage application process for data stored in a target area in the memory. The controller performs an erase verification process for determining whether the erase is successful using erase verification voltage. The controller determines whether an erase time is longer than a first threshold value. The controller sets the target area to a use prohibition state when the erase time is longer than the first threshold value.”
Song; Paul Jei-zen US 5978275 A Erase And Program Control State Machines For Flash Memory ([AB] “An erase state machine controls the process of erasing all the memory cells in a selected sector of a flash memory array. The erase state machine includes a sequence of states for controlling generation of high positive and negative voltages, and application of the high positive voltage to all word lines in the selected sector and application of the high negative voltage to the source nodes of all memory cells in the selected sector. A sequence of two discharge states are used to discharge the high voltages from the word lines and source nodes. If an erase operation is aborted while high voltages are being generated, the erase state machine asynchronously transitions to the first of the two discharge states, and then transitions to the second discharge state and then back to a final inactive state during successive state machine clock cycles. Further, the erase state machine simultaneously checks all the cells in the selected sector to see if they are fully erased, without having to use a repeating loop of states for that purpose. The program state machine controls the programming of one page of flash memory cells. It enables the use of N/2.sup.k programming bit latches in the memory array, instead of a full set of N programming bit latches, where N is the number of columns in the memory array and k is a positive integer, thereby alleviating the space constraints normally imposed on programming bit latches in flash memory devices.”)
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/K.J.G./Examiner, Art Unit 2408
/LINGLAN EDWARDS/Supervisory Patent Examiner, Art Unit 2408