Prosecution Insights
Last updated: October 23, 2026
Application No. 18/822,835

MEMORY SYSTEM GENERATING ERASE CERTIFICATE

Non-Final OA §102
Filed
Sep 03, 2024
Priority
Sep 06, 2022 — continuation of PCTJP2022033420
Examiner
GILLESPIE, KAMRYN JORDAN
Art Unit
2408
Tech Center
2400 — Computer Networks
Assignee
KIOXIA Corporation
OA Round
3 (Non-Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
5m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
25 granted / 33 resolved
+17.8% vs TC avg
Strong +17% interview lift
Without
With
+17.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
16 currently pending
Career history
51
Total Applications
across all art units

Statute-Specific Performance

§101
7.1%
-32.9% vs TC avg
§103
53.5%
+13.5% vs TC avg
§102
22.8%
-17.2% vs TC avg
§112
15.0%
-25.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 33 resolved cases

Office Action

§102
DETAILED ACTION This communication is in response to applicant' s response filed on 09/08/2026. Claims 1-20 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claim(s) 11-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Allowable Subject Matter Claims 1-10 remain allowed. Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 11 & 13-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Satpathy (US 20230336537 A1), hereafter Satpathy. 11. (Currently Amended) A memory system (SATPATHY [0006] “and a memory system that is coupled to the processing system”) comprising: a nonvolatile memory that includes a plurality of first storage areas each configured to store user data(SATPATHY [0002] “In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.” [0022] “For purposes of this disclosure, an information handling system may include any instrumentality or aggregate of instrumentalities operable to compute, calculate, determine, classify, process, transmit, receive, retrieve, originate, switch, store, display, communicate, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, or other purposes. For example, an information handling system may be a personal computer (e.g., desktop or laptop), tablet computer, mobile device (e.g., personal digital assistant (PDA) or smart phone), server (e.g., blade server or rack server), a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The information handling system may include random access memory (RAM), one or more processing resources such as a central processing unit (CPU) or hardware or software control logic, ROM, and/or other types of nonvolatile memory.”); and a controller configured to: in response to a command from a host, execute a data erase operation on each of the plurality of first storage areas(SATPATHY [0040] “As discussed in some of the specific examples below, component lifetimes may be expressed in terms of an amount of usage (e.g., 3000 program/erase cycles, or 2000 hours at peak voltage), as well as other component lifetime factors that would be apparent to one of skill in the art in possession of the present disclosure.”, [0068] “the applicable component lifetime parameter for a storage device may be a particular number of write cycles (e.g., 3,000 program/erase cycles). The component monitoring engine 404 poll the storage device to determine its current lifetime (e.g., 3,100 program/erase cycles)”); in response to completion of the data erase operation, acquire information related to at least the number of program/erase cycles for at least one of the plurality of first storage areas after the data erase operation is executed(SATPATHY [0068] “The component monitoring engine 404 poll the storage device to determine its current lifetime (e.g., 3,100 program/erase cycles) and then determine that the storage device has exceeded the applicable component lifetime. The foregoing process for determining whether a component has exceeded a component lifetime may be performed by the computing device 208/400 periodically (e.g., hourly, daily, weekly, or some other set interval) and/or in conjunction with other operations of the computing device 208/400”); and generate an erase certificate that includes at least the information(SATPATHY [0048] “the certificate generation system may modify an existing component verification certificate (e.g., an initial component verification certificate generated by a computing device manufacturer) to include the newly added components and corresponding component lifetimes.”). 13. (Original) The memory system according to claim 11, wherein the controller is configured to: in response to receiving a first request from a first host, execute the data erase operation(SATPATHY [0048] “For example, a reseller may customize a computing device and may use a certificate generation system of the reseller to generate an additional component verification certificate to capture these changes.”, [0022] “he information handling system may include random access memory (RAM), one or more processing resources such as a central processing unit (CPU) or hardware or software control logic, ROM, and/or other types of nonvolatile memory.”, [0068] “As another example, the applicable component lifetime parameter for a storage device may be a particular number of write cycles (e.g., 3,000 program/erase cycles). The component monitoring engine 404 poll the storage device to determine its current lifetime (e.g., 3,100 program/erase cycles) and then determine that the storage device has exceeded the applicable component lifetime.), the first request requesting the data erase operation on the plurality of first storage areas and generation of the erase certificate(SATPATHY [0048] “For example, a reseller may customize a computing device and may use a certificate generation system of the reseller to generate an additional component verification certificate to capture these changes.”); and in response to the completion of the data erase operation, generate the erase certificate(SATPATHY [0068] “The component monitoring engine 404 poll the storage device to determine its current lifetime (e.g., 3,100 program/erase cycles) and then determine that the storage device has exceeded the applicable component lifetime. The foregoing process for determining whether a component has exceeded a component lifetime may be performed by the computing device 208/400 periodically (e.g., hourly, daily, weekly, or some other set interval) and/or in conjunction with other operations of the computing device 208/400”, [0042] “In some embodiments, the certificate generation engine 304 may request and receive the component lifetime parameters from the policy administration system 214 or a component manufacturer system (not illustrated). For example, the certificate generation engine 304may invoke an outward facing service (e.g., via the communication system 308 and through network 204) provided by the policy administration system 214 or a component manufacturer system (not illustrated) that returns this information.”). 14. (Original) The memory system according to claim 13, wherein the controller is further configured to, in response to the generation of the erase certificate, transmit a response to the first request to the first host, the response indicating that the erase certificate has been generated(SATPATHY [0058] “The computing device 208/400, for example, may transmit the existing component verification certificate to the certificate generation system 206 as part of a change request. Alternatively, where the change request was initiated by another entity (e.g., the certificate generation system 206 itself, or policy administration system 214),”). 15. (Original) The memory system according to claim 11, wherein the controller is further configured to, in response to receiving a second request from a second host, transmit the erase certificate in a response to the second request to the second host, the second request requesting issuance of the erase certificate(SATPATHY [0058] “As noted above, in alternative embodiments, the certificate generation engine 304 may operate to generate an additional component verification certificate by modifying an existing component verification certificate (e.g., an initial component verification certificate generated by a computing device manufacturer). In such cases, the certificate generation engine 304 may operate to receive the existing component verification certificate from network 204 via the communication system 308. The computing device 208/400, for example, may transmit the existing component verification certificate to the certificate generation system 206 as part of a change request. Alternatively, where the change request was initiated by another entity (e.g., the certificate generation system 206 itself, or policy administration system 214), the certificate generation engine 304 may transmit a request to the computing device 208/400 over network 204 via communication system 308 requesting the existing component verification certificate, and may receive the existing component verification certificate from the computing device 208/400 over network 204 via communication system 308 in response.”). 16. (Original) The memory system according to claim 11, wherein the information includes: a sum of the numbers of program/erase cycles for the respective first storage areas before the data erase operation is executed (SATPATHY [0040] “For example, component manufacturers may provide components with default recommended lifetimes after which they recommend those components be replaced, and those default recommended lifetimes may be available to the computing device manufacturer for use as the component lifetime information…As discussed in some of the specific examples below, component lifetimes may be expressed in terms of an amount of usage (e.g., 3000 program/erase cycles, or 2000 hours at peak voltage), as well as other component lifetime factors that would be apparent to one of skill in the art in possession of the present disclosure.”); and a sum of the numbers of program/erase cycles for the respective first storage areas after the data erase operation is completed(SATPATHY [0068] “The component monitoring engine 404 may compare this against a current date (e.g., Apr. 1, 2022) and determine that the power supply unit has exceeded the applicable component lifetime. As another example, the applicable component lifetime parameter for a storage device may be a particular number of write cycles (e.g., 3,000 program/erase cycles). The component monitoring engine 404 poll the storage device to determine its current lifetime (e.g., 3,100 program/erase cycles) and then determine that the storage device has exceeded the applicable component lifetime.). 17. (Original) The memory system according to claim 11, wherein the information includes: the number of program/erase cycles for each of the first storage areas before the data erase operation is executed(SATPATHY [0040] “For example, component manufacturers may provide components with default recommended lifetimes after which they recommend those components be replaced, and those default recommended lifetimes may be available to the computing device manufacturer for use as the component lifetime information…As discussed in some of the specific examples below, component lifetimes may be expressed in terms of an amount of usage (e.g., 3000 program/erase cycles, or 2000 hours at peak voltage), as well as other component lifetime factors that would be apparent to one of skill in the art in possession of the present disclosure.”); and the number of program/erase cycles for each of the first storage areas after the data erase operation is completed (SATPATHY [0068] “The component monitoring engine 404 may compare this against a current date (e.g., Apr. 1, 2022) and determine that the power supply unit has exceeded the applicable component lifetime. As another example, the applicable component lifetime parameter for a storage device may be a particular number of write cycles (e.g., 3,000 program/erase cycles). The component monitoring engine 404 poll the storage device to determine its current lifetime (e.g., 3,100 program/erase cycles) and then determine that the storage device has exceeded the applicable component lifetime.). 18. (Original) The memory system according to claim 11, wherein the information includes: at least one of a maximum value and a minimum value of the numbers of program/erase cycles for the respective first storage areas before the data erase operation is executed, and at least one of a maximum value and a minimum value of the numbers of program/erase cycles for the respective first storage areas after the data erase operation is completed(SATPATHY [0068] “The component monitoring engine 404 may then perform component lifetime assessment operations to determine whether any computing device component 410 of the computing device 208/400 has exceeded the applicable component lifetime parameters for that component. In doing so, the component monitoring engine 404 may perform current lifetime operations 904 to determine a current lifetime of a computing device component 410… As another example, the applicable component lifetime parameter for a storage device may be a particular number of write cycles (e.g., 3,000 program/erase cycles). The component monitoring engine 404 poll the storage device to determine its current lifetime (e.g., 3,100 program/erase cycles) and then determine that the storage device has exceeded the applicable component lifetime.”). 19. (Original) The memory system according to claim 11, wherein the information further includes one or more parameters related to a degree of wear-out of the nonvolatile memory(SATPATHY [0040] “As discussed in some of the specific examples below, component lifetimes may be expressed in terms of an amount of usage (e.g., 3000 program/erase cycles, or 2000 hours at peak voltage), as well as other component lifetime factors that would be apparent to one of skill in the art in possession of the present disclosure.”). 20. (Original) The memory system according to claim 11, wherein the nonvolatile memory includes a plurality of blocks, and each of the first storage areas includes one or more blocks on which the data erase operation is executable in parallel, among the plurality of blocks(SATPATHY [0022-0023] “For purposes of this disclosure, an information handling system may include any instrumentality or aggregate of instrumentalities operable to… process, transmit, receive, retrieve, originate, switch, store…handle, or utilize any form of information, intelligence, or data for business, scientific, control, or other purposes.”, “A system memory 114 is coupled to processor 102 to provide the processor with fast storage to facilitate execution of computer programs by processor 102. Examples of system memory may include random access memory (RAM) devices such as dynamic RAM (DRAM), synchronous DRAM (SDRAM), solid state memory devices, and/or a variety of other memory devices known in the art.” Dual ported RAM is a random access memory known within the art to support parallel processing through the use of distinct ports.). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kamryn Gillespie whose telephone number is 703-756-5498. The examiner can normally be reached on Monday through Thursday from 9am to 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Linglan Edwards can be reached on (571) 270-5440. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.J.G./Examiner, Art Unit 2408 /LINGLAN EDWARDS/Supervisory Patent Examiner, Art Unit 2408
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Prosecution Timeline

Sep 03, 2024
Application Filed
Feb 09, 2026
Non-Final Rejection mailed — §102
Apr 07, 2026
Applicant Interview (Telephonic)
Apr 10, 2026
Examiner Interview Summary
Apr 23, 2026
Response Filed
Jul 08, 2026
Final Rejection mailed — §102
Sep 08, 2026
Response after Non-Final Action
Oct 02, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
93%
With Interview (+17.3%)
2y 7m (~5m remaining)
Median Time to Grant
High
PTA Risk
Based on 33 resolved cases by this examiner. Grant probability derived from career allowance rate.

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