Prosecution Insights
Last updated: October 02, 2026
Application No. 18/822,953

MULTILAYER ELECTRONIC COMPONENT

Final Rejection §103
Filed
Sep 03, 2024
Priority
Oct 05, 2023 — RE 10-2023-0132538
Examiner
FERGUSON, DION
Art Unit
2848
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electro-Mechanics Co., Ltd.
OA Round
2 (Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
889 granted / 1022 resolved
+19.0% vs TC avg
Moderate +8% lift
Without
With
+8.2%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
28 currently pending
Career history
1038
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
51.3%
+11.3% vs TC avg
§102
29.3%
-10.7% vs TC avg
§112
7.7%
-32.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1022 resolved cases

Office Action

§103
DETAILED ACTION Response to Arguments Applicant’s arguments with respect to claims 1-12 and 15 have been considered but are moot in light of the new grounds of rejection set forth below, necessitated by Applicant’s amendment. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-4, 6, 12, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pat. App. Pub. No. 2023/0094110) in view of Lee et al. (US Pat. App. Pub. No. 2023/0282420). With respect to claim 1, Kim teaches a multilayer electronic component (see abstract), comprising: a body including a dielectric layer and internal electrodes alternately disposed with the dielectric layer (see FIG. 2, body 110, dielectric layers 111, internal electrodes 121/122, and paragraph [0037]); an interface plating layer disposed on an end of at least one of the internal electrodes (see FIG. 8, interface plating layers 131, and paragraphs [0048] and [0052]); and an external electrode disposed to contact at least a portion of an end of the dielectric layer and to cover the interface plating layer (see FIG. 8, electrode layer 132), wherein the external electrode includes a conductive resin layer including a conductive metal and a resin (see FIG. 8, resin 132a and conductive metal 132b, and paragraph [0055]), the conductive metal included in the conductive resin layer includes a plurality of metal particles and a first intermetallic compound connecting at least a portion of the plurality of metal particles (see FIG. 8 and paragraph [0059]), the plurality of the metal particles include Ag and/or Cu (see paragraphs [0057] and [0059]). Kim further teaches that the conductive paste layer may include a copper-tin alloy, but fails to explicitly teach that the first intermetallic compound includes one or more of Cu6Sn5 and Cu3Sn. Lee, on the other hand, teaches that that the first intermetallic compound includes one or more of Cu6Sn5 and Cu3Sn, and further, that an intermetallic compound of Cu6Sn5 and Cu3Sn is a known substitute for Ag3Sn, if the conductive particles in the conductive resin layer are Cu particles. See paragraph [0123]. Accordingly, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the invention, to modify Kim, as taught by Lee, as one of Cu6Sn5 and/or Cu3Sn is a known substitute for Ag3Sn, when the conductive resin layer particles are Cu. With respect to claim 2, the combined teachings of Kim and Lee teach that the body includes a groove portion in which the end of the internal electrode is spaced apart from one surface of the body, and the interface plating layer includes a first region disposed in the groove portion and a second region protruding from one surface of the body. See Kim, FIG. 8, noting that element 131a fills a groove in body 110, and paragraph [0084]. With respect to claim 3, the combined teachings of Kim and Lee teach that the internal electrodes are alternately disposed with the dielectric layer in a first direction (see Kim, FIG. 2, element 121/122, and paragraph [0040]), and the body includes first and second surfaces opposing each other in the first direction, third and fourth surfaces connected to the first and second surfaces and opposing each other in a second direction, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other in a third direction in first and second directional cross-sections of the multilayer electronic component (see Kim, FIG. 1 and paragraphs [0034]-[0036]), the second region of the interface plating layer has a semicircular shape (see Kim, FIG. 8, element 131b). With respect to claim 4, the combined teachings of Kim and Lee teach that when an average thickness of the internal electrode is te, an average thickness of the dielectric layer is td, and a radius of the semicircular shape is referred to as r, te/2 ≤ r ≤ (te+td)/2 is satisfied. See Kim, FIG. 8, noting that element 131b is larger than te, and that 131b is smaller than (te+td)/2; see also, paragraphs [0039] and [0044], and [0070]. With respect to claim 6, the combined teachings of Kim and Lee teach that the body includes a plurality of the interface plating layers, each of the plurality of the interface plating layer is spaced apart from each other. See Kim, FIG. 8, noting multiple elements 131 are disposed on the surface. With respect to claim 12, the combined teachings of Kim and Lee teach that the conductive metal included in the conductive resin layer includes one or more of Cu, Ag, Sn, and alloys thereof. See Kim, paragraph [0080]. With respect to claim 15, the combined teachings of Kim and Lee teach that a second intermetallic compound is disposed in an interface between the interface plating layer and the external electrode, and the second intermetallic compound includes Ni and Sn. See Kim, FIG. 8, element 133, and paragraph [0069]. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pat. App. Pub. No. 2023/0094110) in view of Lee et al. (US Pat. App. Pub. No. 2023/0282420), and further, in view of Zenzai et al. (US Pat. App. Pub. No. 2013/0106560). With respect to claim 5, the combined teachings of Kim and Lee fail to explicitly teach that a radius of the semicircular shape is 4 μm or less. Zenzai, on the other hand, teaches that a connecting portion disposed between the inner and outer electrodes has a radius greater than 2.4 μm. See paragraph [0010]. Such an arrangement results in a high bonding strength between the inner and outer electrodes. See paragraph [0009]. Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify the combined teachings of Kim and Lee, as taught by Zenzai, in order to provide a high bonding strength between the inner and outer electrodes. Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pat. App. Pub. No. 2023/0094110) in view of Lee et al. (US Pat. App. Pub. No. 2023/0282420), and further, in view of Sasabayashi et al. (US Pat. App. Pub. 2014/0293503). With respect to claim 7, the combined teachings of Kim and Lee fail to teach that the interface plating layer has an amorphous structure. Sasabayashi, on the other hand, teaches the use of an amorphous Ni-P plating layer disposed between an internal electrode and an external electrode. See FIG. 4, element 20, and paragraph [0072]. Such an arrangement results in a high anchoring effect. See paragraph [0072]. Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify the combined teachings of Kim and Lee, as taught by Sasabayashi, in order to provide a high anchoring effect. With respect to claim 8, the combined teachings of Kim and Lee fail to teach that the interface plating layer includes Ni and P. Sasabayashi, on the other hand, teaches the use of an amorphous Ni-P plating layer disposed between an internal electrode and an external electrode. See FIG. 4, element 20, and paragraph [0072]. Such an arrangement results in a high anchoring effect. See paragraph [0072]. Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify the combined teachings of Kim and Lee, as taught by Sasabayashi, in order to provide a high anchoring effect. With respect to claim 9, the combined teachings of Kim, Lee, and Sasabayashi teach that a mass ratio of a P content to a Ni content included in the interface plating layer is 8% or more and 15% or less. See Sasabayashi, paragraph [0072], citing more than 9%. Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pat. App. Pub. No. 2023/0094110) in view of Lee et al. (US Pat. App. Pub. No. 2023/0282420), and further, in view of CN 116802757. With respect to claim 10, the combined teachings of Kim and Lee fail to teach that the interface plating layer includes Ni and B. CN ‘757, on the other hand, teaches a Ni-B plating layer. See element 15A and paragraph [0027]. Such an arrangement improves the electrical connection and reliability between the end face and the external electrode. See paragraph [0022]. Accordingly, it would have been obvious to one of ordinary skill in the art, at the effective filing date of the invention, to modify the combined teachings of Kim and Lee, as taught by CN ‘757, in order to improve the electrical connection and reliability between the end face and the external electrode. With respect to claim 11, the combined teachings of Kim, Lee, and CN ‘757 teach that a mass ratio of a B content to a Ni content included in the interface plating layer is 2.5% or more and 10% or less. See CN ‘757, paragraph [0027], citing 0.1 to 5.0% B. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DION R FERGUSON whose telephone number is (571)270-7566. The examiner can normally be reached Monday-Friday, 5:30 a.m. - 4:00 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole, can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DION R. FERGUSON/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Sep 03, 2024
Application Filed
Apr 01, 2026
Non-Final Rejection mailed — §103
Jul 01, 2026
Response Filed
Sep 11, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
95%
With Interview (+8.2%)
2y 1m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1022 resolved cases by this examiner. Grant probability derived from career allowance rate.

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