Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites the limitations "the memory" and “the application code”. There is insufficient antecedent basis for this limitation in the claim. Parent claim 16 does not recite a memory or application code.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5, 7, 9, 11, 12, 14, 16, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Refaeli et al. (US Patent Application Publication 2019/0171536, included in IDS dated April 18, 2025) hereinafter Refaeli, in view of Boettcher et al. (US Patent Application Publication 2020/0192742), hereinafter Boettcher.
Regarding claim 1, Refaeli teaches:
A hardware reconfiguration system for first and second devices in a lock-step configuration using a comparator that provides a lock-step error indication (Paragraph 0024), comprising:
a lock-step monitor that is configured to detect occurrences of the lock-step error (Paragraph 0024, the controller responds with further action to the lockstep error), and when the lock-step error occurs, to enter a repair state to determine which one of the first and second devices is operating correctly (Paragraphs 0035 and 0036, determining which core is faulty) and to reconfigure operation into a split-lock mode to resume operation using the one of the first and second devices that is operating correctly (Paragraphs 0039/0040, in the event of a hard error, the faulty core is disabled and the functioning core continues to operate).
Refaeli does not explicitly teach that the system comprises at least one register that stores a lock-step threshold, nor that the repair state is entered when the lock-step monitor finds the threshold is reached in a comparison between a count of occurrences of the lock-step error indication with the threshold.
Boettcher teaches a hardware reconfiguration system for a lock-step configuration (Abstract) comprising at least one register that stores a lock-step threshold (Paragraph 0235, the counters to store an error count may be internal registers in order to detect permanent faults); and
a lock-step monitor that is configured to compare a count of occurrences of the lock-step error indication from the comparator with the lock-step threshold (Paragraph 0217), and when the lock-step threshold is reached, to enter a repair state to determine which of the first and second devices is operating correctly (Paragraph 0230, the cores may identify the location of the fault and whether the state was compromised) and to reconfigure operation into a split-lock mode to resume operation using the one of the first and second devices that is operating correctly (Paragraph 0049/0217, the error handling circuitry may trigger switching processing from one processor to another in response to the error counter reaching a threshold).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to include an error threshold such as the one taught in Boettcher in the system of Refaeli. It would be obvious because it provides the benefit of detecting permanent faults that may require further correction and testing (Boettcher paragraph 0048). Refaeli already detects similar permanent faults (Refaeli paragraph 0033, hard errors refer to the same type of error as permanent errors in Boettcher). However, as explained by Boettcher, self-tests introduce an amount of complexity that increases integrity but lowers efficiency (Boettcher paragraph 0059). The threshold of Boettcher allows for the detection of permanent faults more effectively (Boettcher paragraph 0217). One of ordinary skill in the art would consider the tradeoff between reliability and efficiency when testing a permanent error after it is confirmed by the threshold system, rather than performing potentially extraneous self-tests. The threshold system would allow permanent faults, and the more extreme recovery methods they require, to be addressed, without increasing the load on soft faults.
Regarding claim 3, Refaeli in view of Boettcher as applied to claim 1 above teaches the hardware reconfiguration system of claim 1, wherein:
during the repair state the lock-step monitor is configured to disable the comparator (Refaeli paragraph 0026/0027, the FAULT signal causes ready signals for each core to de-assert, and the system transitions into an isolated safe mode. Although the compare unit is not expressly mentioned, it is clear that comparisons are not occurring at this step as per Refaeli Fig. 4) to initiate independent testing of the first and second devices (Refaeli paragraph 0035, MBIST and LBIST are performed), and to reconfigure operation in the split-lock mode to resume operation using one of the first and second devices that has passed the testing (Refaeli paragraph 0036, if MBIST or LBIST does not pass, it is a hard error. It follows that the device that did not experience a hard error passed MBIST and LBIST as in Refaeli paragraph 0040).
Regarding claim 5, Refaeli in view of Boettcher as applied to claim 1 above teaches the hardware reconfiguration system of claim 1, wherein the first and second devices comprise first and second processing cores (Refaeli Abstract, the devices are cores), further comprising:
a memory that stores application instructions for execution by the first and second processing cores during the lock-step configuration, wherein the memory further stores test instructions (Refaeli paragraph 0035, the interrupt service routine or other software routine to analyze the fault; Although software routines are known to be stored in a memory, Refaeli does not explicitly state where the routines are stored; Boettcher paragraph 0112 and 0125 explicitly recites a location of handler code that addresses the error. It is clear that the test routines of Refaeli would also be stored in memory)
wherein at least one register further stores a starting address of the test instructions (Boettcher paragraphs 0125/0126 and FIG. 5, the error handler’s address to perform the BNE fault_detected break instruction can be stored in a register);
wherein the lock-step monitor is further configured to direct the first and second processing cores to execute the test instructions located at the starting address when in the repair state to determine which of the first and second processing cores is operating correctly (Refaeli paragraph 0035, the interrupt causes each of the cores to perform testing).
Regarding claim 7, Refaeli in view of Boettcher as applied to claim 5 above teaches the hardware reconfiguration system of claim 5, wherein the lock-step monitor is further configured to resume operation in a split-lock mode by causing the correctly operating processing core that has passed the testing to begin executing the application instructions (Refaeli Abstract, the non-faulty core is allowed to execute instructions).
Regarding claim 9, Refaeli teaches that the comparator compares processing results of the first and second processors (Paragraph 0024).
Claim 9 otherwise recites similar language to claim 1, and is similarly rejected.
Claim 11 recites similar language to claim 3, and is similarly rejected.
Claim 12 recites similar language to claim 5, and is similarly rejected.
Claim 14 recites similar language to claim 7, and is similarly rejected.
Claim 16 recites similar language to claim 1, and is similarly rejected.
Claim 18 recites similar language to claim 3, and is similarly rejected.
Claim 20 recites similar language to claim 7, and is similarly rejected.
Claims 4, 8, 15 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Refaeli and Boettcher as applied to claim 1 above, and further in view of Quach (US Patent Application Publication 2004/0019771).
Regarding claim 4, Refaeli and Boettcher teach the hardware reconfiguration system of claim 1.
Refaeli and Boettcher do not teach that the lock-step monitor is further configured to provide a notification of reconfigured mode after resuming operation in the split-lock mode.
Quach teaches a notification of reconfigured mode after resuming operation in the split-lock mode (Paragraph 0051, a firmware-based recovery routine switches the processor to split mode. Paragraph 0052, the firmware-based recovery mechanism can notify higher-level systems).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to, after changing the system of Refaeli to a degraded mode, provide a notification as taught by Quach. It would be obvious because notifying a higher-level system can allow for the higher-level system to address issues that may not be covered by lower-level systems (Quach paragraph 0052). Additionally, one of ordinary skill in the art would understand that, given that the change to a degraded mode indicates damage to the system and a significant change in processing capability, it would be advantageous for the user to be aware of it.
Claim 8 recites similar language to claim 4, and is similarly rejected.
Claim 15 recites similar language to claim 4, and is similarly rejected.
Claim 19 recites similar language to claim 4, and is similarly rejected.
Claims 6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Refeali and Boettcher as applied to claim 1 above, and further in view of Dorsey (US Patent Application Publication 20030074618).
Regarding claim 6, Refaeli and Boettcher teach the hardware reconfiguration system of claim 5, wherein the first processing core updates the first test result value during the testing, wherein the second processing core updates the second test result value during the testing (Refeali paragraph 0035, MBIST and LBIST testing are performed on each core. The cores may operate independently according to Refaeli paragraph 0014), and wherein the lock-step monitor is further configured to consult the first and second test result values to identify results of the testing (Refeali paragraph 0036, the result of MBIST and LBIST is consulted to identify which core is faulty).
They do not explicitly teach that the test result values are stored in at least one register (Refeali and Boettcher do not teach implementation details of how test results are stored.).
Dorsey teaches a method for performing MBIST and LBIST wherein the results are stored in a register (Abstract, the MISR).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention that the results of the MBIST and LBIST tests of Refaeli would be stored in a register, as taught by Dorsey. It would be obvious because registers are a commonly known basic computer component for storing intermediate and final results of computations (Boettcher paragraphs 0031/0032, 0141, 0195, and 0235 discuss use cases for registers). One of ordinary skill in the art would understand that, given that the MBIST and LBIST tests need to store a final result, that a register would be an appropriate solution.
Claim 13 recites similar language to claim 6, and is similarly rejected.
Allowable Subject Matter
Claims 2, 10, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: With respect to prior art, Nakano et al. (US Patent Application Publication 2018/0046557) teaches a similar concept for lockstep processors, where the error correction stops resetting the system when resetting fails to resolve the fault (Paragraph 0149). However, this does not involve the use of a correction select value, nor does it specifically list a reset performed register. The claims recite specific conditions under which specific corrective actions are taken. A search of the prior art did not find a piece of prior art which taught a single system that performed recited corrective actions under all the recited conditions.
Conclusion
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/B.P.H./Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114