DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are:
controller in claim 1
clock management controller in claim 7
clock management controller module in claim 13
hardware based clock frequency adjustment module in claim 14
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1, 7, 13, and 14 recite the generic placeholders “controller” and “module” associated with various functions, and are rejected because the specification fails to provide adequate written description of structures corresponding to the functions as required for interpretation under 35 U.S.C. 112(f). The specification discloses a controller and CMC module in Fig. 4, and discloses that the controller is comprised of various modules. MPEP 2181(I)(A) indicates that “module” is a non-structural term, and therefore its use in the specification does not provide adequate description of structure. The modules are also not described as components known in the art to have a specified structure (e.g., a memory controller, a network interface, a SouthBridge). Nor does the specification teach that the controller is comprised of a processor programmed with instructions for executing the functions.
Claims 17-19 are additionally rejected because they recite a step of identifying a bottleneck in the HW modules. This function is not disclosed in the originally filed specification as being performed in the embodiment presently claimed. The present application is a divisional application of parent application no. 17/729,854 (issued as U.S. Patent No. 12,105,574) in which a restriction requirement set forth two species:
Species I, claims 1-10 and 18-20, directed to a controller configured to identify a bottleneck in one or more hardware modules and change a clock frequency of one or more of the hardware modules.
Species II, claims 11-17, directed to a controller configured to determine a hardware module with the smallest amount of messages in an input queue, set a first HW module to a first frequency, and set a second HW module to a second frequency lower than the first frequency.
Claims 1-7 of the present application are identical to the non-elected claims 11-17 in the ‘854 parent application. In the originally filed specification, the steps of determining a smallest amount of messages and setting a first and second HW module to respective frequencies are discussed solely in para. 0009 and para. 0044. Para. 0009 and 0044 are cursory descriptions that merely repeat the language of claims 1-7 and do not provide any indication that the bottleneck detection functions are associated with the steps of claims 1-7, as they are completely silent regarding the bottleneck detection functions. Additionally, the Examiner notes that the in remaining portions of the specification that discuss bottleneck detection, there is no teaching to indicate that determining a smallest amount of messages is part of the embodiment that detects bottlenecks. On the contrary, the specification suggests that detection of a bottleneck condition requires the determination of a largest number of messages in the input queue [para. 0036: “The product of the number of messages times the processing time for each HW module is compared, and the largest number is the bottleneck.“]1.
Given the specification’s compartmentalization of the bottleneck detection function from the steps for determining the smallest number of messages in the input queue, and the restriction requirement in the parent application indicating that these functions belong to separate species, the Examiner submits that the specification fails to disclose detecting a bottleneck and determining a smallest number of messages as being usable together in the same embodiment. The inclusion of claims 17-19 as dependent claims of claim 1 is therefore not supported by the specification.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1-20 invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function.
Claims 1, 7, 13, and 14 recite the generic placeholders “controller” and “module” associated with various functions, and are rejected because the specification fails to provide adequate written description of structures corresponding to the functions as required for interpretation under 35 U.S.C. 112(f). The specification discloses a controller and CMC module in Fig. 4, and discloses that the controller is comprised of various modules. MPEP 2181(I)(A) indicates that “module” is a non-structural term, and therefore its use in the specification does not provide adequate description of structure. The modules are also not described as components known in the art to have a specified structure (e.g., a memory controller, a network interface, a SouthBridge). Nor does the specification teach that the controller is comprised of a processor programmed with instructions for executing the functions. Therefore, the claims are indefinite and are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claims 1-20 are additionally rejected as being indefinite for the following language:
Claim 1, line 13, “the setting” and “the setting”: indefinite due to identical language referring to two different previously recited settings.
Claim 3, line 3, “the message”: lack of antecedent basis, inconsistent with previous limitations reciting a plurality of messages, unclear if a particular message is in view.
Claim 6, “where in setting the clock frequency for the second HW module comprises lowering the clock frequency by a percentage of the clock frequency from the clock frequency of the first HW module…”: unclear due to the recitation of multiple clock frequencies.
Claim 7, line 3, “the setting” and “the setting”: rejected on the same basis as claim 1.
Claim 11, line 1, “the other two HW modules”: lack of antecedent basis, unclear whether “the other two” includes the already-recited second HW module.
Claim 16, line 2, “the clock frequency of a third HW module”: lack of antecedent basis.
Claim 20, line 1, “the setting” and “the setting”: rejected on the same basis as claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8-11, 13-16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tidwell et al., U.S. Patent Application Publication No. 2019/0094938, in view of Thompson et al., U.S. Patent Application Publication No. 2019/0243578, in view of Peleg et al., U.S. Patent Application Publication No. 2012/0105876.
Regarding claim 1, Tidwell discloses a data storage device [Fig. 1] comprising:
a memory device [NVM 130]; and
a controller [central controller 110] coupled to the memory device, wherein the controller is configured to:
determine a number of messages pending [para. 0028: “…each channel controller 112 provides the central controller 110 with backlog information 308 of the memory commands pending in the command queue 134… the signal may indicate the number of memory commands pending in the command queue…”] in an input queue [command queue 134] of a plurality of hardware (HW) modules [channel controllers 112];
set a clock frequency for a first HW module of the plurality of HW modules to a first clock frequency setting [maximum frequency, para. 0036: “If the channel controller's clock frequency is below the maximum frequency, at block 608, the central controller 110 may utilize the DFS control block 116 to increase the clock frequency of the channel controller.”]2;
set a clock frequency for a second HW module of the plurality of HW modules to a second clock frequency setting, wherein the second clock frequency setting lower than the first clock frequency setting [para. 0037: “If the channel controller's clock frequency is above the minimum frequency, at block 612, the central controller 110 may utilize the DFS control block 116 to reduce the clock frequency of the channel controller.”] 3.
Tidwell does not teach a step to determine which HW module has the smallest amount of messages in the input queue. Additionally, while Tidwell teaches that the determining, the setting, and the setting comprise a closed-loop control process [para. 0030: “This close-loop power control process may be called reactive power management...”], Tidwell does not explicitly teach that the closed-loop control process is repeated after a predetermined period of time.
Thompson discloses a step to determine which HW module of a plurality of HW modules has the smallest amount of messages in the input queue [para. 0047: “…SSD controller 201 may send the calculated parity value to the non-volatile memory 205 using the memory channel that has the smallest number of pending commands 249 in channel command queue 231, 233, 235 or 237.”].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Tidwell and Thompson by modifying Tidwell to include a step to determine which HW module of a plurality of HW modules has the smallest amount of messages in the input queue, as taught by Thompson. Both Tidwell [para. 0003: “…one will understand how the aspects of various embodiments are used to manage power consumption in storage devices (e.g., solid-state drives, sometimes called SSDs).”] and Thompson [Fig. 1] are directed to SSD systems. Tidwell [Fig. 1] and Thompson [Fig. 2] also disclose analogous structures of a plurality of non-volatile memories (NVM) coupled to respective controllers with an input queue for commands directed to the NVMs, with each controller/queue/NVM combination representing a memory channel. Thompson teaches that in such a system, a reliability scheme may be used to protect against the loss of data during a power loss [para. 0047: “In one embodiment, SSD 200 may use a reliability scheme to protect against the loss of data upon a loss of a power, including any reliability scheme known in the art.”]. The reliability scheme taught by Thomson includes a step to determine which HW module of a plurality of HW modules has the smallest amount of messages in the input queue so as to use that HW module to send a calculated parity value to the associated NVM. Therefore it would have been obvious to one of ordinary skill in the art to apply the teachings of Thompson’s reliability scheme (including the sending of the parity value) to Tidwell’s invention based on Thompson’s teaching that such a scheme would protect against the loss of data during a power loss.
Peleg discloses a system that uses a closed-loop control process that is repeated after a predetermined period of time [para. 0017: “The process illustrated in FIGS. 2-4 can be repeated periodically at predetermined intervals, or even for each page so that the CPR error is continually or periodically checked and corrected, providing a closed-loop system.”].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Tidwell and Peleg by modifying Tidwell to repeat the closed-loop control process after a predetermined period of time, as taught by Peleg. Tidwell discloses a closed-loop control process, but does not explicitly disclose repeating the process. Peleg discloses that closed-loop control is achieved, in part, by periodically repeating the process at regular intervals so that control is continuously applied. It would therefore have been obvious to one of ordinary skill in the art to apply Peleg’s teaching to Tidwell based on Peleg’s teaching that closed-loop control is achieved by periodically repeating at regular intervals to provide continuous control.
Regarding claim 8, Tidwell teaches that the plurality of HW modules comprise three HW modules [Fig. 1: four channel controllers].
Regarding claim 9, Tidwell teaches that the controller further comprises two sub-modules [central controller 110 includes clock generator 114, DFS control 116, host interface 118, memory command processor 120, and power credit allocation 124].
Regarding claim 10, Tidwell teaches that the two sub-modules are connected to the first HW module [DFS control 116, memory command processor 120, and power credit allocation 124 are coupled to channel controllers].
Regarding claim 11, Tidwell teaches that the other two HW modules operate at a different clock frequency that the first module. Fig. 6 indicates that a channel controller may operate at a maximum frequency, a minimum frequency, or a frequency between the maximum and minimum (i.e., a frequency increase or decrease implies an in-between frequency value).
Regarding claim 13, Tidwell discloses that the controller further comprises a clock management controller module [DFS control 116; para. 0020: “The DFS control block 116 can generate a frequency scale factor signal that dynamically controls the clock frequency of the clock generator 114.”].
Regarding claim 14, Tidwell discloses that the clock management controller module comprises a hardware based clock frequency adjustment module [para. 0020].
Regarding claim 15, Tidwell discloses that the hardware based clock frequency adjustment module is configured to receive inputs from each HW module [Fig. 1: DFS control 116 receives inputs from command queue 134].
Regarding claim 16, Tidwell discloses that the controller is further configured to decrease the clock frequency of a third HW module of the plurality of HW modules [Fig. 6, step 612: reduce frequency of channel controller clock].
Regarding claim 20, Tidwell teaches that the setting and the setting are performed dynamically [para. 0019: “…a dynamic frequency scaling (DFS) control block 116…”].
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Tidwell in view of Thompson in view of Peleg as applied to claim 1 above, and further in view of Iwai et al., U.S. Patent Application Publication No. 2019/0303024.
Regarding claim 2, Tidwell, Thompson, and Peleg disclose the device of claim 1, but do not teach that the controller is further configured to determine a handling time for each message for each HW module of the plurality of HW modules.
Iwai discloses determining a handling time for each message for a HW module [para. 0057: “When a request from the OS 42 (application layer 41) is received, the command issuing module 431 determines a deadline time by which the command corresponding to the request is to be processed in the SSD 3. Then, the command issuing module 431 issues the command for which the deadline time is designated and submits the command to the submission queue 31.”].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Tidwell and Iwai by modifying Tidwell to determine a handling time for each message, as taught by Iwai. Tidwell and Iwai are both directed to SSDs. Iwai teaches that determining a handling time for SSD commands may be used, in part, to reduce power consumption and improve quality of service [para. 0058]. Therefore, it would have been obvious to one of ordinary skill in the art to apply the teachings of Iwai to Tidwell based on Iwai’s teaching that determination of handling time can be used to reduce power and improve QoS.
Allowable Subject Matter
Claims 3-7 and 12 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(a) and 112(b) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Matta et al., U.S. Patent Application Publication No. 2023/0213997, discloses an invention that compares a number of pending commands for a storage system to a threshold and adjusts a clock frequency [para. 0040].
Jeter et al., U.S. Patent Application Publication No. 2018/0074743, discloses an invention that compares an amount of traffic and/or a queue depth for a memory controller to a threshold and adjusts a clock frequency for the memory controller and memory devices [abstract].
Benistry et al., U.S. Patent Application Publication No. 2018/0356996, discloses an invention that calculates an average workload per command of a storage system, wherein the workload is determined based on a number of pending commands, and adjusts a clock frequency [para. 0017, 0018].
Enz, U.S. Patent Application Publication No. 2020/0183624, discloses an invention that determines an expected performance for a storage engine by determining a number of pending reads and writes in a queue for a plurality of storage drives [para. 0010].
Eilert et al., U.S. Patent No. 6,622,177, discloses an invention that determines a performance measure for a device based on a number of requests in a queue for the device [claim 14].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JI H BAE whose telephone number is (571)272-7181. The examiner can normally be reached Tuesday to Friday and every other Monday, 9 am to 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JI H BAE/Primary Examiner, Art Unit 2176 U.S. Patent and Trademark Office
Phone: 571-272-7181
Fax: 571-273-7181
ji.bae@uspto.gov
1 Assuming the same processing time, the largest number of messages would result a larger product than the smallest number of messages. Therefore, the smallest number of messages would indicate the opposite of a bottleneck condition.
2 Para. 0036 and Fig. 6 indicate that the channel controller operates at a maximum or higher frequency when Fig. 6, step 606, follows the “no” path.
3 Conversely, para. 0036 and Fig. 6 indicate that a channel controller may operate at the minimum or lower frequency when Fig. 6, step 610, follows the “no” path. The Examiner notes that the BRI of claim 1 does require the setting of the frequencies to be dependent upon the determination of the number of messages in the queue.
Prosecution Insights