DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/03/2024 and 04/22/2026 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6 and 12-16 of U.S. Patent No. US12081321B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant application and Pat’321 claim similar time gates configured to control transfer of packet data within the network device; and use the identified initial positions to identify updated positions in the schedules that correspond to events when control of the time gates is needed, and use scheduling information in the schedule at the updated positions to control time gates to selectively transfer packet data to components of the network device.
2. (New) A network device, comprising: a plurality of network interfaces configured to communicatively couple to a plurality of network links; a plurality of time gates coupled to the plurality of network interfaces, each time gate, amongst at least a subset of the plurality of time gates, configured to control transfer of packet data to a corresponding network interface for transmission via a respective communication link; a unitary memory device configured to store multiple schedules corresponding to the at least the subset of the plurality of time gates, each schedule amongst the multiple schedules indicating when a respective time gate is to permit transfer of packet data to the corresponding network interface; centralized control circuitry configured to repeatedly scan the multiple schedules in the unitary memory device to repeatedly identify initial scheduling information corresponding to the schedules using a clock; and a plurality of per-gate control circuitry corresponding to the at least the subset of the plurality of time gates, each per-gate circuitry configured to i) use initial scheduling information corresponding to the respective time gate from the centralized control circuitry to identify updated scheduling information corresponding to a respective schedule, the updated scheduling information corresponding to a time when control of the time gate is needed, and ii) use the updated scheduling information to control the respective time gate to selectively transfer packet data to the respective network interface.
1. A network device, comprising:
a plurality of time gates configured to control transfer of packet data within the network device;
a memory configured to store schedules that indicate when time gates are to permit transfer of packet data; and
control circuitry configured to:
use a clock to repeatedly identify initial positions in the schedules, the initial positions i) corresponding to times when the schedules are accessed in a background procedure, and ii) having an accuracy that is insufficient for directly controlling the time gates,
use the identified initial positions to identify updated positions in the schedules that correspond to events when control of the time gates is needed, and
use scheduling information in the schedule at the updated positions to control time gates to selectively transfer packet data to components of the network device.
2. The network device of claim 1, wherein:
the memory is configured to store, for each of at least some gates among the plurality of gate circuits, a respective scheduling table corresponding to a respective schedule of when the time gate is to permit transfer of packet data; and
the control circuitry comprises:
first control circuitry configured to perform a background operation that uses the clock to repeatedly identify respective initial positions in respective scheduling tables, the respective initial positions having the accuracy that is insufficient for directly controlling the time gates, and
second control circuitry configured to control respective time gates using the respective scheduling tables, including:
in response to events when decisions regarding control of time gates are needed, and using the respective identified initial positions, identifying respective updated positions in respective scheduling tables that correspond to the events, and
using respective scheduling information in the respective scheduling tables at the respective updated positions to control time gates to selectively transfer packet data to components of the network device.
3. (New) The network device of claim 2, wherein: the unitary memory device is configured to store, for each of the at least the subset of the plurality of time gates, a respective scheduling table corresponding to a respective schedule of when the respective time gate is to permit transfer of packet data;the centralized control circuitry is configured to repeatedly scan multiple scheduling tables including repeatedly identifying respective initial scheduling information corresponding to respective scheduling tables using the clock; andeach per-gate circuitry is configured to:in response to an event when a decision regarding control of the respective time gate is needed and using initial scheduling information corresponding to the respective time gate from the centralized control circuitry, identify respective updated scheduling information corresponding to the respective scheduling table, and use the respective updated scheduling information corresponding to the respective scheduling table to control the respective time gate.
3. (Original) The network device of claim 1, further comprising: a plurality of ports configured to communicatively couple to a plurality of communication links; wherein each time gate within a set of time gates among the plurality of time gates is configured to control transfer of packet data to a corresponding port for transmission via a corresponding communication link, each time gate in the set corresponding to a respective priority level; and wherein the memory is configured to store, for each of at least some time gates among the set of time gates, a respective scheduling table corresponding to a respective schedule of when the time gate is to permit transfer of packet data to the corresponding port.
4. (New) The network device of claim 3, wherein the event when the decision regarding control of the respective time gate is needed comprises one of i) packet data arriving at the respective time gate, and ii) packet data being stored in a queue that corresponds to the respective time gate.
5. (New) The network device of claim 2, wherein: the centralized control circuitry is configured to repeatedly scan the multiple schedules in the unitary memory device to repeatedly identify initial positions in the schedules using the clock; and each per-gate circuitry configured to i) use an initial position corresponding to the respective time gate from the centralized control circuitry to identify an updated position in the respective schedule that corresponds to the time when control of the time gate is needed, and ii) use control information at the position in the respective schedule to control the respective time gate to selectively transfer packet data to the respective network interface.
6. (New) The network device of claim 2, wherein the centralized control circuitry is configured to perform a background process that repeatedly scans the multiple schedules in the unitary memory device to repeatedly identify the initial scheduling information.
2. The network device of claim 1, wherein:
the memory is configured to store, for each of at least some gates among the plurality of gate circuits, a respective scheduling table corresponding to a respective schedule of when the time gate is to permit transfer of packet data; and
the control circuitry comprises:
first control circuitry configured to perform a background operation that uses the clock to repeatedly identify respective initial positions in respective scheduling tables, the respective initial positions having the accuracy that is insufficient for directly controlling the time gates, and
second control circuitry configured to control respective time gates using the respective scheduling tables, including:
in response to events when decisions regarding control of time gates are needed, and using the respective identified initial positions, identifying respective updated positions in respective scheduling tables that correspond to the events, and
using respective scheduling information in the respective scheduling tables at the respective updated positions to control time gates to selectively transfer packet data to components of the network device.
7. (New) The network device of claim 2, further comprising: respective sets of multiple queues coupled to the plurality of network interfaces, each set of multiple queues configured to store packet data corresponding to packets to be transmitted via the respective network interface; wherein respective sets of time gates amongst the plurality of time gates correspond to the respective sets of multiple queues; and wherein each time gate within each set of time gates is configured to control transfer of packet data from a respective queue, the transfer of packet data from the respective queue causing packet data to be transmitted via the respective network interface.
3. (Original) The network device of claim 1, further comprising: a plurality of ports configured to communicatively couple to a plurality of communication links; wherein each time gate within a set of time gates among the plurality of time gates is configured to control transfer of packet data to a corresponding port for transmission via a corresponding communication link, each time gate in the set corresponding to a respective priority level; and wherein the memory is configured to store, for each of at least some time gates among the set of time gates, a respective scheduling table corresponding to a respective schedule of when the time gate is to permit transfer of packet data to the corresponding port.
8. (New) The network device of claim 7, wherein each time gate within each set of time gates is configured to control transfer of packet data from a respective queue to a memory controller to cause a corresponding packet to be sent to the respective network interface for transmission.
9. (New) The network device of claim 7, wherein respective queues in each set correspond to respective priority levels.
4. (New) The network device of claim 3, wherein the event when the decision regarding control of the respective time gate is needed comprises one of i) packet data arriving at the respective time gate, and ii) packet data being stored in a queue that corresponds to the respective time gate.
10. (New) The network device of claim 2, wherein each per-gate circuitry is configured to identify updated scheduling information corresponding to the respective schedule in response to packet data arriving at the respective time gate.
6. (New) The network device of claim 2, wherein the centralized control circuitry is configured to perform a background process that repeatedly scans the multiple schedules in the unitary memory device to repeatedly identify the initial scheduling information.
11. (New) The network device of claim 2, wherein each per-gate circuitry is configured to identify updated scheduling information corresponding to the respective schedule in response to packet data being stored in a queue that corresponds to the respective time gate.
5. (New) The network device of claim 2, wherein: the centralized control circuitry is configured to repeatedly scan the multiple schedules in the unitary memory device to repeatedly identify initial positions in the schedules using the clock; and each per-gate circuitry configured to i) use an initial position corresponding to the respective time gate from the centralized control circuitry to identify an updated position in the respective schedule that corresponds to the time when control of the time gate is needed, and ii) use control information at the position in the respective schedule to control the respective time gate to selectively transfer packet data to the respective network interface.
12. (New) A method for controlling information transfer within a network device, the method comprising: storing multiple schedules in a unified memory device of the network device, the multiple schedules indicating when respective time gates among a plurality of time gates are to permit transfer of packet data; repeatedly scanning, by centralized control circuitry of the network device, the multiple schedules in the unitary memory device to repeatedly identify initial scheduling information corresponding to the schedules using a clock of the network device; using, at each per-gate control circuitry among a plurality of per-gate control circuitry corresponding to the plurality of time gates, initial scheduling information corresponding to the respective time gate from the centralized control circuitry to identify updated scheduling information corresponding to a respective schedule, the updated scheduling information corresponding to a time when control of the time gate is needed; and using, at each per-gate control circuitry, the updated scheduling information to control the respective time gate to selectively transfer packet data within the network device.
12. (Currently Amended) A method for controlling information transfer within a network device, the method comprising: storing schedules in a memory, the schedules indicating when time gates are to permit transfer of packet data; repeatedly identifying, by control circuitry, initial positions in the schedules i) corresponding to times when the schedules are accessed in a background procedure, and ii) having an accuracy that is insufficient for directly controlling the time gates; using, by the control circuitry, the identified initial positions to identify updated positions in the schedules that correspond to events when control of the time gates is needed; and using, by the control circuitry, scheduling information at the updated positions in the schedules to selectively transfer packet data to components of the network device using the time gates.
13. (Currently Amended) The method of claim 12, wherein: storing schedules in the memory comprises storing respective scheduling tables in the memory, the respective scheduling tables corresponding to respective schedules for when respective time gates are to permit transfer of packet data; repeatedly identifying the initial positions in the schedules comprises performing, by first control circuitry, the background operation to use a clock to repeatedly identify respective initial positions in respective scheduling tables, the respective initial positions having the accuracy that is insufficient for directly controlling the time gatescorresponding to times when the schedules are accessed in a background procedure; using the identified initial positions to identify updated positions in the schedules comprises: in response to events when time gate circuitry decisions are needed, identifying, by second control circuitry, respective updated positions in the respective scheduling tables that correspond to the events using the initial positions; andusing the scheduling information at the updated positions in the schedules to selectively transfer packet data comprises using, by the second control circuitry, respective scheduling information at the respective updated positions in the respective scheduling tables to selectively transfer packet data to components of the network device.
13. (New) The method of claim 12, wherein: storing multiple schedules in a unified memory device of the network device comprises storing, for each of the at least a subset of the plurality of time gates, a respective scheduling table in the unified memory device, the respective scheduling table corresponding to a respective schedule of when the respective time gate is to permit transfer of packet data;repeatedly scanning the multiple schedules in the unitary memory device comprises repeatedly scanning multiple scheduling tables, including repeatedly identifying respective initial scheduling information corresponding to respective scheduling tables using the clock; andusing, at each per-gate control circuitry, the initial scheduling information to identify the updated scheduling information comprises, in response to an event when a decision regarding control of the respective time gate is needed and using initial scheduling information corresponding to the respective time gate from the centralized control circuitry, identifying, by the each per-gate control circuitry, respective updated scheduling information corresponding to the respective scheduling table; andusing, at each per-gate control circuitry, the updated scheduling information to control the respective time gate comprises using, at each per-gate control circuitry, the respective updated scheduling information corresponding to the respective scheduling table to control the respective time gate.
14. (Original) The method of claim 12, further comprising: storing packet descriptors corresponding to packets in a plurality of queues corresponding to a plurality of time gates; wherein using the scheduling information at the updated positions in the schedules to selectively transfer packet data comprises the control circuitry using scheduling information at the updated positions in the schedules to selectively transfer packet descriptors from the plurality of queues to a memory controller to cause packets corresponding to packet descriptors to be sent to one or more ports for transmission via the corresponding communication link.
14. (New) The method of claim 13, wherein the event when the decision regarding control of the respective time gate is needed comprises one of i) packet data arriving at the respective time gate, and ii) packet data being stored in a queue that corresponds to the respect
15. (New) The method of claim 12, wherein: repeatedly scanning the multiple schedules in the unitary memory device comprises repeatedly scanning, by the centralized control circuitry, the multiple schedules in the unitary memory device to repeatedly identify initial positions in the schedules using the clock; and using, at each per-gate control circuitry, the initial scheduling information to identify the updated scheduling information comprises using, by the each per-gate control circuitry, an initial position corresponding to the respective time gate from the centralized control circuitry to identify an updated position in the respective schedule that corresponds to the time when control of the time gate is needed; andusing, at each per-gate control circuitry, the updated scheduling information to control the respective time gate comprises using, at each per-gate control circuitry, control information at the position in the respective schedule to control the respective time gate to selectively transfer packet data to the respective network interface.tive time gate.
16. (New) The method of claim 12, wherein repeatedly scanning the multiple schedules in the unitary memory device comprises performing, by the centralized control circuitry, a background process that repeatedly scans the multiple schedules in the unitary memory device to repeatedly identify the initial scheduling information.
13. (Currently Amended) The method of claim 12, wherein: storing schedules in the memory comprises storing respective scheduling tables in the memory, the respective scheduling tables corresponding to respective schedules for when respective time gates are to permit transfer of packet data; repeatedly identifying the initial positions in the schedules comprises performing, by first control circuitry, the background operation to use a clock to repeatedly identify respective initial positions in respective scheduling tables, the respective initial positions having the accuracy that is insufficient for directly controlling the time gatescorresponding to times when the schedules are accessed in a background procedure; using the identified initial positions to identify updated positions in the schedules comprises: in response to events when time gate circuitry decisions are needed, identifying, by second control circuitry, respective updated positions in the respective scheduling tables that correspond to the events using the initial positions; andusing the scheduling information at the updated positions in the schedules to selectively transfer packet data comprises using, by the second control circuitry, respective scheduling information at the respective updated positions in the respective scheduling tables to selectively transfer packet data to components of the network device.
15. (Original) The method of claim 14, wherein using the identified initial positions to identify updated positions in the schedules comprises: in response to packet descriptors being stored in respective queues, identifying, by the control circuitry, respective updated positions in the respective schedules that correspond to respective times at which the packet descriptors were stored in the respective queues.
16. (Original) The method of claim 14, wherein using the identified initial positions to identify updated positions in the schedules comprises: in response to packet descriptors arriving at respective time gates, identifying, by the control circuitry, respective updated positions in respective schedules that correspond to respective times at which the packet descriptors arrived at the respective time gates.
17. (New) The method of claim 12, further comprising: respective sets of multiple queues coupled to the plurality of network interfaces, each set of multiple queues configured to store packet data corresponding to packets to be transmitted via a respective network interface of the network device; wherein respective sets of time gates amongst the plurality of time gates correspond to the respective sets of multiple queues; and using, at each per-gate control circuitry, the updated scheduling information to control the respective time gate comprises using, at each per-gate control circuitry, the updated scheduling information to control transfer of packet data from a respective queue, the transfer of packet data from the respective queue causing packet data to be transmitted via the respective network interface.
14. (Original) The method of claim 12, further comprising: storing packet descriptors corresponding to packets in a plurality of queues corresponding to a plurality of time gates; wherein using the scheduling information at the updated positions in the schedules to selectively transfer packet data comprises the control circuitry using scheduling information at the updated positions in the schedules to selectively transfer packet descriptors from the plurality of queues to a memory controller to cause packets corresponding to packet descriptors to be sent to one or more ports for transmission via the corresponding communication link.
18. (New) The method of claim 17, further comprising: controlling transfer, at each time gate within each set of time gates, of packet data from a respective queue to a memory controller to cause a corresponding packet to be sent to the respective network interface for transmission.
19. (New) The method of claim 17, wherein respective queues in each set correspond to respective priority levels.
15. (Original) The method of claim 14, wherein using the identified initial positions to identify updated positions in the schedules comprises: in response to packet descriptors being stored in respective queues, identifying, by the control circuitry, respective updated positions in the respective schedules that correspond to respective times at which the packet descriptors were stored in the respective queues.
20. (New) The method of claim 12, wherein using, at each per-gate control circuitry, the initial scheduling information to identify the updated scheduling information comprises identifying, by the each per-gate control circuitry, updated scheduling information corresponding to the respective schedule in response to packet data arriving at the respective time gate.
16. (Original) The method of claim 14, wherein using the identified initial positions to identify updated positions in the schedules comprises: in response to packet descriptors arriving at respective time gates, identifying, by the control circuitry, respective updated positions in respective schedules that correspond to respective times at which the packet descriptors arrived at the respective time gates.
21. (New) The method of claim 12, wherein using, at each per-gate control circuitry, the initial scheduling information to identify the updated scheduling information comprises identifying, by the each per-gate control circuitry, updated scheduling information corresponding to the respective schedule in response to packet data being stored in a queue that corresponds to the respective time gate.
15. (Original) The method of claim 14, wherein using the identified initial positions to identify updated positions in the schedules comprises: in response to packet descriptors being stored in respective queues, identifying, by the control circuitry, respective updated positions in the respective schedules that correspond to respective times at which the packet descriptors were stored in the respective queues.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please also see PTO-892.
Takahashi et al. US 20230075721 A1 teaches in para. [0035] The scheduler unit 205 controls transmission availability of each of the plurality of time gate units 203 based on schedule information notified from the signal transfer management apparatus 101. Here, the schedule information includes parameters (gate start time, gate opening time, gate opening period, and the like) necessary to open the time gate unit 203. For example, the scheduler unit 205 starts the output from the buffer unit 202(1) to the signal transfer unit 204 at the gate start time of the time gate unit 203(1) in the buffer unit 202(1) having the highest priority, which is described in the schedule information notified from the signal transfer management apparatus 101. Then, the time gate unit 203 outputs the signal of the buffer unit 202(1) to the signal transfer unit 204 for the designated gate opening time, and transmits the signal from the signal transfer unit 204 to a transfer destination.
Hajduczenia et al. EP 1786149 A1 teaches enabling the OLT level scheduler to gain access directly into the particular LLID supported queues. Such a solution allows therefore to group packet buffers storing the same traffic type into a single LLID entity and then grant them individually from the OLT level so as to eliminate any possible packet delineation problems and upstream slot remainders, caused by ONU based packet schedulers operating on a single, aggregate grant value conveyed within the standard GATE MPCP (00-02) message.
Shibata et al. US 20230135477 A1 teaches in para. [0034] The time gate unit 203 includes a plurality of gates corresponding to the plurality of buffers of the buffer unit 202 and opens and closes the gates in response to commands from the scheduler unit 205. In the example of FIG. 2, the time gate unit 203 includes n gates 203(1), 203(2), ..., 203(n). The time gate unit 203 controls opening and closing of the gates that output frames from the corresponding buffers in which the frames with corresponding priorities are held, for example, in response to commands from the scheduler unit 205.
Oge et al. US 20190158620 A1 teaches in para. [0085] A plurality of transmission queues and open/close processing of the gates corresponding to the respective transmission queues are controlled, at the timing set in the gate control list. In this manner, the transmission timing from each of the transmission queues is controlled, at the timing scheduled on the basis of the gate control list.
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/WUTCHUNG CHU/Primary Examiner, Art Unit 2418
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