Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1 and 19.
b. Claims 1-20 are pending on the application.
Drawings
2. The drawings were received on 09/03/2024. These drawings are review and accepted by examiner.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 12/13/2024. The information disclosed therein was considered.
Specification
5. Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words. It is important that the abstract not exceed 150 words in length since the space provided for the abstract on the computer tape used by the printer is limited. The form and legal phraseology often used in patent claims, such as "means" and "said," should be avoided. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, "The disclosure concerns," "The disclosure defined by this invention," "The disclosure describes," etc.
The abstract of the disclosure is objected to because it uses the phrase “OF THE DICLOSURE” in page 1, line 1, which is implied. Correction is required. See MPEP § 608.01(b).
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1-2, 6 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Byeon et al (Patent No.: US 6,888,756 B2).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding to independent claim 1, Byeon et al in Figures 1-6 are directly discloses a voltage generation circuit (a bias voltage generated circuit 150, Figures 1-5) comprising:
a first transistor (a transistor 27, Fig. 2) including a gate to which a reference voltage (a reference voltage circuit 151, Fig. 1) is applied, a first terminal to which a power voltage is applied, and a second terminal that is connected to a first node (the reference voltage circuit 151 contain the transistor 27, which is the control signal REFE connected to the gate of the transistor 27 and the reference voltage circuit 151 output the reference voltage Vref, Figs. 1-2, column 3, lines 38-54);
a first circuit (a 1st voltage regulator 153, Figs. 1 and 4) connected to the first node, and configured to boost a first voltage (a power source voltage Vdd, Figs. 1 and 4) at the first node and output the boosted first voltage as a second voltage (the 1st voltage regulator 153 of the bias circuit 150 receives the reference voltage Vref from the reference voltage generation circuit 151 and generating the sensing voltage Vs in response to the control signal SE, see at least in Figs. 1 and 4, column 3, 38-67); and
a second circuit (a 2nd voltage regulator 154, Figs. 1 and 5) connected to the first node, and configured to sense a first current that flows from the first transistor to the first circuit (the 2nd voltage regulator 154 of the bias circuit 150 receives the reference voltage Vref from the reference voltage generation circuit 151 and generating the sensing voltage Vs in response to the control signal PRE, Figs. 1 and 5, column 4, lines 30-41), wherein
the first circuit (a 1st voltage regulator 153, Figs. 1 and 4) is configured to stop the boosting of the first voltage based on a sensing result from the second circuit (a 2nd voltage regulator 154, Figs. 1 and 5)(for example, the 1st voltage regulator 153 and the a 2nd voltage regulator 154 of the bias circuit 150 receives the reference voltage Vref and voltage Vp generating the sensing voltage Vs in response to the control signal SE and PRE, see at least in Figs. 1 and 4-5, column 2, 23 to column 5, lines 37 and the related disclosures).
Regarding dependent claim 2, Byeon et al in Figures 1-6 are directly discloses a voltage generation circuit (a bias voltage generated circuit 150, Figures 1-5) wherein the sensing result (the output voltage Vs, Fig. 1) indicates whether or not the first current is greater than a reference current (the reference voltage Vref, Fig. 1)(the reference voltage circuit 151 generate the reference voltage Vref by utilizing the power source voltage Vdd which is applied to the 1st regulator circuit, see Figures 1-2, column 3, lines 38-54).
Regarding dependent claim 6, Byeon et al in Figures 1-6 are directly discloses a voltage generation circuit (a bias voltage generated circuit 150, Figures 1-5) wherein the second circuit (the 2nd regulator voltage circuit 154, Fig. 1) is configured to stop sensing the first current in response to a control signal (the control signal Vp)(the control signal Vp generate the output to the 2nd regulator voltage circuit and sensing the voltage Vs, see Fig. 1, column 3, lines 55-63).
Regarding to independent claim 19, Byeon et al in Figures 1-6 are directly discloses a semiconductor memory device (a non-volatile memory device 100, Figures 1-5) comprising:
memory cells (a memory cell array 110, Fig. 1); and
voltage generation circuit (a bias voltage generated circuit 150, Figures 1-5) including
a first transistor (a transistor 27, Fig. 2) including a gate to which a reference voltage (a reference voltage circuit 151, Fig. 1) is applied, a first terminal to which a power voltage is applied, and a second terminal that is connected to a first node (the reference voltage circuit 151 contain the transistor 27, which is the control signal REFE connected to the gate of the transistor 27 and the reference voltage circuit 151 output the reference voltage Vref, Figs. 1-2, column 3, lines 38-54);
a first circuit (a 1st voltage regulator 153, Figs. 1 and 4) connected to the first node, and configured to boost a first voltage (a power source voltage Vdd, Figs. 1 and 4) at the first node and output the boosted first voltage as a second voltage (the 1st voltage regulator 153 of the bias circuit 150 receives the reference voltage Vref from the reference voltage generation circuit 151 and generating the sensing voltage Vs in response to the control signal SE, see at least in Figs. 1 and 4, column 3, 38-67) that is supplied to the memory cells (the memory cell array 110); and
a second circuit (a 2nd voltage regulator 154, Figs. 1 and 5) connected to the first node, and configured to sense a first current that flows from the first transistor to the first circuit (the 2nd voltage regulator 154 of the bias circuit 150 receives the reference voltage Vref from the reference voltage generation circuit 151 and generating the sensing voltage Vs in response to the control signal PRE, Figs. 1 and 5, column 4, lines 30-41), wherein
the first circuit (a 1st voltage regulator 153, Figs. 1 and 4) is configured to stop the boosting of the first voltage based on a sensing result from the second circuit (a 2nd voltage regulator 154, Figs. 1 and 5)(for example, the 1st voltage regulator 153 and the a 2nd voltage regulator 154 of the bias circuit 150 receives the reference voltage Vref and voltage Vp generating the sensing voltage Vs in response to the control signal SE and PRE, see at least in Figs. 1 and 4-5, column 2, 23 to column 5, lines 37 and the related disclosures).
Allowable Subject Matter
7. Claims 3-5, 7-18 and 20, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependents claims 3-5, the prior art fails to tech or suggest the claimed limitations, namely, the voltage generation circuit, wherein the second circuit is configured to generate the sensing result based on a second current that is proportional to the first current, wherein the second circuit is configured to generate the sensing result by comparing the second current with a reference current, wherein the second circuit is configured to output a first sensing result when the second current is higher than the reference current, and a second sensing result when the second current is equal to or lower than the reference current, and the first circuit stops the boosting of the first voltage in response to the first sensing result and does not stop the boosting of the first voltage in response to the second sensing result.
With respected to dependents claims 7-16, the prior art fails to tech or suggest the claimed limitations, namely, the voltage generation circuit, wherein the second circuit includes: a second transistor including a gate to which the reference voltage is applied, a first terminal to which the power voltage is applied, and a second terminal that is connected to a second node; an operational amplifier including a first input terminal to which the first voltage at the first node is applied, a second input terminal to which a third voltage at the second node is applied, and an output terminal from which the operational amplifier outputs a fourth voltage based on the first voltage and the third voltage; a third transistor including a gate to which a fifth voltage based on the fourth voltage is applied, a first terminal that is connected to the second node, and a second terminal that is connected to a third node; a current source that supplies a reference current to a fourth node; a fourth transistor including a gate to which the fifth voltage is applied, a first terminal that is connected to the fourth node, and a second terminal that is connected to a fifth node; and an inverter including an input terminal to which a sixth voltage at the fourth node is applied and an output terminal from which the inverter outputs a second signal based on the sixth voltage, wherein the sensing result is a signal that is generated by the second circuit based on the second signal.
With respected to dependents claims 17-18, the prior art fails to tech or suggest the claimed limitations, namely, the voltage generation circuit, wherein the first circuit is configured to stop the boosting of the first voltage based further on a fourth signal that is generated based on the second voltage, further comprising a third circuit including a first terminal to which the sensing result is input, a second terminal to which the fourth signal is input, and a third terminal, wherein the third circuit is configured to calculate a logical product of the sensing result and the fourth signal and output the calculated logical product through the third terminal, wherein the first circuit is configured to stop the boosting of the first voltage based on the calculated logical product.
With respected to dependents claim 20, the prior art fails to tech or suggest the claimed limitations, namely, the semiconductor memory device, further comprising a fourth circuit configured to control the voltage generating circuit, wherein the fourth circuit generates a control signal for enabling the second circuit to sense the first current and transmits the control signal to the voltage generation circuit.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Urabe et al (US. 7,359,249) discloses the writing controller is capable of individually setting memory information of each of the memory cells in the memory cell array.
Jinbo (US. 5,305,273) discloses a semiconductor memory device has a matrix of memory cells interconnected by a plurality of column and row lines and a voltage source corresponding to a specified status.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see
http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov