DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in KOREA on 01/18/2024. It is noted, however, that applicant has not filed a certified copy of the REPUBLIC OF KOREA 10-2024-0008162 application as required by 37 CFR 1.55.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
The claims use the terms “check node unit” and “variable node unit” which a generic placeholder for means plus function language.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The preamble in claim 1 recites a “hardware optimization device”. However, paragraph 3 on page 8 recites, that in implementations described herein may be a software program a data stream or a signal. Hence, is not clear what relationship a “variable node unit” or a “check node unit” has to do with the hardware device recited in the preamble.
In the case that the implementations are executed as a data stream or signal, the claims are nonstatutory. In the case that the implementations are executed in software, the Applicant has not provided sufficient software steps to demonstrate how such an implementation would be executed, and software.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to the mathematical algorithm taught in figure 7; and, on pages 14 and 15 in the Applicant’s specification without significantly more. The claim(s) recite(s) a mathematical algorithm comprising a step for updating a variable node message comprising mathematical calculations and a step for updating a check node messages comprising mathematical calculations: page 14 and 15 in the Applicant’s specification. This judicial exception is not integrated into a practical application because the hardware device recited in claim one could be a general-purpose computer, which is insufficient to raise the level to a practical application. The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because any structural element, which when combined with the abstract algorithm raises the level to a practical application. Note: as per claim 11, claim 11 is a method claim and only recites the abstract algorithm.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 and 11-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SHAM; Chiu-Wing et al. (US 20160142074 A1, hereafter referred to as SHAM).
Note: Figures 2-5; and, paragraphs [0072]-[0077] on page 4 in SHAM teaches a decoder 10 comprised of a plurality of individual sub- decoders 11 whereby the individual sub- decoders 11 are arranged in a ring shape for short delay pipelined processing. Figure 3 in SHAM teaches that the parity check matrix H is divided into column blocks/submatrices and phase for subcode 20 are performed on phases for subcodes for each row of column blocks/submatrices (for example, subcode 20 in Figure 3 in Sham gives rise to calculations for a phase corresponding to Hl, Hm and Hr; note: the column blocks/submatrices above subcode 20 corresponds to another phase previously executed and a column blocks/submatrices below subcode 20 corresponds to still another phase to subsequently be executed).
Rejection of claims 1 and 11:
Figures 2-5; and, paragraphs [0072]-[0077] on page 4 in SHAM teaches a variable node unit/VNP 17 configured to update a variable node message/V2C message delivered to each variable node; and a check node unit/CNP 16 configured to update a check node message/C2V message delivered to each check node, wherein the variable node unit/VNP 17 and the check node unit/CNP 16 divide a parity check matrix into N column blocks/submatrices for the update (N is a natural number of 2 or more), repeatedly perform calculations for the variable node and the check node for each of the divided column blocks/submatrices, and perform different calculations for variable nodes according to each of phases corresponding to rows of the column blocks/submatrices through a pipeline method.
Rejection of claims 2 and 12:
Figures 2-5; and, paragraphs [0072]-[0077] on page 4 in SHAM teaches that sub- decoders 11 are arranged in a ring shape for iteratively decoding phase corresponding to Hl, Hm and Hr;
Rejection of claims 3 and 13:
Figures 2-5; and, paragraphs [0072]-[0077] on page 4 in SHAM teaches various stages 11 for calculations offset for each of phases.
Rejection of claims 4-5 and 14-15:
Figures 2-5; and, paragraphs [0072]-[0077] on page 4 in SHAM.
Rejection of claims 6-9 and 16-19:
Paragraph [0074] on page 4 of SHAM.
Allowable Subject Matter
Claims 10 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 10 and 20 depend from respective claims 1 and 11 and since dependent claims inherit all the limitations of the claims from which they depend, the rejections of claims 1 and 11 clearly indicate what is nonobvious and/or novel in claims 10 and 20 in view of the claims from which they depend and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20070220398 A1 is directed to An apparatus for decoding a Low-Density Parity Check (LDPC) code in a communication system, the apparatus comprising: an edge memory for storing a message delivered through an edge between a variable node and a check node; a node memory for storing a check node value; a node processor performing a node processing operation using information stored in at least one of the node memory and the edge memory, storing a check node value generated by performing the node processing operation in the node memory, and storing a message generated by performing the node processing operation in the edge memory; a switch for switching outputs of the node memory and the node processor through a permutation operation; a parity check verifier for parity-checking an output from the node memory; and a controller for providing a control signal for controlling the node processor; and, is a good teaching reference.
US 20090113256 A1 is directed to A method comprising: storing an encoded data block comprising codewords; and decoding the data block in a pipelined manner using a layered belief propagation technique and scalable resources, where the scalable resources comprise a scalable permuter, a scalable memory unit, and a scalable decoder, and where the scalable resources are configurable to accommodate at least two codeword lengths and at least two code rates; and, is a good teaching reference.
US 20130212450 A1 is directed to A Low-Density Parity-Check Convolutional Code (LPDCCC) decoder for partial parallel decoding of low-density parity-check convolutional codes, the decoder comprising: a plurality of pipeline processors to receive channel messages and edge-messages; each processor having: a plurality of block processing units (BPUs), each BPU having a plurality of check node processors (CNPs) to process check nodes that enter into the processor and a plurality of variable node processors (VNPs) to process variable nodes that are about to leave the processor; and a plurality of Random Access Memory (RAM) blocks for dynamic message storage of the channel messages and the edge-messages; wherein in each processor, the VNPs are directly connected to corresponding RAM blocks, and the CNPs are directly connected to corresponding RAM blocks such that the connections from the VNPs and CNPs to the corresponding RAM blocks are pre-defined and fixed according to a parity-check matrix of an unterminated time-varying periodic LDPCCC; and, is a good teaching reference.
US 20110161770 A1 is directed to A method for encoding and decoding a low-density parity-check code, comprising steps of: (a) layering a parity-check matrix of a quasi-cyclic low-density parity-check code into a plurality of layers in a row permutation manner; (b) partitioning each of the layers into a plurality of sub-layers by rows; (c) partitioning each of the sub-layers into a plurality of tasks, wherein each of the layers comprises the tasks; and (d) iteratively processing the tasks of each of the layers in a sequential manner; and, is a good teaching reference.
US 20160197701 A1 is directed to A method for receiving a signal in a signal receiving apparatus in a communication system supporting a low density parity check (LDPC) code, the method comprising: performing an LDPC decoding operation which is based on a preset first parity check matrix on a received signal, wherein the first parity check matrix is generated based on a second parity check matrix including M×N sub-matrices, wherein the first parity check matrix includes non-zero matrices among the M×N sub-matrices included in the second parity check matrix, wherein the non-zero matrices are expressed as an n_c form, n denotes a number of blocks included in the second parity check matrix, and c denotes a number of non-zero matrices included in an nth block column included in the second parity check matrix, and wherein the first parity check matrix includes a preset number of partial matrices, and each of the partial matrices includes a preset number of non-zero sub-matrices on a block column of the second parity check matrix basis; and, is a good teaching reference.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH D TORRES whose telephone number is (571)272-3829. The examiner can normally be reached Monday-Friday 10-7 PT.
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/JOSEPH D TORRES/Primary Examiner, Art Unit 2112