DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-15 and 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Abelmoneum et al. (US 20220200655).
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With respect to claim 1, Abelmoneum et al. (US 20220200655) discloses a security chip (See figs. 2 and 5), comprising: a clock gating type generator (processor 501) configured to generate a clock gating type based on chip-specific parameters (See [0040]:” security logic 503 comprises circuits with physically unclonable function (PUF) that produce randomized values used as a secret key. The PUF provides unique identification per part which is secret and that is not exposed outside the hardware logic.”); and a main operation unit including a plurality of flip-flop groups (flip-flop groups within modules such as i.e. 202a-202ab in module 1) , wherein each of the plurality of flip-flop groups is configured to receive a clock signal (clock signals such as i.e. CLk2a etc) at a clock input terminal (fig. 2, modules 1, 2…n”) in a first gating mode or a second gating mode, wherein the first gating mode results in a different current consumption pattern compared to the second gating mode (See[0043], “The keys are then decoded and read by different logic units 504-1, 504-2, through 504-N. Each logic provides the keys (Key1, Key2) to the appreciate clock gating logic (e.g., clock gating logic 1 through N that are marked as 505-1, 505-2, through 505-N). The outputs of each clock gating logic are a clock (e.g., Clock 1, Clock2, through Clock N.”).
With respect to claim 2, Abelmoneum et al. discloses the security chip of claim 1, wherein the clock gating type generator comprises: a bit string generator (see [0040] PUF, “ security logic 503 comprises circuits with physically unclonable function (PUF) that produce randomized values used as a secret key. The PUF provides unique identification per part which is secret and that is not exposed outside the hardware logic.”) configured to generate a bit string using a physically unclonable function or a chip identifier (Note: per [0040], physically unclonable function (PUF))“; and a security chip including a register (see for example [0034], “spread-spectrum is applied using a frequency hopping time sequence which is random. This random sequence is generated by pseudorandom number generator 402”) that generates the clock gating type of a predetermined length from the bit string ([0034], When a clock (e.g., a reference clock) is encoded with data (e.g., keys for gating a particular clock gating driver) as random frequency hopping time sequence is being instituted for spread-spectrum, the encoded data is hard or nearly impossible to decipher. In some embodiments, crypto keys are generated for a particular clock gating structure 405. If an IP block (e.g., a processor) uses different types of designs for its clock gating driver, separate crypto keys can be generated for each of such clock gating driver. “).
With respect to claim 4, Abelmoneum discloses the security chip of claim 1, wherein the clock gating type generator comprises: a random number generator (see [0034] referring to (402) as random number generator) configured to generate a random number sequence ([0034], “random sequence is generated by pseudorandom number generator 402”); and a register (see for example [0034], “spread-spectrum is applied using a frequency hopping time sequence which is random. This random sequence is generated by pseudorandom number generator 402”) configured to generate the clock gating type of a predetermined length from the random number sequence.
With respect to claim 5, Abelmoneum discloses the security chip of claim 1, wherein each of the plurality of flip-flop group comprises: at least one flip-flop (i.e. 202a) configured to receive input data in synchronization with the clock signal (i.e. CLk2a); and a gating control circuit (i.e. clock gate logic or driver 100-32 are gated) configured to transmit or block the clock signal to the clock input terminal in response to the clock gating type and the latch control signal (ie. enable signal).
With respect to claim 6, Abelmoneum discloses the security chip of claim 5, wherein the gating control circuit comprises: a first OR gate (see fig. 1 gates 102 ) configured to perform a logical OR operation of the latch control signal and the clock gating type; an AND gate (see fig. 1 element 104) configured to transmit a result of a logical AND operation of output of the first OR gate and the clock signal to the clock input terminal (Gated_ClkX).
With respect to claim 7, Abelmoneum discloses the security chip of claim 6, wherein the gating control circuit comprises a second OR gate (see fig. 1 gates 103) configured to perform a logical OR operation of the latch control signal and an inverted clock gating type.
With respect to claim 8, Abelmoneum discloses the security chip of claim 7, wherein each of the plurality of flip-flop groups comprises a multiplexer (AND gate can be considered a multiplexer) configured to transmit input data or output data to the data input terminal of the at least one flip-flop according to the output of the second OR gate (see fig. 1 gates 103).
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With respect to claim 9, Abelmoneum discloses a clock gating method of a security chip, comprising: generating a plurality of clock gating types (see. Fig. 8 with respect to figs. 2 and 5) , each clock gating type (Multiple processors, i.e. (see fig. 5)) corresponding to a unique bit string of the security chip (see fig. 5, generating keys patterns 504-1, 504-2.. 504-N); distributing the clock gating types to a plurality of flip-flop groups included in the security chip; and (See fig. 5, clock gated logic 505-1, 505-2… 505-N/ see also fig. 1 and [0023]: “The sequential logic 101 can be a flip-flop or a latch.”) transmitting a clock signal to clock input terminals of flip-flops in at least one of the plurality of flip-flop groups (fig. 2 modules 1, 2, ..n receiving Clk2a… Clk2n) in a first gating mode or a second gating mode based on a clock gating type assigned to the at least one of the flip-flop group, wherein the first gating mode and the second gating mode are associated with different current consumption patterns ([0043]: “The keys art then decoded and read by different logic units 504-1, 504-2, through 504-N. Each logic provides the keys (Key1, Key2) to the appreciate [appropriate] clock gating logic (e.g., clock gating logic 1 through N that are marked as 505-1, 505-2, through 505-N).”)
With respect to claim 10, Abelmoneum discloses the method of claim 9, wherein in the generating the plurality of clock gating types, the unique bit string is generated using a physically unclonable function (PUF function is referred to being unclonable) , a chip identifier, or a random number generator (see [0034] referring to (402) as random number generator).
With respect to claim 11, Abelmoneum discloses the method of claim 9, wherein 1-bit of the clock gating type (i.e. key) is provided to each of the plurality of flip-flop groups.
With respect to claim 12, Abelmoneum discloses the method of claim 9, further comprising: receiving a latch control signal (i.e. CLk3_Key1, Clk3_Key2 Clk3_Enable) to activate or deactivate data reception of the flip-flops (i.e. 202a) , wherein in the first gating mode, toggling of the clock signal is activated or deactivated depending on logic value of the latch control signal (i.e CLk3_Key1, Clk3_Key2 Clk3_ with the Enable) , and in the second gating mode (i.e. Clk3_Enable activated), toggling of the clock signal is activated irrespective of the logic value of the latch control signal.
With respect to claim 13, Abelmoneum discloses the method of claim 12, wherein when the latch control signal is activated, input data is transmitted to data input terminals of the flip-flops (i.e. 202a), and when the latch control signal is deactivated, output terminals of the flip-flops are connected to the data input terminals.
With respect to claim 14, Abelmoneum discloses a security chip, comprising: a clock gating type generator (i.e processor 501) configured to generate a chip-specific clock gating type; and a plurality of flip-flop groups (flip-flop groups within modules such as i.e. 202a-202ab in module 1), wherein each of the plurality of flip-flop groups is configured to be set to a clock gating mode with different current consumption patterns (See[0043], “The keys are then decoded and read by different logic units 504-1, 504-2, through 504-N. Each logic provides the keys (Key1, Key2) to the appreciate clock gating logic (e.g., clock gating logic 1 through N that are marked as 505-1, 505-2, through 505-N). The outputs of each clock gating logic are a clock (e.g., Clock 1, Clock2, through Clock N.”). based on the clock gating type, wherein each of the plurality of flip-flop groups comprises: at least one flip-flop configured to receive input data synchronized with a clock signal; and a gating control circuit configured to transmit or block the clock signal to a clock input terminal of the at least one flip-flop in response to a latch control signal and the clock gating type.
With respect to claim 15, Abelmoneum discloses the security chip of claim 14, wherein the clock gating type generator generates the clock gating type based on a physically unclonable function (See [0040]:” security logic 503 comprises circuits with physically unclonable function (PUF) that produce randomized values used as a secret key. The PUF provides unique identification per part which is secret and that is not exposed outside the hardware logic.”), a chip identifier, or a random number generator.
With respect to claim 17, Abelmoneum discloses the security chip of claim 14, wherein the gating control circuit comprises: a first logic gate (i.e. fig. 1 OR gate 102) configured to generate a selection signal by performing a logical OR operation of the latch control signal and an inverted clock gating type; a second logic gate (i.e. fig.1 Or gate 103) configured to perform the logical OR operation of the latch control signal and the clock gating type; and a third logic gate (AND gate 104) configured to transmit a result of a logical AND operation of an output of the second logic gate and the clock signal to the clock input terminal (i.e Gated_ClkX).
With respect to claim 18 Abelmoneum discloses the security chip of claim 17, wherein the clock gating modes includes: a first gating mode when the clock gating type is logic '0'; and a second gating mode when the clock gating type is logic '1'. (Within the scope of the invention as the truth table of figure 1 would produce the said configuration).
With respect to claim 19, Abelmoneum discloses the security chip of claim 18, wherein in the first gating mode, when the latch control signal is logic '0', an output of the third logic gate is deactivated, and when the latch control signal is logic '1', the output of the third logic gate is activated, and wherein in the second gating mode, the output of the third logic gate is activated irrespective of the logic value of the latch control signal. (Within the scope of the invention as the truth table of figure 1 would produce the said configuration).
With repsect to claim 20, (Abelmoneum discloses the method of claim 17, further comprising: a multiplexer (Here, AND gate can be considered a multiplexer) configured to selectively transmit input data to a data input terminal of the at least one flip-flop in response to the selection signal.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abelmoneum (US 20220200655) in view of Guruprasad et al. (US 20230124622)
With respect to claim 3, Abelmoneum discloses the security chip of claim 2, wherein the bit string generator includes a one-time programmable (OTP) memory or eFlash that stores the bit string.
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Guruprasad et al. (US 20230124622) discloses a shift register using an OTP in for the purpose of producing an OTP that is unique for each chip [0057]. It would have been obvious before the effective filing date of the claimed invention to use the teaching in Guruprasad in the circuit of Abelmoneum for the purpose of producing a unique security for each chip.
With respect to claim 16, the combination above discloses the security chip of claim 15, wherein the clock gating type generator includes a one-time programmable (OPT) memory or non-volatile memory to store the clock gating type. [0057] It would have been obvious before the effective filing date of the claimed invention to use the teaching in Guruprasad in the circuit of Abelmoneum for the purpose of producing a unique security for each chip.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2849