DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication 2018/0090213 to PETERSON et al.
Regarding claim 1, 7, 11, and 17, PETERSON shows the claimed storage apparatus as system 100 in Fig. 1. He teaches that it has storage blocks at 304 (Figs. 3 and 4), 402 and 410 (Fig. 4), 704 (Fig. 7), and 804, 812, 814, 820, and 822 (Fig. 8).
He shows the claimed controller as nonvolatile memory controller 124 in Figs. 1 and 2.
He teaches that his controller operates as claimed, namely grouping blocks into a quantity of storage regions based on maximum data retention times (see paragraphs 0006, 0031-32, 0079, 0083-0088, and elsewhere, and Figs. 6A and 6B). He explicitly mentions maximum data retention times at 0082 and 0125.
He shows the claimed memory configured to store instructions as computer readable storage media 114 (see 0030).
He shows the claimed processor as processor 111 (see 0029-0030).
Regarding claims 2 and 12, PETERSON shows the claimed host as storage clients 116.
Regarding claims 3 and 13, PETERSON shows the claimed region identifiers as groups 602 in Fig. 6A and groups 652 in Fig. 6B. He shows the claimed mapping relationship in those figures also.
Regarding claims 4 and 14, PETERSON divides up the logical address space among the storage regions (groups) as claimed.
Regarding claims 5 and 15, PETERSON’s device receives commands and writes data in the target storage regions as claimed.
Regarding claims 6 and 16, PETERSON discloses the claimed inverse relationship between retention time and program/erase counts at 0120.
Regarding claims 8-10 and 18-20, PETERSON’s device operates as claimed, selecting a target storage region (group) from the groups shown in Figs. 6A and 6B and sending the data to the target region.
Note
It is noted that any citations to specific pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Conclusion
Any inquiry concerning this Office action should be directed to the Examiner by phone at (571) 272-4214.
Any response to this Office action should be labeled appropriately (including serial number, Art Unit 2132, and type of response) and mailed to Commissioner for Patents, P.O. Box 1450, Alexandria, VA 22313-1450; hand-carried or delivered to the Customer Service Window at the Knox Building, 501 Dulany Street, Alexandria, VA 22314; faxed to (571) 273-8300; or filed electronically using the Patent Center.
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/Kevin Verbrugge/
Kevin Verbrugge
Primary Examiner
Art Unit 2132