Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant application having Application No. 18/824,055 filed on 9/04/2025 is presented for examination.
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Authorization for Internet Communications
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“Recognizing that Internet communications are not secure, I hereby authorize the USPTO to communicate with the undersigned and practitioners in accordance with 37 CFR 1.33 and 37 CFR 1.34 concerning any subject matter of this application by video conferencing, instant messaging, or electronic mail. I understand that a copy of these communications will be made of record in the application file.”
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Information Disclosure Statement
As required by M.P.E.P. 609, the applicant’s submissions of the Information Disclosure Statement dated 6/23/2025 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 12-14, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mylius (US 2014/0215188) in view of Blasco (US 10,452,434).
As per claim 1, Mylius further discloses
A method for distributing instructions to dispatch buffers (Abstract “In an embodiment, a processor includes a multi-level dispatch circuit configured to supply operations for execution by multiple parallel execution pipelines. The multi-level dispatch circuit may include multiple dispatch buffers, each of which is coupled to multiple reservation stations. Each reservation station may be coupled to a respective execution pipeline and may be configured to schedule instruction operations (ops) for execution in the respective execution pipeline. The sets of reservation stations coupled to each dispatch buffer may be non-overlapping. Thus, if a given op is to be executed in a given execution pipeline, the op may be sent to the dispatch buffer which is coupled to the reservation station that provides ops to the given execution pipeline.”), comprising:
receiving a bundle of a plurality of instructions (Paragraph 16 “The instruction cache and fetch control unit 12 is coupled to the decode unit 14, which is coupled to the map unit 16. The map unit 16 is coupled to the dispatch unit 18, which is further coupled to the reservation stations 20A-20I. The reservation stations 20A-20I are coupled to respective execution units 22A-22I and the register file(s) 24. The register file(s) 24 are further coupled to the execution units 22A-22I.”);
wherein the first dispatch buffer is able to process a first instruction affinity and a second instruction affinity (Paragraph 17 “More particularly, in FIG. 1, the dispatch unit 18 may include a set of dispatch buffers 26A-26E. Each of the dispatch buffers 26A-26D is coupled to multiple reservation stations, as shown in FIG. 1. That is, in the illustrated embodiment, the dispatch buffer 26A is coupled to the reservation stations 20A-20B; the dispatch buffer 26B is coupled to the reservation stations 20C-20D; the dispatch buffer 26C is coupled to the reservation stations 20E-20F; and the dispatch buffer 26D is coupled to the reservation stations 20G-20H. Because there is an odd number of reservation stations and the dispatch buffers 26A-26D are coupled to two reservation stations each, the dispatch buffer 26E is coupled to one reservation station 20I. In other embodiments, the reservation station 20I may also be coupled to the dispatch buffer 26D and thus the dispatch buffer 26E may not be required in such embodiments. Coupling two reservation stations per dispatch buffer is merely exemplary, other embodiments may implement more than two reservation stations per dispatch buffer, if desired.”);
wherein the second dispatch buffer is not able to process the first instruction affinity but is able to process the second instruction affinity (Paragraph 17);
queuing a first instruction of the plurality of instructions for distribution to the first dispatch buffer based on the first instruction being of the first instruction affinity (Paragraph 18 “Providing the dispatch buffers may provide a multi-level dispatch from the decode/mapping of ops to the reservation stations. The relatively large number of ops that may be received concurrently in a clock cycle at the dispatch unit 18 may be distributed to the smaller number of dispatch buffers, which may redistribute the ops to the more numerous reservation stations. Thus, a high instruction operation bandwidth into the dispatch unit 18 may be maintained, which may help ensure that the execution units 22A-22I are used efficiently. Additionally, the timing complexities of spreading the large number of ops over the large number of reservation stations may be alleviated in the multi-level scheme.”).
Mylius does not expressly disclose but Blasco discloses determining, for a first dispatch buffer, a first number of credits (Column 6, lines 21-56 “The control logic in the reservation stations 122A-122N also selects a number of ops in the secondary buffer to transfer to the primary buffer. In some embodiments, the number of ops to transfer includes ops with a highest priority among the ops stored in the secondary buffer, although the source operands may not yet be ready or the execution units for executing the instructions may not yet be available. In some embodiments, the control logic cancels, or invalidates, the transfer of a given op from the secondary buffer to the primary buffer in response to determining that the given op has issued to the one or more execution units 124A-124N. Therefore, the given op is not issued twice, and it no longer consumes resources that can be used by other ops. In various embodiments, the control logic in a given one of the reservation stations 122A-122N sends an indication to the dispatch unit 118, which includes a value suggesting a number of ops to dispatch from the dispatch unit 118. In some embodiments, the value is a number of available entries within the given reservation station. In other embodiments, the value is a number of credits, or other value corresponding to the number of available entries within the given reservation station. In some embodiments, the value is based on only newly deallocated entries such as entries deallocated within a past clock cycle. The value may be based on at least one or more of the ops in the second number of ops selected for issue from the secondary buffer. The value may also be based on one or more of the ops selected for transfer from the secondary buffer to the primary buffer. The dispatch unit receives the indication with the value, but the dispatch unit may not be aware of separate buffers, such as each of the primary buffer and the secondary buffer, within the reservation station. It is noted that the control logic within the dispatch unit may or may not dispatch the suggested number of ops all at one time since the dispatch unit uses other criteria to determine both how many ops to dispatch and when to dispatch ops.”);
determining, for a second dispatch buffer, a second number of credits (Column 6, lines 21-56);
adjusting the first number of credits based on the queuing of the first instruction (Column 14, lines 44-67 “A second number of available entries in the secondary buffer is determined (block 706). The second number of available entries may include one or more of already deallocated entries, newly deallocated entries such as entries deallocated within a past clock cycle, entries selected for issue to fill an issue width, and entries selected for transfer to the primary buffer. In some embodiments, an overlap of entries selected for filling an issue width and selected for transfer to the primary buffer is detected and appropriate adjustment of the second number is performed. For example, entries selected for both issue and transfer are not counted twice. An indication is sent to a dispatch unit with a value based on at least the second number requesting ops to be dispatched to the reservation station (block 708). As described earlier, in some embodiments, the value is the second number of available entries. In other embodiments, the value is a number of credits, or other value corresponding to the second number of available entries. In various embodiments, one or more stage boundaries are used in each of the dispatch path, the transfer path, the issue path from the secondary buffer and the update path to the secondary buffer with indications of at least destination operands of issued ops. In some embodiments, the number of stage boundaries is different for one or more of the paths from other paths. These numbers of stage boundaries and any differences in the numbers is taken into account when determining the indication to send to the dispatch unit.”); and
queuing a second instruction of the plurality of instructions for distribution to either the first dispatch buffer or the second dispatch buffer based on a comparison of the adjusted first number of credits and the second number of credits (Column 14, lines 44-67).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Mylius to include the teachings of Blasco because it provides a predictable use of a known resource accounting technique for ensuring available processor queue capacity.
As per claim 4, Blasco further discloses wherein the second number of credits is not adjusted based on the queuing of the second instruction for distribution (Column 6, lines 21-56).
As per claim 12, Mylius further discloses wherein the first number of credits is based on a first availability for instructions within the first dispatch buffer and the second number of credits is based on a second availability for instructions within the second dispatch buffer (Paragraph 7 “Furthermore, the mechanisms for choosing dispatch buffers to receive ops, and for choosing reservation stations to receive ops from the dispatch buffers, may be designed to approximate the transmission of each op to the reservation station that has the most available entries among the reservation stations that are eligible to receive that op.”).
As per claim 13, Mylius further discloses wherein the first number of credits and the second number of credits are determined prior to distributing the first instruction (Paragraph 7).
As per claim 14, it is a device claim having similar limitations as cited in claim 1 and is thus rejected under the same rationale.
As per claim 17, it is a device claim having similar limitations as cited in claim 4 and is thus rejected under the same rationale.
As per claim 20, it is a method claim having similar limitations as cited in claim 1 and is thus rejected under the same rationale.
Claims 2, 3, 5-10, 15, 16, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable Mylius in view of Blasco in further view of Griffith (US 5,689,674).
As per claim 2, Mylius does not expressly disclose but Griffith discloses wherein the comparison of the adjusted first number of credits and the second number of credits comprises a difference value based on a subtraction of the adjusted first number of credits from the second number of credits (Column 11, lines 5-14 “Counter mechanism 510 includes a counter 511, a counter 512, and subtract logic 513. In one embodiment, counter 511 corresponds to Dispatch Port 0 and counter 512 corresponds to Dispatch Port 1. Counters 511 and 512 output their respective counts to subtract logic 513. Subtract logic 513 compares the two counts and outputs the difference between the two counts to the port identifiers 501. Based on this difference and the nature of the micro operation, a port identifier 501 identifies the Dispatch Port from which its corresponding micro operation is to be dispatched.”), further comprising:
accumulating a total number of instructions of the second instruction affinity within the bundle that has been queued for distribution to either the first dispatch buffer or the second dispatch buffer (Column 11, lines 5-14);
comparing the total number of instructions to the difference value (Column 11, lines 5-14); and
queuing the second instruction for distribution to the first dispatch buffer or the second dispatch buffer based on the comparison of the total number of instructions to the difference value (Column 11, lines 5-14).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Mylius as modified to include the teachings of Griffith because is maintains a count of already allocated instructions in order to maintain fairness amongst the dispatching of instructions.
As per claim 3, Griffith further discloses wherein the queuing of the second instruction for distribution further comprises:
queuing the second instruction for distribution to the second dispatch buffer when the total number of instructions is less than the difference value (Column 11, lines 31-51 “A micro operation is received by port identifier 501 and input to two port assignors, port assignor 601 and port assignor 602. Port assignor 601 identifies to which of the Dispatch Ports 2, 3 or 4 the micro operation is to be bound, if any. In one embodiment, port assignor 601 maintains a lookup table of micro operations to Dispatch Ports, based on the execution units coupled to the Dispatch Ports 2, 3 and 4. Thus, upon receipt of the micro operation, port assignor 601 can readily determine whether the micro operation is to be bound to one of the Dispatch Ports 2, 3 or 4. If the lookup by port assignor 601 identifies one of these three ports (Dispatch Port 2, 3 or 4), then the ALDispPort signal line corresponding to that Dispatch Port is asserted, thereby causing the reservation station to tag the micro operation for dispatch from the identified Dispatch Port. It should be noted, however, that a particular micro operation may not be dispatched over any of the Dispatch Ports 2, 3 and 4 (e.g., it may be dispatched over Dispatch Port 1 ), thereby causing none of the ALPDispPort signal lines to be asserted by port assignor 601.”); and
queuing the second instruction for distribution to the first dispatch buffer when the total number of instructions is greater than or equal to the difference value (Column 11, lines 31-51).
As per claim 5, Mylius further discloses further comprising:
determining, for a third dispatch buffer, a third number of credits, wherein the third dispatch buffer is able to process a third instruction affinity and the second instruction affinity (Paragraph 6 “In an embodiment, a processor includes a multi-level dispatch circuit configured to supply operations for execution by multiple parallel execution pipelines. The multi-level dispatch circuit may include multiple dispatch buffers, each of which is coupled to multiple reservation stations. Each reservation station may be coupled to a respective execution pipeline and may be configured to schedule instruction operations (ops) for execution in the respective execution pipeline. The sets of reservation stations coupled to each dispatch buffer may be non-overlapping. Thus, if a given op is to be executed in a given execution pipeline, the op may be sent to the dispatch buffer which is coupled to the reservation station that provides ops to the given execution pipeline.”);
queuing a third instruction of the plurality of instructions for distribution to the third dispatch buffer based on the third instruction being of the third instruction affinity (Paragraph 7);
adjusting the third number of credits based on the queuing of the third instruction for distribution (Paragraph 7); and
queuing a fourth instruction of the plurality of instructions of the second instruction affinity for distribution to either the first dispatch buffer, the second dispatch buffer, or the third dispatch buffer based on respective values of each of the adjusted first number of credits, the second number of credits, and the adjusted third number of credits (Paragraphs 6-7).
As per claim 6, Blasco further discloses further comprising:
determining a first difference value between the adjusted number of first credits and the adjusted number of third credits (Column 6, lines 21-56); and
determining a second difference value between the second number of credits and a higher value of the adjusted number of first credits and the adjusted number of third credits, wherein the queuing of the fourth instruction for distribution is based on the first difference value and the second difference value (Column 6, lines 21-56).
As per claim 7, Griffith further discloses further comprising:
accumulating a total number of instructions of the second instruction affinity within the bundle that have been queued for distribution to either the first dispatch buffer, the second dispatch buffer, or the third dispatch buffer (Column 14, lines 37-50 “Multiplexer 613 is a 4 to 1 multiplexer which outputs one of four count values corresponding to the input count value incremented by zero, one, two or three. Multiplexer control 616 indicates which of the four count values is output by multiplexer 613 based on the inputs it receives from each of the port identifiers 501. The output signal from latch 604 of port identifier 501 indicates whether the micro operation is tagged for dispatch from Dispatch Port 0 or 1. Multiplexer control 616 indicates to multiplexer 613 that multiplexer 613 should output the count value which is the input count value incremented by zero, one, two or three if the number of micro operations tagged to the Dispatch Port corresponding to counter 511 as indicated by the port identifiers is zero, one, two or three, respectively.”);
comparing the total number of instructions to the first difference value and the second difference value (Column 14, lines 37-50); and
queuing the second instruction for distribution to the first dispatch buffer or the second dispatch buffer based on the comparison of the total number of instructions to the first difference value and the second difference value (Column 14, lines 37-50).
As per claim 8, Mylius further discloses wherein the queuing of the fourth instruction for distribution further comprises:
queuing the fourth instruction for distribution to the second dispatch buffer wherein the total number of instructions is less than the second difference value (Paragraph 6); and
queuing the fourth instruction for distribution to one of the first dispatch buffer or the third dispatch buffer based on the first difference value wherein the total number of instructions is greater than or equal to the second difference value (Paragraph 6).
As per claim 9, Griffith further discloses wherein the queuing of the fourth instruction for distribution to one of the first dispatch buffer or the third dispatch buffer based on the first difference value comprises:
adding the first difference value to the second difference value to generate a third difference value (Column 11, lines 5-14);
queuing the fourth instruction for distribution to the first dispatch buffer if the adjusted first number of credits is greater than the adjusted third number of credits and the total number of instructions is less than the third difference value (Column 11, lines 5-14);
queuing the fourth instruction for distribution to the first dispatch buffer if the adjusted first number of credits is less than the adjusted third number of credits and the total number of instructions is greater than or equal to the third difference value (Column 11, lines 5-14);
queuing the fourth instruction for distribution to the third dispatch buffer if the adjusted third number of credits is greater than the adjusted first number of credits and the total number of instructions is less than the third difference value (Column 11, lines 5-14); and
queuing the fourth instruction for distribution to the third dispatch buffer if the adjusted third number of credits is less than the adjusted first number of credits and the total number of instructions is greater than or equal to the third difference value (Column 11, lines 5-14).
As per claim 10, Mylius further discloses wherein the second number of credits is not adjusted based on the queuing of the second instruction or the queuing of the third instruction (Paragraph 7 “Furthermore, the mechanisms for choosing dispatch buffers to receive ops, and for choosing reservation stations to receive ops from the dispatch buffers, may be designed to approximate the transmission of each op to the reservation station that has the most available entries among the reservation stations that are eligible to receive that op.”).
As per claim 15, it is a device claim having similar limitations as cited in claim 2 and is thus rejected under the same rationale.
As per claim 16, it is a device claim having similar limitations as cited in claim 3 and is thus rejected under the same rationale.
As per claim 18, it is a device claim having similar limitations as cited in claim 5 and is thus rejected under the same rationale.
As per claim 19, it is a device claim having similar limitations as cited in claim 6 and is thus rejected under the same rationale.
Mylius in view of Blasco in further view of Griffith in further view of Nilsson (US 2014/0344549).
As per claim 11, Mylius does not expressly discloses but Nilsson discloses wherein the first instruction affinity comprises a branch instruction and the third instruction affinity comprises a complex ALU instruction (Paragraph 50 “There could be an arbitrary number of vector execution units, in addition to the two shown in FIG. 1. There may be only CMAC units, only CALU units or a suitable number of each type. There may also be other types of vector execution unit than CMAC and CALU. As explained above, a vector execution unit is a processor that is able to process vector instructions, which means that a single instruction performs the same function to a number of data units. Data may be complex or real, and are grouped into bytes or words and packed into a vector to be operated on by a vector execution unit. In this document, CALU and CMAC units are used as examples, but it should be noted that vector execution units may be used to perform any suitable function on vectors of data.”).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Mylius as modified to include the teachings of Nilsson because it allows a known CALU resource to predictably employ processor affinity.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (US 20170060592) discloses a processor chip can have a pre-execution pipeline sharing a plurality of resources including at least one resource of interest, a resource tracker having more than one credit unit associated to each one of said at least one resource of interest. The method can include: decoding the instruction data to determine a resource requirement including a quantity of virtual credits required from the credit units for the at least one resource of interest, checking the resource tracker for an availability of said quantity of virtual credits and, if the availability of the amount of said virtual credits is established, i) dispatching the instruction data, and ii) subtracting the quantity of said credits from the resource tracker.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY A MUDRICK whose telephone number is (571)270-3374. The examiner can normally be reached 9am-5pm Central Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached at (571)272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TIMOTHY A MUDRICK/Primary Examiner, Art Unit 2198 9/15/2026
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