Detailed Action
The instant application having Application No. 18/824,080 has a total of 18 claims pending in the application; there are 2 independent claims and 16 dependent claims, all of which are ready for examination by the examiner. This Office action is in response to the claims filed 4/22/26. Claims 1-18 are pending.
NOTICE OF PRE-AIA OR AIA STATUS
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10-12 and 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Iwai et al. (U.S. Patent Application Publication No. 2019/0303024), herein referred to as Iwai et al. in view of Kang (U.S. Patent Application Publication No. 2013/0222009), herein referred to as Kang.
Referring to claim 1, Iwai et al. disclose as claimed, a memory control circuit, comprising: an access control circuit, sending a read command, a write command, or a power save command (see fig. 1, showing a memory controller which would send read and write commands. Also see para. 37, where the controller may be a circuit), wherein the access control circuit sends the power save command when idle (see para. 169, where the power save state is entered after an idle period); a connection pad circuit (see para. 39-40 where the controller is connected to memory with an interface such as Toggle DDR, ONFI or a similar interface. ONFI for example, utilizes pads), comprising: a transceiver circuit; and a receiver circuit, wherein the transceiver circuit and the receiver circuit are connected to a memory through an external pad (see fig. 1, showing a controller connected to a DRAM and NAND, showing channels connecting them, with data flowing both ways, and a read and write control module. Also see para. 39-40, describing a Toggle DDR or ONFI which utilize pads to connect to memory); and a pad control circuit, connected between the access control circuit and the receiver circuit, wherein the pad control circuit executes the read command to enable the receiver circuit to receive read data from the memory through the external pad (see fig. 1, showing specific NAND and DRAM interfaces which allow for receiving read data and executing read commands from memory. See para. 39-40, where interfaces utilizing connection pads are described); and the pad control circuit executes the write command or receives the read data to turn off output of the receiver circuit to enable the receiver circuit to enter a power save state (see para. 149, where read commands are executed and data read up to a limit of the buffer capacity, and then the SSD transitions to a low power consumption state. Note that Kang shows in fig. 1 where the receiver circuit is part of the memory).
Iwai et al. disclose the claimed invention except for in the power save state, executes the power save command to decrease an operating current of the receiver circuit to a current value of a minimum level and forces an internal signal of the receiver circuit to a level to enable the receiver circuit to enter a deep power save state;
However, Kang discloses in the power save state, executes the power save command to decrease an operating current of the receiver circuit to a current value of a minimum level and forces an internal signal of the receiver circuit to a level to enable the receiver circuit to enter a deep power save state (see para. 29, where a deep power down signal is generated, and all current paths of the semiconductor module are disconnected, which would decrease the operating current of the receiving circuit to zero which would constitute a minimum level);
Iwai et al. and Kang are analogous art because they are from the same field of endeavor of memory power consumption (see Iwai et al., para. 3-7 and Kang, abstract, regarding memory power consumption).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Iwai et al. to comprise in the power save state, executing the power save command to decrease an operating current of the receiver circuit to a current value of a minimum level and forces an internal signal of the receiver circuit to a level to enable the receiver circuit to enter a deep power save state, as taught by Kang, in order to allow for even more power savings and efficient operation when memory operations aren’t needed.
Referring to claim 10, Iwai et al. disclose as claimed, a memory control circuit control method, comprising: receiving a read command; executing the read command to receive read data from a memory by a receiver circuit (see fig. 1, showing a memory controller which would send read and write commands to and from a memory. See interfaces with channels connecting the controller to the memory which would constitute a receiver circuit); controlling the receiver circuit to enter a power save state after the read data is received or a write command is executed (see para. 149, where read commands are executed and data read up to a limit of the buffer capacity, and then the SSD transitions to a low power consumption state. Note that Kang fig. 1 shows where the receiver is part of the memory);
Iwai et al. disclose the claimed invention except for in the power save state, receiving and executing a power save command to control the receiver circuit to enter a deep power save state from the power save state, wherein a step of entering the power save state comprises: turning off output of the receiver circuit; and a step of entering the deep power save state comprises: turning off the output of the receiver circuit; decreasing an operating current of the receiver circuit to the minimum; and forcing an internal signal of the receiver circuit to a level.
However, Kang discloses in the power save state, receiving and executing a power save command to control the receiver circuit to enter a deep power save state from the power save state, wherein a step of entering the power save state comprises: turning off output of the receiver circuit; and a step of entering the deep power save state comprises: turning off the output of the receiver circuit; decreasing an operating current of the receiver circuit to the minimum; and forcing an internal signal of the receiver circuit to a level (see para. 29, where a deep power down signal is generated, and all current paths of the semiconductor module are disconnected, which would decrease the operating current of the receiving circuit to zero which would constitute a minimum level, as well as a deep power down signal being forced high. Also see Iwai, para. 169-179, where a deep power state is entered into from the power save state, and both states have the receiver output turned off).
Iwai et al. and Kang are analogous art because they are from the same field of endeavor of memory power consumption (see Iwai et al., para. 3-7 and Kang, abstract, regarding memory power consumption).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Iwai et al. to comprise in the power save state, receiving and executing a power save command to control the receiver circuit to enter a deep power save state from the power save state, wherein a step of entering the power save state comprises: turning off output of the receiver circuit; and a step of entering the deep power save state comprises: turning off the output of the receiver circuit; decreasing an operating current of the receiver circuit to the minimum; and forcing an internal signal of the receiver circuit to a level, as taught by Kang, in order to allow for even more power savings and efficient operation when memory operations aren’t needed.
As to claim 11, Iwai et al. and Kang also disclose the memory control circuit control method according to claim 10, further comprising: entering a power down state from the power save state or the deep power save state, wherein a step of entering the power down state comprises: turning off the receiver circuit (see Iwai et al. para. 169-179, where the deep power down state PS4 is entered into from the power save state PS3. See Kang, para. 29, where a deep power down signal is generated, and all current paths of the semiconductor module are disconnected, which would decrease the operating current of the receiving circuit to a minimum and turn off the receiver circuit).
As to claim 12, Iwai et al. and Kang also disclose the memory control circuit control method according to claim 10, wherein the step of entering the deep power save state further comprises: disconnecting a power supply path for providing the operating current to the receiver circuit (See Kang, para. 29, where a deep power down signal is generated, and all current paths of the semiconductor module are disconnected, which would decrease the operating current of the receiving circuit to a minimum and turn off the receiver circuit).
As to claim 14, Iwai et al. and Kang also disclose the memory control circuit control method according to claim 10, wherein a step of turning off the output of the receiver circuit comprises: forcing an output stage of the receiver circuit to be in a non-output state (See Kang, para. 29, where a deep power down signal is generated, and all current paths of the semiconductor module are disconnected, which would force an output stage of the receiver circuit to be in a non-output state).
As to claim 15, Iwai et al. and Kang also disclose the memory power save control method according to claim 14, wherein the output stage is an AND gate, a step of forcing the output stage of the receiver circuit to be in the non-output state is to provide a logic signal to an input end of the AND gate, and the logic signal is 0 (see Kang, para. 36, where if an information signal has a logic low voltage state, a power down mode signal is outputted. Although Kang doesn’t explicitly disclose using an AND gate, it would be obvious to include a logic gate such as an AND gate to also include the input of a deep power down mode signal or self-refresh signal, as discussed in para. 34).
As to claim 16, Iwai et al. and Kang also disclose the memory control circuit control method according to claim 10, a step of decreasing the operating current of the receiver circuit to the minimum comprises: decreasing an input current, wherein the operating current is generated by mapping the input current (see Kang, para. 29, where when entering a deep power down mode, the current paths are disconnected, which would decrease both the input current and the operating current for the receiver which would be tied to the input current).
As to claim 17, , Iwai et al. and Kang also disclose the memory control circuit control method according to claim 16, further comprising: entering a power down state from the power save state or the deep power save state, wherein a step of entering the power down state comprises: cutting off the input current (see Kang, para. 29, where a deep power down mode signal disconnects all current paths and therefore would cut off the input current).
Claims 2-9, 13 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Iwai et al. in view of Kang and in view of Hekmat (U.S. Patent Application Publication No. 2014/0314172), herein referred to as Hekmat.
As to claim 2, Iwai et al. and Kang disclose the claimed invention except for the memory control circuit according to claim 1, wherein the receiver circuit comprises: a current mirror circuit, controlled by the pad control circuit, and mapping an input current to generate the operating current; a comparator group, connected to the external pad, and powered by the operating current; an output stage, connected between the comparator group and the pad control circuit; and a switch circuit, connected to the comparator group, and controlled by the pad control circuit.
However, Hekmat discloses wherein the receiver circuit comprises: a current mirror circuit, controlled by the pad control circuit, and mapping an input current to generate the operating current (see para. 48 and fig. 6 showing a current being mirrored through three different comparators. Note that both Iwai et al. and Kang teach connections through pads); a comparator group, connected to the external pad, and powered by the operating current (see fig. 6, showing a comparator group of three comparators powered by the operating current. Note that both Iwai et al. and Kang teach connections through pads); an output stage, connected between the comparator group and the pad control circuit (see fig. 1b, showing where a comparator group would be placed, and an output after it); and a switch circuit, connected to the comparator group, and controlled by the pad control circuit (see fig. 1b, showing a decoder, which would be a switch circuit. Also see Kang, para. 29, where a deep power down signal and register would be a switch).
Iwai et al. and Hekmet are analogous art because they are from the same field of endeavor of power consumption (see Iwai et al., para. 3-7 and Hekmet, abstract, regarding power consumption).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Iwai et al. to comprise wherein the receiver circuit comprises: a current mirror circuit, controlled by the pad control circuit, and mapping an input current to generate the operating current; a comparator group, connected to the external pad, and powered by the operating current; an output stage, connected between the comparator group and the pad control circuit; and a switch circuit, connected to the comparator group, and controlled by the pad control circuit, as taught by Hekmet, in order to allow for reduced power consumption (see Hekmet, para. 6, where comparators in a multi-level receiver allow for reduced power consumption).
As to claim 3, Iwai et al., Kang and Hekmet also disclose the memory control circuit according to claim 2, wherein the switch circuit comprises: an operating switch, connected between the current mirror circuit and the comparator group, and controlled by the pad control circuit, wherein in the deep power save state, the pad control circuit further controls the operating switch to disconnect a power supply path that is between the current mirror circuit and the comparator group and that is configured to provide the operating current for the comparator group (see Kang, para. 29, where a deep power down signal and register would be a switch. The power down switch disconnects all current paths of the semiconductor module. Therefore, when combined with Hekmet, which teaches a current mirror circuit and comparator group, this would disconnect the power supply path there).
As to claim 4, Iwai et al., Kang and Hekmet also disclose the memory control circuit according to claim 2, wherein in the deep power save state, the pad control circuit controls the switch circuit to connect a plurality of input ends of the comparator group to a power supply and to a ground respectively to force the internal signal of the receiver circuit to the level (see Hekmet, fig. 2, showing input ends of comparator group being connected to a power supply and ground. See Kang, para. 29, where a deep power down signal switches the current off and would decrease the operating current of the receiving circuit).
As to claim 5, Iwai et al., Kang and Hekmet also disclose the memory control circuit according to claim 2, wherein in the power save state and the deep power save state, the pad control circuit forces the output stage to be in a non-output state to turn off the output of the receiver circuit (See Kang, para. 29, where a deep power down signal switches the current off and would decrease the operating current of the receiving circuit and have the receiver circuit be in a non-output state).
As to claim 6, Iwai et al., Kang and Hekmet also disclose the memory control circuit according to claim 5, wherein the output stage is an AND gate, the pad control circuit provides a logic signal to an input end of the AND gate to force the output stage to be in the non-output state, and the logic signal is 0 (see Kang, para. 36, where if an information signal has a logic low voltage state, a power down mode signal is outputted. Although Kang doesn’t explicitly disclose using an AND gate, it would be obvious to include a logic gate such as an AND gate to also include the input of a deep power down mode signal or self-refresh signal, as discussed in para. 34).
As to claim 7, Iwai et al., Kang and Hekmet also disclose the memory control circuit according to claim 2, wherein the receiver circuit further comprises: a current switch, connected between the current mirror circuit and a ground, and executing a power down command to disconnect the current mirror circuit from the ground, to enable the receiver circuit to enter a power down state (see Kang, para. 29, where a deep power down signal may disconnect all current paths, and therefore would disconnect the mirror circuit from the ground).
As to claim 8, Iwai et al., Kang and Hekmet also disclose the memory control circuit according to claim 2, wherein the comparator group comprises: a plurality of comparators, connected in series between the external pad and the pad control circuit (see Hekmet, fig. 2, showing a plurality of comparators connected in series. Both Iwai et al. and Kang teach connections via pads, so the comparators would be between pads. Also see Hekmet, fig. 1b, showing the comparator group being connected via pads/pins), wherein in the deep power save state, the pad control circuit controls the switch circuit to disconnect the current mirror circuit to turn off a first comparator in the plurality of comparators (see Hekmet, para. 48, where the FET of the first comparator is switched off depending on the voltage. See Kang, para. 29, where the deep power down switch disconnects current paths), and controls the switch circuit to connect two input ends of each of remaining comparators in the plurality of comparators to a power supply and to a ground respectively to force the internal signal of the receiver circuit to the level (see Hekmet, fig. 2, showing comparators with input ends connected to power supply and ground).
As to claim 9, Iwai et al., Kang and Hekmet also disclose the memory control circuit according to claim 2, wherein the current mirror circuit comprises: a current mirror, mapping the input current to the operating current (see Hekmet, para. 48 and fig. 6 showing a current being mirrored through three different comparators. Note that both Iwai et al. and Kang teach connections through pads); and a current adjustment circuit, connected to the current mirror, controlled by the pad control circuit, and configured to adjust the input current (see Kang, para. 29, where a deep power down signal may disconnect all current paths, and therefore adjust the input current).
As to claim 13, Iwai et al. and Kang disclose the claimed invention except for the memory control circuit control method according to claim 10, wherein a step of forcing the internal signal of the receiver circuit to the level comprises: connecting a plurality of input ends of a comparator group of the receiver circuit to a power supply and to a ground respectively.
However, Hekmat discloses wherein a step of forcing the internal signal of the receiver circuit to the level comprises: connecting a plurality of input ends of a comparator group of the receiver circuit to a power supply and to a ground respectively (see fig. 2, showing input ends of comparator group being connected to a power supply and ground).
Iwai et al. and Hekmet are analogous art because they are from the same field of endeavor of power consumption (see Iwai et al., para. 3-7 and Hekmet, abstract, regarding power consumption).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Iwai et al. to comprise wherein a step of forcing the internal signal of the receiver circuit to the level comprises: connecting a plurality of input ends of a comparator group of the receiver circuit to a power supply and to a ground respectively, as taught by Hekmet, in order to allow for reduced power consumption (see Hekmet, para. 6, where comparators in a multi-level receiver allow for reduced power consumption).
As to claim 18, Iwai et al. and Kang disclose the claimed invention except for the memory control circuit control method according to claim 10, wherein the receiver circuit comprises a plurality of comparators, and a step of forcing the internal signal of the receiver circuit to the level comprises: turning off a first comparator in the plurality of comparators, and connecting two input ends of each of remaining comparators in the plurality of comparators to a power supply and to a ground respectively.
However, Hekmat discloses wherein the receiver circuit comprises a plurality of comparators (see fig. 2, showing a plurality of comparators), and a step of forcing the internal signal of the receiver circuit to the level comprises: turning off a first comparator in the plurality of comparators (see para. 48, where the FET of the first comparator is switched off in response to a certain voltage), and connecting two input ends of each of remaining comparators in the plurality of comparators to a power supply and to a ground respectively (see fig. 2, showing input ends of comparator group being connected to a power supply and ground).
Iwai et al. and Hekmet are analogous art because they are from the same field of endeavor of power consumption (see Iwai et al., para. 3-7 and Hekmet, abstract, regarding power consumption).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Iwai et al. to wherein the receiver circuit comprises a plurality of comparators, and a step of forcing the internal signal of the receiver circuit to the level comprises: turning off a first comparator in the plurality of comparators, and connecting two input ends of each of remaining comparators in the plurality of comparators to a power supply and to a ground respectively, as taught by Hekmet, in order to allow for reduced power consumption (see Hekmet, para. 6, where comparators in a multi-level receiver allow for reduced power consumption).
Response to Arguments
Applicant's arguments filed 4/22/26 have been fully considered but they are not persuasive.
Applicant argues that Iwai and Kang do not disclose “the pad control circuit executes the write command or receives the read data to turn off output of the receiver circuit to enable the receiver circuit to enter a power save state.” Applicant argues that Kang , para. 35 states that when in a deep power down state, a control signal is still outputted, and therefore the receiver circuit is not “unable to output any signal.” The claim language states “turn off output of the receiver circuit to enable the receiver circuit to enter a power save state.” Although applicant argues that seems to mean that the receiver is unable to output any signal, there is no indication that turning off output means turning off every output. In addition, applicant has cited para. 30 and 52 for support, but para. 30 states that the receiver circuit output is turned off in step S05, which is after a power save command is executed and the receiver is already in a power save state. The claim language appears to state that the receiver output is turned off in the power save state, and not the deep power save state. Therefore it is unclear exactly when the receiver output is being turned off.
However, Iwai was cited for that element. Iwai teaches in para. 149 that read commands are executed and data read up to a limit of the buffer capacity before transitioning to a low power state. See para. 178-179, where the execution of all read processing is turned off when in the power state of PS4, therefore the receiver circuit would turn off output of the receiver circuit.
In addition, applicant argues that Kang, para. 35 states that in a deep power down state, a control signal is still outputted and therefore the receiver circuit is not “unable to output any signal.” However, Kang, para. 31 states that in a deep power down mode, the control signal CTRL1 may be disabled. Therefore it is optional to output the control signal during a deep power down mode and Kang would be outputting no signals in that situation.
Applicant argues that Kang disconnects all current paths in a deep power down mode, but in the claim language, the current paths are not disconnected but maintained at a minimum level, so that the application can be quickly awakened from the deep power save state. However, a current level of zero (when current paths are disconnected) would constitute a minimum level.
CLOSING COMMENTS
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-18 stand rejected.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALAN OTTO whose telephone number is (571)270-1626. The examiner can normally be reached M-F 8:30AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.O/Examiner, Art Unit 2132
/HOSAIN T ALAM/Supervisory Patent Examiner, Art Unit 2132
Prosecution Insights