Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Rashdan Mostafa et al. (“Differential-Time and Pulse-Amplitude Modulation Signaling for Serial Link Transceivers”, IEEE, IEEE, May 19, 2014, pages 248-253) (see IDS) in view of Hashimoto et al (US 2011/0235737 A1)
With regards to claim 1, Rashdan Mostafa et al discloses a data transmission circuit system (fig. 2, The block diagram of the PAM-DTS serial link, transmitter side shown in more detail in fig.3) and using an edge (rising edge and falling edge) of a pulse signal (see abstract: ” pulse-position modulation (PPM) of the rising and falling edges of the input clock signal”) , the data transmission circuit system (fig. 2) comprising:
a data pulse generation circuit ( see fig. 3, the two PPM blocks and the signal combination block) configured to receive a digital signal (see fig. 3, A0,- - - , An-1, B0, -- --, BN-1) and generate, based on a clock pulse signal (fig. 3, signals clock and its inverse clock), a data pulse signal (signal trace 4 output from the signal combination block in fig.3 and shown in fig. 7(c) The eye diagram of the data signal) with a first type (a rising) edge of a time level ( signal trace 2 output from the upper PPM block in fig. 3 and also shown in fig.7(a)) corresponding to the digital signal (see page 249, first paragraph , right column, 1) DTS Modulation, The DTS modulation shown in fig. 3 modulates 2N number of bits. The input bits-- - -);
Rashdan Mostafa et al shows the input clock signals in fig. 3, which must have been previously generated, clock and clock(with bar)) with a first type (a rising) edge of a base time level that is a basis of the time level (see page 249, first paragraph , right column, 1) DTS Modulation,-- - -the positive and negative edge of the input clock signal are modulated independently and thus, by definition, these edges form the bases of the modulated rising and falling edge, respectively of the generated data pulse signal shown in fig. 7(c) ; and
a transmission interface circuit configured to transmit the data pulse signal (see fig. 3, n-type and p-type DAC for PAM modulation produce a “PAM-DTS transmitted signals”), wherein a time difference between a first type (rising) edge of the clock pulse signal and a first type (rising) edge of the data pulse signal indicates the time level (correspondingly, the clock’s falling edge is delayed by the lower PPM block shown in fig. 3. See equation (1) on page 249, first paragraph, right column,
Rashdan Mostafa et al does not explicitly show a clock pulse generation circuit configured to generate the clock pulse signal.
However, Hashimoto et al in the same endeavor (data transmission circuit system using edge of a pulse signal) discloses in fig. 1, [0027], a transmission unit 1. In [0034], the clock pulse generating circuit 7 is configured such that it detects, based on the output of the AND circuit 9, a state transition of the clock signal "Clk" from L level to H level and generates a clock pulse corresponding to the clock signal "Clk".
Thus, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the inventions and modify Rashdan Mostafa et al ‘s Transmitter circuit with Hashimoto et al clock pulse generating circuit. For this combination, the motivation would have been to improve communications systems, performing high-accuracy isolated communication with simple configurations (see. Hashimoto et al [0019]) MPEP 2143, Rationale C.
With regards to claim 2, the combination of Rashdan Mostafa et al and Hashimoto et al discloses the data transmission circuit system of claim 1, wherein the data pulse generation circuit is further configured to generate the data pulse signal by delaying the clock pulse signal according to the time level corresponding to the digital signal (See Rashdan Mostafa et al, page 249, first paragraph, right column, 1) DTS Modulation and equation (1)).
With regards to claim 9, Rashdan Mostafa et al discloses the data transmission circuit system (fig. 2, The block diagram of the PAM-DTS serial link, transmitter side shown in more detail in fig.3) of claim 1, wherein the first type edge is one of a rising edge and a falling edge (see abstract: “pulse-position modulation (PPM) of the rising and falling edges of the input clock signal).
With regards to claim 10, A data transmission method using an edge of a pulse signal, the data transmission method comprising: receiving a digital signal; generating a clock pulse signal with a first type edge of a base time level that is a basis of a time level; generating, based on the clock pulse signal, a data pulse signal with a first type edge of a time level corresponding to the digital signal; and transmitting the data pulse signal, wherein a time difference between a first type edge of the clock pulse signal and a first type edge of the data pulse signal indicates the time level (claim 10, recites a data transmission method of the circuit of claim1, similar limitations as in claim 1 above. Claim 10 is therefore rejected similarly as in claim 1 above.)
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Rashdan Mostafa et al. (“Differential-Time and Pulse-Amplitude Modulation Signaling for Serial Link Transceivers”, IEEE, IEEE, May 19, 2014, pages 248-253) (see IDS) in view of JP 4158465 B2 (“CLOCK REPRODUCTION DEVICE AND ELECTRONIC DEVICE USING CLOCK REPRODUCTION DEVICE”, 2008-10-01, Clarivate Analytics content, pages 1-13).
With regards to claim 11, Rashdan Mostafa et al discloses a data reception circuit system (see fig. 2, The receiver side RX whose DTS demodulation is shown in more details in fig. 8) using an edge of a pulse signal (see abstract: “pulse-position modulation (PPM) of the rising and falling edges of the input clock signal), the data reception circuit system (see RX in fig. 2) comprising:
a reception interface circuit (see fig. 8 comparator) configured to receive a data pulse signal (fig. 8, received signal VR, see also signal trace 8 in fig. 11(a) comprising a data pulse signal following a reference clock pulse; Also see left column, second paragraph describing the DTS Demodulation);
a digital signal generation circuit(fig.8, upper and lower TDC stages) configured to generate ( fig. 8, fig. 8, A0,- - -AN-1, B0, - - -, BN-1) , based on a recovered clock pulse signal ( fig. 8, the recovered clock pulse signals CLK-out signal_1” and “clock_out signal_2” are input into the upper and lower TDC block, respectively; see signal trace s in fig. 11 (c ) and (e) respectively), a digital signal( fig. 8, A0,- - -AN-1, B0, - - -, BN-1) corresponding to a time level of a first type edge of the data pulse signal (see page 251, left column, second paragraph; “The first TDC circuit recovers the transmitted data- - -, which is stored in the positive edge of the data pulse signal. The second TDC circuit recovers the transmitted data- - -, which is stored in the negative edge of the data pulse signal”); and
Rashdan Mostafa et al discloses fig. 8, separation circuit, that recovered clock pulse signal with a first type edge of a base time level that is a basis of the time level (see, page 251, right column, last two sentences at top of fig. 11; the positive edge of the recovered reference clock pulse signal_1 shown in fig. 11 (c ) is the temporal basis for assessing the time difference towards the positive edge of the positive edge data signal in fig. 11(d); Also, the positive edge of the recovered reference clock pulse signal_2 in fig. 11(e ), coinciding with the negative edge of the reference clock pulse in fig. 11(b), forms the basis for the positive edge of the negative edge data signal in fig. 11(f), which edge coincides with the negative edge of the data pulse in fig. 11(b).
wherein a time difference between a first type edge of the recovered clock pulse signal and a first type edge of the data pulse signal determines the time level (see page 251, right column starting from fig. 11(c) represents the eye diagram of the recovered clock signal which is used to recover the data stored in the positive edge of the data signal- - -“).
Rashdan Mostafa et al does not explicitly show a clock recovery circuit configured to generate the recovered clock pulse signal.
However, JP 4158465 B2 in the same endeavor (a clock recovery device) discloses in [0014], the clock recovery device of the present invention is A phase determination circuit for determining a phase advance state or a phase delay state of the same direction edge of the reception data signal and the clock signal for each edge of the reception data signal, and outputting a phase determination signal; An inversion control circuit that generates and outputs an injection edge signal based on the phase determination signal and the received data signal, and an edge detection circuit that outputs an edge detection signal having a constant pulse width when an edge is detected in the received data signal. In [0016], The phase determination circuit includes a D flip-flop that inputs the clock signal in response to a rising edge trigger of the received data signal. Also see claim 1, “In a clock recovery device that recovers and outputs a clock signal from a received data signal,- - - “
Thus, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the inventions and modify Rashdan Mostafa et al ‘s Reception circuit system with JP 4158465 B2 ‘s clock recovery device technique. For this combination, the motivation would have been to improve the communication speed in order to solve next-generation high-speed multi-channel communication device. (see JP 4158465 B2, [0013]) MPEP 2143, Rationale C.
With regards to claim 19, Rashdan Mostafa et al discloses the data reception circuit system (see fig. 2, The receiver side RX whose DTS demodulation is shown in more details in fig. 8) of claim 11, wherein the first type edge is one of a rising edge and a falling edge (see abstract: “pulse-position modulation (PPM) of the rising and falling edges of the input clock signal).
Allowable Subject Matter
Claims 3-8 and 12-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior arts cited alone or in combination provides the motivation to teach the data transmission circuit system of claim 1, wherein the clock pulse generation circuit is further configured to generate a plurality of clock pulse signals with different phases, and the data pulse generation circuit is further configured to generate sub-data pulse signals by respectively delaying the plurality of clock pulse signals according to time levels corresponding to the digital signal, and generate the data pulse signal by combining the sub-data pulse signals with each other as recited in claim 3;
the data reception circuit system of claim 11, wherein the digital signal generation circuit comprises: a time-digital conversion circuit configured to generate a digital stream signal corresponding to a time level of the data pulse signal; and a parallelization circuit configured to generate the digital signal by parallelizing the digital stream signal as recited in claim 12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al (US 20100290517) discloses pulse edge demodulation.
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/HELENE E TAYONG/Primary Examiner, Art Unit 2631 December 27, 2025