NEURAL NETWORK COMPUTATION CIRCUIT

DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . 1. Claims 1-15 are present for examination. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 2. Claims 1 & 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kouno et al (US 11,604,974). Claims 1 & 15, Kouno (Fig. 1-2) clearly shows a neural network computation circuit (see Fig. 2 as example, input layer 1 -> hiddenlayer2 -> output layer3), that holds a plurality of connection weight coefficients (10) in one-to-one correspondence with a plurality of input data items (input layer 1), and each of which selectively takes on a first logical value or a second logical value, and outputs output data (output layer 3) having the first logical value or the second logical value according to a result of a multiply-accumulate operation (see Figs. 3-4 as example, function y = summation equation of Wi x Xi, etc.) on the plurality of input data items and the plurality of connection weight coefficients in one-to-one correspondence, the neural network computation circuit further comprising the following components: at least two bits of semiconductor storage elements (see Fig. 1B, elements Rp + Rn) provided for each of the plurality of connection weight coefficients, the at least two bits of semiconductor storage elements including a first semiconductor storage element Rp and a second semiconductor storage element Rn that are provided for storing the connection weight coefficient, wherein each storage element is at least a variable resistance element, and that the plurality of connection weight coefficients corresponds to a total current value that is a sum of a current value flowing through both said first and second semiconductor storage elements. Patricianly, Fig. 8B (see below illustrations) shows an equation representing a summation of both current values flowing through two storage elements Rpi & Rni of a selected accessed row, and the output current is the arrow Y representing such total current value. [AltContent: textbox (Multiplication of connection weight coefficients Wi, for whole neural/network connections from a matrix of rows & columns. See also Figs. 1-2, 10-11, & 13A)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow] PNG media_image1.png 712 480 media_image1.png Greyscale PNG media_image2.png 272 384 media_image2.png Greyscale [AltContent: textbox (Total/summation or both current values going through two adjacent storage elements/resistances Rpi & Rni )] 3. Claims 1 & 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Myung et al (Us 221/0303266). Claims 1 & 15, Myung (see Fig. 1, 3A-3B & 6) clearly shows a neural network computation circuit that holds a plurality of connection weight coefficients (see Fig. 2, hidden layers 1-2, and see three weights W11, W21 & W31 applied to the three adjacent resistance storage elements R11, R12 & R13 as example) in one-to-one correspondence with a plurality of input data items (X1, X2 & X3 in Fig. 6), and each of which selectively takes on a first logical value or a second logical value, and outputs having the first logical value or the second logical value according to a result of a multiply-accumulate operation (see Fig. 2, output layer as example) on the plurality of input data items and the plurality of connection weight coefficients in one-to-one correspondence, the neural network computation circuit further comprising the following components: at least two bits of semiconductor storage elements (see Fig. 6, resistance [AltContent: arrow][AltContent: textbox (Multiplication of connection weight coefficients Wi, for whole neural/network connections from a matrix of rows & columns. )]elements R11, R12 or R13) provided for each of the plurality of connection weight coefficients, that are provided for storing a respective connection weight coefficient, wherein each storage element has at least a variable resistance elements (R11a-b, R12a-b, & R13a-b), and that the plurality of connection weight coefficients corresponds to a total current value that is a sum of a current value flowing through both said first and second semiconductor storage element. PNG media_image3.png 324 554 media_image3.png Greyscale Patricianly, Figs. 6-7 (see below illustrations) shows circuit realizing a summation of the current values flowing through at least two storage elements on a same column that can be used as an output current on the output layer. [AltContent: textbox (Total/summation or the out current values going through at least two adjacent storage elements/resistances on a same column or BL)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow] PNG media_image4.png 672 310 media_image4.png Greyscale PNG media_image5.png 708 238 media_image5.png Greyscale Allowable Subject Matter 4. Claims 5-14 are allowable over the prior arts of record for reciting novel limitations which are not seen elsewhere at this time. Additionally, claims 2-4 are tentatively objected as being dependent upon its parent/rejected claim 1 but they also include other novel limitations which are also not clearly suggested by the prior art teachings at this time. 5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VIET Q NGUYEN/Primary Examiner, Art Unit 2827