DETAILED ACTION
Claim 31, line 4, is objected to because of the “PWM” is not spelled out in an independent claim. Correction/clarification is required.
Claim 32, last line, is objected to because of the phrase “a output rate” is mistyped. It should be amended to read as -- an output rate --. Correction/clarification is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-18, 30-31, and 33-35 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-30 of U.S. Patent No. 12,119,834. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims are anticipated by the patented claims – claims are reproduced for comparison in a table below.
Claims No.: __ application no. 18,824,537
Claim No.: __ of USP 12,119,834
1. Driver circuitry comprising: a loop filter configured to receive an analog input signal and to output a digital loop filter output signal based on the analog input signal and an analog feedback signal; and a modulator configured to receive a digital signal based on the digital loop filter output signal and to output a modulated signal, wherein the driver circuitry further comprises a feedback path coupled to an output of the driver circuitry for the analog feedback signal.
1. Pulse width modulation (PWM) driver circuitry comprising: a loop filter configured to receive an analog input signal and to output a digital loop filter output signal based on the analog input signal and an analog feedback signal; and a PWM modulator configured to receive a digital signal based on the digital loop filter output signal and to output a PWM signal, wherein the PWM driver circuitry further comprises a feedback path coupled to an output of the PWM driver circuitry for the analog feedback signal.
2. Driver circuitry according to claim 1, further comprising a digital feedforward path configured to receive a digital input signal and to output a digital feedforward signal, wherein the digital signal received by the modulator signal is based on the digital loop filter output signal and the digital feedforward signal.
2. PWM driver circuitry according to claim 1, further comprising a digital feedforward path configured to receive a digital input signal and to output a digital feedforward signal, wherein the digital signal received by the PWM modulator is based on the digital loop filter output signal and the digital feedforward signal.
3. Driver circuitry according to claim 1, further comprising a power driver configured to receive the modulated signal output by the modulator and to generate a drive signal for driving a load coupled to the driver circuitry.
3. PWM driver circuitry according to claim 1, further comprising a power driver configured to receive the PWM signal output by the PWM modulator and to generate a drive signal for driving a load coupled to the PWM driver circuitry.
4. Driver circuitry according to claim 3, wherein an output of the power driver is coupled to the output of the driver circuitry, such that the feedback path for the analog feedback signal receives the drive signal.
4. PWM driver circuitry according to claim 3, wherein an output of the power driver is coupled to the output of the PWM driver circuitry, such that the feedback path for the analog feedback signal receives the drive signal.
5. Driver circuitry according to claim 3, wherein the power driver comprises multi-level converter (MLC) circuitry.
5. PWM driver circuitry according to claim 3, wherein the power driver comprises multi-level converter (MLC) circuitry.
6. Driver circuitry according to claim 3, further comprising a digital feedforward path configured to receive a digital input signal and to output a digital feedforward signal, wherein the digital signal received by the modulator signal is based on the digital loop filter output signal and the digital feedforward signal, wherein the digital feedforward path comprises a digital correction element configured to apply a correction to a signal in the digital feedforward path to correct or compensate, at least partially, for error introduced by the power driver and/or the load.
6. PWM driver circuitry according to claim 3, further comprising a digital feedforward path configured to receive a digital input signal and to output a digital feedforward signal, wherein the digital signal received by the PWM modulator is based on the digital loop filter output signal and the digital feedforward signal, wherein the digital feedforward path comprises a digital correction element configured to apply a correction to a signal in the digital feedforward path to correct or compensate, at least partially, for error introduced by the power driver and/or the load.
7. Driver circuitry according to claim 6, wherein the digital correction element comprises one or more of: a digital gain element for applying a digital gain to the signal in the digital feedforward path; and an adaptive digital filter.
7. PWM driver circuitry according to claim 6, wherein the digital correction element comprises one or more of: a digital gain element for applying a digital gain to the signal in the digital feedforward path; and an adaptive digital filter.
8. Driver circuitry according to claim 1, wherein the driver circuitry further comprises input digital to analog converter (DAC) circuitry configured to receive a digital input signal and to output the analog input signal to the loop filter.
8. PWM driver circuitry according to claim 1, wherein the PWM driver circuitry further comprises input digital to analog converter (DAC) circuitry configured to receive a digital input signal and to output the analog input signal to the loop filter.
9. Driver circuitry according to claim 1, wherein the loop filter comprises analog integrator circuitry and analog to digital converter circuitry.
9. PWM driver circuitry according to claim 1, wherein the loop filter comprises analog integrator circuitry and analog to digital converter circuitry.
10. Driver circuitry according to claim 9, wherein the loop filter comprises: first analog integrator circuitry configured to receive the analog input signal and to output a first integrated analog output signal; second analog integrator circuitry having an input coupled to an output of the first analog integrator circuitry, the second analog integrator circuitry configured to output a second integrated analog output signal; third analog integrator circuitry having an input coupled to an output of the second analog integrator circuitry, the third analog integrator circuitry configured to output a third integrated analog output signal; a first analog signal path having an input coupled to the output of the first analog integrator circuitry, the first analog signal path comprising a first analog correction element; a second analog signal path having an input coupled to the output of the second analog integrator circuitry, the second analog signal path comprising a second analog correction element; a third analog signal path having an input coupled to the output of the third analog integrator circuitry, the third analog signal path comprising a third analog correction element; an analog summing node configured to receive output signals of the first, second and third analog signal paths and to output a combined analog output signal; and analog to digital converter circuitry coupled to an output of the analog summing node and configured to convert the combined analog output signal into the digital loop filter output signal.
10. PWM driver circuitry according to claim 9, wherein the loop filter comprises: first analog integrator circuitry configured to receive the analog input signal and to output a first integrated analog output signal; second analog integrator circuitry having an input coupled to an output of the first analog integrator circuitry, the second analog integrator circuitry configured to output a second integrated analog output signal; third analog integrator circuitry having an input coupled to an output of the second analog integrator circuitry, the third analog integrator circuitry configured to output a third integrated analog output signal; a first analog signal path having an input coupled to the output of the first analog integrator circuitry, the first analog signal path comprising a first analog correction element; a second analog signal path having an input coupled to the output of the second analog integrator circuitry, the second analog signal path comprising a second analog correction element; a third analog signal path having an input coupled to the output of the third analog integrator circuitry, the third analog signal path comprising a third analog correction element; an analog summing node configured to receive output signals of the first, second and third analog signal paths and to output a combined analog output signal; and analog to digital converter circuitry coupled to an output of the analog summing node and configured to convert the combined analog output signal into the digital loop filter output signal.
11. Driver circuitry according to claim 9, wherein the loop filter further comprises digital integrator circuitry.
11. PWM driver circuitry according to claim 9, wherein the loop filter further comprises digital integrator circuitry.
12. Driver circuitry according to claim 11, wherein the loop filter comprises: first analog integrator circuitry configured to receive the analog input signal and to output a first integrated analog output signal; second analog integrator circuitry having an input coupled to an output of the first analog integrator circuitry, the second analog integrator circuitry configured to output a second integrated analog output signal; a first analog signal path having an input coupled to the output of the first analog integrator circuitry, the first analog signal path comprising a first analog correction element; a second analog signal path having an input coupled to an output of the second analog integrator circuitry, the second analog signal path comprising a second analog correction element; an analog summing node configured to receive output signals of the first and second analog signal paths and to output a combined analog output signal; analog to digital converter (ADC) circuitry coupled to an output of the analog summing node and configured to convert the combined analog output signal into an intermediate digital output signal; digital integrator circuitry coupled to an output of the ADC circuitry to receive the intermediate digital output signal, the digital integrator circuitry configured to output an integrated digital signal; a digital signal path having an input coupled to the output of the ADC circuitry, the digital signal path comprising a digital correction element; and a digital summing node configured to combine the integrated digital signal with an output signal from the digital signal path to generate the digital loop filter output signal.
12. PWM driver circuitry according to claim 11, wherein the loop filter comprises: first analog integrator circuitry configured to receive the analog input signal and to output a first integrated analog output signal; second analog integrator circuitry having an input coupled to an output of the first analog integrator circuitry, the second analog integrator circuitry configured to output a second integrated analog output signal; a first analog signal path having an input coupled to the output of the first analog integrator circuitry, the first analog signal path comprising a first analog correction element; a second analog signal path having an input coupled to an output of the second analog integrator circuitry, the second analog signal path comprising a second analog correction element; an analog summing node configured to receive output signals of the first and second analog signal paths and to output a combined analog output signal; analog to digital converter (ADC) circuitry coupled to an output of the analog summing node and configured to convert the combined analog output signal into an intermediate digital output signal; digital integrator circuitry coupled to an output of the ADC circuitry to receive the intermediate digital output signal, the digital integrator circuitry configured to output an integrated digital signal; a digital signal path having an input coupled to the output of the ADC circuitry, the digital signal path comprising a digital correction element; and a digital summing node configured to combine the integrated digital signal with an output signal from the digital signal path to generate the digital loop filter output signal.
13. Driver circuitry according to claim 11, wherein the loop filter comprises: first analog integrator circuitry configured to receive the analog input signal and to output a first integrated analog output signal; second analog integrator circuitry having an input coupled to an output of the first analog integrator circuitry, the second analog integrator circuitry configured to output a second integrated analog output signal; first analog to digital converter (ADC) circuitry having an input coupled to the output of the second analog integrator circuitry; second analog to digital converter (ADC) circuitry having an input coupled to an output of the first analog integrator circuitry; digital integrator circuitry configured to receive a digital signal output by the first ADC circuitry and to output an integrated digital signal; a digital signal path having an input coupled to an output of the first ADC circuitry, the digital signal path comprising a digital correction element; and a digital summing node configured to combine the integrated digital signal with an output signal from the digital signal path to generate the digital loop filter output signal.
13. PWM driver circuitry according to claim 11, wherein the loop filter comprises: first analog integrator circuitry configured to receive the analog input signal and to output a first integrated analog output signal; second analog integrator circuitry having an input coupled to an output of the first analog integrator circuitry, the second analog integrator circuitry configured to output a second integrated analog output signal; first analog to digital converter (ADC) circuitry having an input coupled to the output of the second analog integrator circuitry; second analog to digital converter (ADC) circuitry having an input coupled to an output of the first analog integrator circuitry; digital integrator circuitry configured to receive a digital signal output by the first ADC circuitry and to output an integrated digital signal; a digital signal path having an input coupled to an output of the first ADC circuitry, the digital signal path comprising a digital correction element; and a digital summing node configured to combine the integrated digital signal with an output signal from the digital signal path to generate the digital loop filter output signal.
14. Driver circuitry according to claim 13, wherein a sampling rate of the first ADC circuitry is different from a sampling rate of the second ADC circuitry.
14. PWM driver circuitry according to claim 13, wherein a sampling rate of the first ADC circuitry is different from a sampling rate of the second ADC circuitry.
15. Driver circuitry according to claim 9, wherein the loop filter comprises: first analog integrator circuitry configured to receive the analog input signal and to output a first integrated analog output signal; second analog integrator circuitry having an input coupled to an output of the first analog integrator circuitry, the second analog integrator circuitry configured to output a second integrated analog output signal; third analog integrator circuitry having an input coupled to an output of the second analog integrator circuitry, the third analog integrator circuitry configured to output a third integrated analog output signal; first analog to digital converter (ADC) circuitry having an input coupled to the output of the first analog integrator circuitry; second analog to digital converter (ADC) circuitry having an input coupled to the output of the second analog integrator circuitry; third analog to digital converter (ADC) circuitry having an input coupled to an output of the first analog integrator circuitry; a first digital signal path having an input coupled to the output of the first ADC circuitry, the first digital signal path comprising a first digital correction element; a second digital signal path having an input coupled to the output of the second ADC circuitry, the second digital signal path comprising a second digital correction element; a third digital signal path having an input coupled to the output of the third ADC circuitry, the third digital signal path comprising a third digital correction element; and a digital summing node configured to combine output signals of the first, second and third digital signal paths to generate the digital loop filter output signal.
15. PWM driver circuitry according to claim 9, wherein the loop filter comprises: first analog integrator circuitry configured to receive the analog input signal and to output a first integrated analog output signal; second analog integrator circuitry having an input coupled to an output of the first analog integrator circuitry, the second analog integrator circuitry configured to output a second integrated analog output signal; third analog integrator circuitry having an input coupled to an output of the second analog integrator circuitry, the third analog integrator circuitry configured to output a third integrated analog output signal; first analog to digital converter (ADC) circuitry having an input coupled to the output of the first analog integrator circuitry; second analog to digital converter (ADC) circuitry having an input coupled to the output of the second analog integrator circuitry; third analog to digital converter (ADC) circuitry having an input coupled to an output of the first analog integrator circuitry; a first digital signal path having an input coupled to the output of the first ADC circuitry, the first digital signal path comprising a first digital correction element; a second digital signal path having an input coupled to the output of the second ADC circuitry, the second digital signal path comprising a second digital correction element; a third digital signal path having an input coupled to the output of the third ADC circuitry, the third digital signal path comprising a third digital correction element; and a digital summing node configured to combine output signals of the first, second and third digital signal paths to generate the digital loop filter output signal.
16. Driver circuitry according to claim 15, wherein a sampling rate of the first ADC circuitry is different from a sampling rate of the second ADC circuitry, and/or wherein the sampling rate of the second ADC circuitry is different from a sampling rate of the third ADC circuitry.
16. PWM driver circuitry according to claim 15, wherein a sampling rate of the first ADC circuitry is different from a sampling rate of the second ADC circuitry, and/or wherein the sampling rate of the second ADC circuitry is different from a sampling rate of the third ADC circuitry.
17. Driver circuitry according to claim 9, wherein the loop filter comprises: first analog integrator circuitry; second analog integrator circuitry; multiplexer circuitry having inputs coupled to outputs of the first and second analog integrator circuitry; andanalog to digital converter (ADC) circuitry having an input coupled to an output of the multiplexer circuitry; a first digital signal path comprising a first digital correction element coupled to the output of the ADC circuitry; a second digital signal path comprising a second digital correction element coupled to the output of the ADC circuitry; and a digital summing node configured to combine output signals of the first and second digital signal paths and output a combined digital signal.
17. PWM driver circuitry according to claim 9, wherein the loop filter comprises: first analog integrator circuitry; second analog integrator circuitry; multiplexer circuitry having inputs coupled to outputs of the first and second analog integrator circuitry; analog to digital converter (ADC) circuitry having an input coupled to an output of the multiplexer circuitry; a first digital signal path comprising a first digital correction element coupled to the output of the ADC circuitry; a second digital signal path comprising a second digital correction element coupled to the output of the ADC circuitry; and a digital summing node configured to combine output signals of the first and second digital signal paths and output a combined digital signal.
18. Driver circuitry according to claim 17, wherein a sampling rate of the ADC circuitry is variable based on which of the inputs of the multiplexer circuitry is selected by the multiplexer circuitry.
18. PWM driver circuitry according to claim 17, wherein a sampling rate of the ADC circuitry is variable based on which of the inputs of the multiplexer circuitry is selected by the multiplexer circuitry.
30. Driver circuitry according to claim 1, wherein the modulator comprises a pulse width modulator.
1. “…a PWM modulator”.
31. Driver circuitry comprising: a loop filter configured to receive an analog input signal and to output a digital loop filter output signal; and a PWM modulator configured to receive a digital signal based on the digital loop filter output signal and to output a PWM signal, wherein the loop filter comprises an analog integrator and a digital integrator.
21. A hybrid loop filter comprising: an input for receiving an analog input signal; an analog integrator for receiving the analog input signal and generating an integrated analog signal; and an analog to digital converter for converting the integrated analog signal into a digital loop filter output signal. 23. A hybrid loop filter according to claim 21, wherein the hybrid loop filter further comprises digital integrator circuitry.
33. An integrated circuit comprising driver circuitry according to claim 1.
19. An integrated circuit comprising PWM driver circuitry according to claim 1.
34. A host device comprising driver circuitry according to claim 1.
29. A host device comprising a hybrid loop filter according to claim 21.
35. A host device according to claim 34, wherein the host device comprises a laptop, notebook, netbook or tablet computer, a gaming device, a games console, a controller for a games console, a virtual reality (VR) or augmented reality (AR) device, a mobile telephone, a portable audio player, a portable device, an accessory device for use with a laptop, notebook, netbook or tablet computer, a gaming device, a games console a VR or AR device, a mobile telephone, a portable audio player or other portable device.
30. A host device according to claim 29, wherein the host device comprises a laptop, notebook, netbook or tablet computer, a gaming device, a games console, a controller for a games console, a virtual reality (VR) or augmented reality (AR) device, a mobile telephone, a portable audio player, a portable device, an accessory device for use with a laptop, notebook, netbook or tablet computer, a gaming device, a games console a VR or AR device, a mobile telephone, a portable audio player or other portable device.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAI M NGUYEN whose telephone number is (571)272-1809. The examiner can normally be reached Mon-Fri: 8:00 am - 4:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dameon E. Levi can be reached at 571-272-2105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHAI M NGUYEN/Primary Examiner, Art Unit 2845