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Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/20/2026 has been entered.
Response to Amendment
In response to the claim amendment, in view of the Remarks filed 08/20/2026, the claim objection have been withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3 – 6, 8 – 11, 13 – 16 and 18 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over the prior art of record, Shanbhogue et al., (US 2021/0311643 A1) (hereinafter “Shanbhogue”) in view of the prior art of record, Lee at al., (US 2008/02322592 A1) (hereinafter “Lee”).
Regarding claim 1, Shanbhogue discloses; a memory device coupled to a computing device [i.e., (see figures 1 and 6)], the memory device comprising:
a volatile storage medium [i.e., primary memory 430 may be composed of one or more memory devices or dies which may include various types volatile memory (see ref. 430 of figure 4), (page 11, para 0094)];
a non-volatile storage medium [i.e., non-volatile memories (NVM) 465 (see figure 4), (page 11, para 0092) i.e., persistent device memory 134 (see figure 1), (page 4, para 0034) i.e., primary memory 430 may be composed of one or more memory devices or dies which may include various types of non-volatile memory (page 11, para 0094)]; and
a processor [i.e., processing component 602 (see figure 6), (page 12, para 0097)] configured to communicate with the volatile storage medium and the non-volatile storage medium [i.e., (see figure 6)], the processor being configured to:
store one or more keys [i.e., i.e., the memory device implements a random number generator to generate this random key and programs the generated random key into the Memory Encryption Engine (MEE) (a key table is implemented inside the MEE to hold these keys) (page 6, para 0064), (see figure 1) i.e., memory device support multiple memory encryption kyes. Each key…is identified by a key ID…(page 6, para 0053)];
receive transmitted data from the computing device [i.e., applicable transaction types for Type 3 include CXL mem, memory read (MemRd) and memory write (MemWr) transactions (page 2, para 0022), (see figure 1) i.e., secure access…by encrypting data transfers from the TEE VM to the memory device (see Abstract)];
identify a first key of the one or more keys associated with the transmitted data [i.e., the MEE uses the MKID of an incoming request to determine the key to use for encryption/decryption…(page 6, para 0064), (see figure 1) i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)];
encrypt the transmitted data based on the first key [i.e., memory encryption involves using a cryptographic cipher to enforce confidentiality of the data stored in the memory device (page 3, para 0026), (see figure 1) i.e., the MEE uses the MKID…to determine the key to use for encryption/decryption to the CXL attached memory (page 6, para 0064)], and output a first encrypted data [i.e., Note; the output of the encryption engine is encrypted data written to memory];
store the first encrypted data in the non-volatile storage medium [i.e., in some cases, the keys may be ephemeral (e.g., when the memory media in device memory 134 is not persistent). In other cases, the memory media in device memory 134 is persistent…(page 4, para 0035) i.e., non-volatile memories (NVM) 465 (see figure 4), (page 11, para 0092) i.e., persistent device memory 134 (see figure 1), (page 4, para 0034)].
Shanbhogue does not disclose;
receive a memory access request; determine a cache miss for the memory access request; and
based on determining the cache miss: decrypt the first encrypted data based on the first key and output a first decrypted data: and store the first decrypted data in the volatile storage medium; identify a second decrypted data stored in the volatile storage medium based on a fullness attribute of the volatile storage medium; evict the second decrypted data from the volatile storage medium, wherein evicting the second decrypted data, the processor is further configured to: encrypt the second decrypted data based on a second key of the one or more keys to generate a second encrypted data; and store the second encrypted data in the non-volatile storage medium.
However, Lee discloses;
receive a memory access request [i.e., input/output layer 208 receives a data block from storage medium 210 in response to data storage system 130 executing an operation received from user 112 (page 3, para 0064), (page 5, para 0086), (see figures 2 – 3 and 6)];
determine a cache miss for the memory access request [i.e., each time a data storage system transaction or operation causes the storage management system to retrieves a data block from a storage medium, the storage management system decrypts the data block before storing the data block in a buffer cache (page 2, para 0024), (page 3, para 0063), (see figure 3) i.e., buffer cache 204, which includes volatile memory that is used to temporarily store a copy of a data that user 112 is currently accessing (pager 3, para 0052), (see figure 2) i.e., the process of writing a data block to a storage medium 210 occurs in response to buffer cache 204 being full…evicting a data block from buffer cache 204 (page 4, para 0081), (see figurer 5) Note; the system is retrieving the block from storage medium and then loading it into the volatile buffer cache based on a conventional cache fill/eviction model. Thus, there is a determination that the requested block is not present in the cache in usable form. In computer architecture/database technology, this operational condition corresponds to a cache miss or buffer cache miss]; and
based on determining the cache miss: decrypt the first encrypted data based on the first key [i.e., decrypt the encrypted data block using the retrieved storage key (see ref. 308 – 310 of figure 3), (page 4, para 0066 and 0072)] and a first output decrypted data [i.e., output layer 208 (page 4, para 0072), (see figures 2 and 3)]: and store the first decrypted data in the volatile storage medium [i.e., input/output layer 208 then stores the decrypted data block in buffer cache 204 (page 4, para 0072), (see ref. 312 of figure 3 and figure 2)];
identify a second decrypted data stored in the volatile storage medium based on a fullness attribute of the volatile storage medium [i.e., writing a data block to storage medium 210 occurs in response to buffer cache 204 being full and receiving another block (page 3, para 0053), (page 4, para 0081), (see figures 2 and 5)];
evict the second decrypted data from the volatile storage medium [i.e., evicting a data block from buffer cache 204 (page 3, para 0053), (page 4, para 0081), (see figures 2 and 5)], wherein evicting the second decrypted data, the processor is further configured to:
encrypt the second decrypted data based on a second key of the one or more keys to generate a second encrypted data [i.e., encrypts any data block that the storage management system evicts from the buffer cache…(page 2, para 0029), (page 3, para 0050) i.e., uses the storage key to encrypt the data block (see ref. 506 of figure 5), (page 5, para 0085) (page 2, para 0035)]; and
store the second encrypted data in the non-volatile storage medium [i.e., encrypts any data block that the storage management system evicts from the buffer cache before sending the data block to the storage medium (page 2, para 0029), (page 3, para 0050)].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the teachings of Shanbhogue by adapting the teachings of Lee for securing data in a data storage system without problem (See Lee; page 1, para 0006).
Regarding claim 3, Shanbhogue discloses; the memory device of claim 1, wherein the first key is assigned to a first region of the non-volatile storage medium, and the second key of the one or more keys is assigned to a second region of the non-volatile storage medium [i.e., each memory encryption key is identified by a key ID. TSM assigns a key ID to a TEE VM…memory requests…tagged with that key ID (page 3, para 0030)].
Regarding claim 4, Shanbhogue discloses; the memory device of claim 3, wherein the first region is allocated to a first virtual machine of the computing device, and the second region is allocated to a second virtual machine of the computing device [i.e., VMM 110 allocates memory (e.g., TEE VM1 memory 136, TEE VM2 memory 138…TEE VMN memory 140) for a TEE VM (e.g., TEE VM1 104, TEE VM2 106, TEE VMN 108) in device memory 134 of memory device 122 (page 6, para 0063)].
Regarding claim 5, Shanbhogue discloses; the memory device of claim 1, wherein a region of the non-volatile storage medium is allocated to a virtual machine [i.e., VMM 110 allocates memory (e.g., TEE VM1 memory 136, TEE VM2 memory 138…TEE VMN memory 140) for a TEE VM (e.g., TEE VM1 104, TEE VM2 106, TEE VMN 108) in device memory 134 of memory device 122 (page 6, para 0063)], wherein the computing device is configured to provide the first key based on allocating a region of the non-volatile storage medium to a virtual machine of the computing device [i.e., the MEE uses the MKID of an incoming request to determine the key to use for encryption/decryption…(page 6, para 0064), (see figure 1) i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)].
Regarding claim 6, Shanbhogue discloses; the memory device of claim 5, wherein the first key has a first status, wherein the processor is configured to mark the first key as having a second status different from the first status based on a command from the computing device [i.e., i.e., the memory device implements a random number generator to generate this random key and programs the generated random key into the Memory Encryption Engine (MEE) (a key table is implemented inside the MEE to hold these keys) (page 6, para 0064), (see figure 1) i.e., memory device support multiple memory encryption kyes. Each key…is identified by a key ID…(page 6, para 0053)].
Regarding claim 9, Shanbhogue discloses; the memory device of claim 1, wherein the computing device is configured to transmit a key identifier and the transmitted data in a request, wherein the processor is configured to identify the first key based on the key identifier [i.e., the MEE uses the MKID of an incoming request to determine the key to use for encryption/decryption…(page 6, para 0064), (see figure 1) i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)].
Regarding claim 10, Shanbhogue discloses; the memory device of claim 1, wherein the first key is associated with a first criterion related to the transmitted data, and a third key of the one or more keys is associated with a second criterion related to the data, wherein the processor is further configured to:
detect the first criterion [i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)]; and
select the first key based on detecting the first criterion [i.e., the MEE uses the MKID of an incoming request to determine the key to use for encryption/decryption…(page 6, para 0064), (see figure 1) i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)].
Regarding claim 11, Shanbhogue discloses; a method comprising:
storing by a memory device coupled to a computer device, one or more keys [i.e., i.e., the memory device implements a random number generator to generate this random key and programs the generated random key into the Memory Encryption Engine (MEE) (a key table is implemented inside the MEE to hold these keys) (page 6, para 0064), (see figure 1) i.e., memory device support multiple memory encryption kyes. Each key…is identified by a key ID…(page 6, para 0053)];
receiving by the memory device transmitted data from the computing device [i.e., applicable transaction types for Type 3 include CXL mem, memory read (MemRd) and memory write (MemWr) transactions (page 2, para 0022), (see figure 1) i.e., secure access…by encrypting data transfers from the TEE VM to the memory device (see Abstract)];
identifying by the memory device a first key of the one or more keys associated with the data [i.e., the MEE uses the MKID of an incoming request to determine the key to use for encryption/decryption…(page 6, para 0064), (see figure 1) i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)];
encrypting by the memory device the data based on the first key [i.e., memory encryption involves using a cryptographic cipher to enforce confidentiality of the data stored in the memory device (page 3, para 0026), (see figure 1) i.e., the MEE uses the MKID…to determine the key to use for encryption/decryption to the CXL attached memory (page 6, para 0064)], and outputting encrypted data [i.e., Note; the output of the encryption engine is encrypted data written to memory]; and
storing by memory device the encrypted data in a non-volatile storage medium of the memory device [i.e., in some cases, the keys may be ephemeral (e.g., when the memory media in device memory 134 is not persistent). In other cases, the memory media in device memory 134 is persistent…(page 4, para 0035) i.e., non-volatile memories (NVM) 465 (see figure 4), (page 11, para 0092) i.e., persistent device memory 134 (see figure 1), (page 4, para 0034)].
Shanbhogue does not disclose;
receiving a memory access request; determining a cache miss for the memory access request; and based on determining the cache miss: decrypting the first encrypted data based on the first key and output a first decrypted data: and storing the first decrypted data in the volatile storage medium; identifying a second decrypted data stored in the volatile storage medium based on a fullness attribute of the volatile storage medium; evicting the second decrypted data from the volatile storage medium, wherein the evicting the second decrypted data further comprises encrypting the second decrypted data based on a second key of the one or more keys to generate a second encrypted data; and storing the second encrypted data in the non-volatile storage medium.
However, Lee discloses;
receiving a memory access request [i.e., input/output layer 208 receives a data block from storage medium 210 in response to data storage system 130 executing an operation received from user 112 (page 3, para 0064), (page 5, para 0086), (see figures 2 – 3 and 6)];
determining a cache miss for the memory access request [i.e., each time a data storage system transaction or operation causes the storage management system to retrieves a data block from a storage medium, the storage management system decrypts the data block before storing the data block in a buffer cache (page 2, para 0024), (page 3, para 0063), (see figure 3) i.e., buffer cache 204, which includes volatile memory that is used to temporarily store a copy of a data that user 112 is currently accessing (pager 3, para 0052), (see figure 2) i.e., the process of writing a data block to a storage medium 210 occurs in response to buffer cache 204 being full…evicting a data block from buffer cache 204 (page 4, para 0081), (see figurer 5) Note; the system is retrieving the block from storage medium and then loading it into the volatile buffer cache based on a conventional cache fill/eviction model. Thus, there is a determination that the requested block is not present in the cache in usable form. In computer architecture/database technology, this operational condition corresponds to a cache miss or buffer cache miss]; and
based on determining the cache miss: decrypting the first encrypted data based on the first key [i.e., decrypt the encrypted data block using the retrieved storage key (see ref. 308 – 310 of figure 3), (page 4, para 0066 and 0072)] and a first output decrypted data [i.e., output layer 208 (page 4, para 0072), (see figures 2 and 3)]: and storing the first decrypted data in the volatile storage medium [i.e., input/output layer 208 then stores the decrypted data block in buffer cache 204 (page 4, para 0072), (see ref. 312 of figure 3 and figure 2)];
identifying a second decrypted data stored in the volatile storage medium based on a fullness attribute of the volatile storage medium [i.e., writing a data block to storage medium 210 occurs in response to buffer cache 204 being full and receiving another block (page 3, para 0053), (page 4, para 0081), (see figures 2 and 5)];
evicting the second decrypted data from the volatile storage medium [i.e., evicting a data block from buffer cache 204 (page 3, para 0053), (page 4, para 0081), (see figures 2 and 5)], wherein evicting the second decrypted data further comprises;
encrypting the second decrypted data based on a second key of the one or more keys to generate a second encrypted data [i.e., encrypts any data block that the storage management system evicts from the buffer cache…(page 2, para 0029), (page 3, para 0050) i.e., uses the storage key to encrypt the data block (see ref. 506 of figure 5), (page 5, para 0085) (page 2, para 0035)]; and
storing the second encrypted data in the non-volatile storage medium [i.e., encrypts any data block that the storage management system evicts from the buffer cache before sending the data block to the storage medium (page 2, para 0029), (page 3, para 0050)].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the teachings of Shanbhogue by adapting the teachings of Lee for securing data in a data storage system without problem (See Lee; page 1, para 0006).
Regarding claim 13, Shanbhogue discloses; the method of claim 11, wherein the first key is assigned to a first region of the non-volatile storage medium, and the second key of the one or more keys is assigned to a second region of the non-volatile storage medium [i.e., each memory encryption key is identified by a key ID. TSM assigns a key ID to a TEE VM…memory requests…tagged with that key ID (page 3, para 0030)].
Regarding claim 14, Shanbhogue discloses; the method of claim 13, wherein the first region is allocated to a first virtual machine of the computing device, and the second region is allocated to a second virtual machine of the computing device [i.e., VMM 110 allocates memory (e.g., TEE VM1 memory 136, TEE VM2 memory 138…TEE VMN memory 140) for a TEE VM (e.g., TEE VM1 104, TEE VM2 106, TEE VMN 108) in device memory 134 of memory device 122 (page 6, para 0063)].
Regarding claim 15, Shanbhogue discloses; the method of claim 11, wherein a region of the non-volatile storage medium is allocated to a virtual machine [i.e., VMM 110 allocates memory (e.g., TEE VM1 memory 136, TEE VM2 memory 138…TEE VMN memory 140) for a TEE VM (e.g., TEE VM1 104, TEE VM2 106, TEE VMN 108) in device memory 134 of memory device 122 (page 6, para 0063)], wherein the computing device is configured to provide the first key based on allocating a region of the non-volatile storage medium to a virtual machine of the computing device [i.e., the MEE uses the MKID of an incoming request to determine the key to use for encryption/decryption…(page 6, para 0064), (see figure 1) i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)].
Regarding claim 16, Shanbhogue discloses; the method of claim 15, wherein the first key has a first status, the method further comprising:
receiving by the memory device a command from the computing device [i.e., applicable transaction types for Type 3 include CXL mem, memory read (MemRd) and memory write (MemWr) transactions (page 2, para 0022), (see figure 1) i.e., secure access…by encrypting data transfers from the TEE VM to the memory device (see Abstract)]; and
marking by the memory device the first key as having a second status different from the first status based on the command [i.e., VMM 110 allocates memory (e.g., TEE VM1 memory 136, TEE VM2 memory 138…TEE VMN memory 140) for a TEE VM (e.g., TEE VM1 104, TEE VM2 106, TEE VMN 108) in device memory 134 of memory device 122 (page 6, para 0063)].
Regarding claim 19, Shanbhogue discloses; the method of claim 11, wherein the computing device is configured to transmit a key identifier and the transmitted data in a request, the method further comprising:
identifying by the memory device the first key based on the key identifier [i.e., the MEE uses the MKID of an incoming request to determine the key to use for encryption/decryption…(page 6, para 0064), (see figure 1) i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)].
Regarding claim 20, Shanbhogue discloses; the method of claim 11, wherein the first key is associated with a first criterion related to the transmitted data, and a third key of the one or more keys is associated with a second criterion related to the transmitted data, the method further comprising:
detecting by the memory device the first criterion [i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)]; and
selecting by the memory device the first key based on detecting the first criterion [i.e., the MEE uses the MKID of an incoming request to determine the key to use for encryption/decryption…(page 6, para 0064), (see figure 1) i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)].
Claim(s) 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Shanbhogue in view of Lee as applied to claims 1 and 11 above, and further in view of the prior art of record, Puthiyedath et al., (US 2014/0297938 A1) (hereinafter “Puthiyedath”).
Regarding claim 2, Shanbhogue discloses; the memory device of claim 1 [i.e., (see claim 1 above)].
Shanbhogue and Lee do not disclose;
wherein the processor is configured to transmit capacity of the non-volatile storage medium for access by the computing device as volatile memory.
However Puthiyedath discloses;
a processor is configured to transmit capacity [i.e., during boot…the BIOS…builds a number of tables that contain the configuration table for OS to read (page 7, para 0080) i.e., decode table 133 stores…a base address and a length for each of the partitions in NVRAM 130 (page 6, para 0075) i.e., NVRAM storage 150…is directly addressable in the physical memory address space, and all instructions that use memory addresses…work with the addresses of NVRAM storage 150 (page 7, para 0084)] of the non-volatile storage medium for access by the computing device as volatile memory [i.e., the affinity table allows kernel level OS code to differentiate between different portions of the system memory…such as DRAM (NM 141A) and NVRAM (FM 142) (page 7, para 0081) i.e., NVRAM 130…can be accessed at the granularity of a byte and its access latency is close to today’s volatile RAM (page 7, para 0083)].
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the teachings of Shanbhogue and Lee to enable new usages such as expanded boot space and mass storage implementation (See Puthiyedath; page 2, para 0028).
Regarding claim 12, Shanbhogue discloses; the method of claim 11 [i.e., (see claim 11 above)].
Shanbhogue and Lee do not disclose;
transmitting capacity of the non-volatile storage medium for access by the computing device as volatile memory.
However, Puthiyedath discloses;
transmitting capacity [i.e., during boot…the BIOS…builds a number of tables that contain the configuration table for OS to read (page 7, para 0080) i.e., decode table 133 stores…a base address and a length for each of the partitions in NVRAM 130 (page 6, para 0075) i.e., NVRAM storage 150…is directly addressable in the physical memory address space, and all instructions that use memory addresses…work with the addresses of NVRAM storage 150 (page 7, para 0084)] of the non-volatile storage medium for access by the computing device as volatile memory [i.e., the affinity table allows kernel level OS code to differentiate between different portions of the system memory…such as DRAM (NM 141A) and NVRAM (FM 142) (page 7, para 0081) i.e., NVRAM 130…can be accessed at the granularity of a byte and its access latency is close to today’s volatile RAM (page 7, para 0083)].
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the teachings of Shanbhogue and Lee to enable new usages such as expanded boot space and mass storage implementation (See Puthiyedath; page 2, para 0028).
Response to Arguments
Applicant's arguments in the Remarks filed 08/20/2025 have been fully considered but they are not persuasive because of the followings;
Regarding claim 1; applicant argued that “there is nothing in either Shanbhogue or Lee that teaches or suggests “identify a second decrypted data stored in the volatile storage medium based on a fullness attribute of the volatile storage medium,” and “evict the second decrypted data from the volatile storage medium,” where “in evicting the second decrypted data, the processor is further configured to: encrypt the second decrypted data based on a second key of the one or more keys to generate a second encrypted data: and store the second encrypted data in the non-volatile storage medium,.” As is now claimed in claim 1 (Emphasis added). Thus, claim 1 is now in condition for allowance” (See Remarks; page 9).
The Examiner respectfully disagrees with this argument because Lee teaches that a data block may be evicted from volatile buffer cache 204 when the buffer cache is full. Further, Lee teaches using a storage key to encrypt the data block and subsequently flushing the encrypted the data block to storage medium (see the rejection above).
Regarding claim 11; applicant argued that “claim 11 is in condition for allowance at least for reasons similar to the reasons discussed above with respect to claim 1” (See Remarks; page 9).
The Examiner respectfully disagrees with this argument because of the response to argument with respect to claim 1 above.
Regarding claims 2 – 6, 9 – 10, 12 – 16 and 19 – 20; applicant argued that each of these claims include all of the limitations of an allowed base claim, including its own limitations, that together make each of these claims are patentably distinct from the cited references (See Remarks; page 10).
The Examiner respectfully disagrees with this argument because of the response claim claims 1 and 11 above and further in view of the rejection above.
Conclusion
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/SYED A RONI/Primary Examiner, Art Unit 2432
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