DETAILED ACTION
713.09 Interviews Between Final Rejection and Notice of Appeal [R-08.2017]
Normally, one interview after final rejection is permitted in order to place the application in condition for allowance or to resolve issues prior to appeal. However, prior to the interview, the intended purpose and content of the interview should be presented briefly, preferably in writing. Such an interview may be granted if the examiner is convinced that disposal or clarification for appeal may be accomplished with only nominal further consideration. Interviews merely to restate arguments of record or to discuss new limitations which would require more than nominal reconsideration or new search should be denied. See MPEP § 714.13.
Interviews may be held after the expiration of the shortened statutory period and prior to the maximum permitted statutory period of 6 months without an extension of time. See MPEP § 706.07(f).
A second or further interview after a final rejection may be held if the examiner is convinced that it will expedite the issues for appeal or disposal of the application.
For interviews after notice of appeal, see MPEP § 1204.03.
Interview time will be revised to a limit of 1 hour per new application or RCE (utility)/CPA (design), when during prosecution, the examiner conducts an interview. When more than one interview is needed in an application supervisors will have the flexibility to approve additional time and ensure that the interviews are being used to advance prosecution.
Authorization for Internet Communications
The examiner encourages Applicant to submit an authorization to communicate with the examiner via the Internet by making the following statement (from MPEP 502.03):
“Recognizing that Internet communications are not secure, I hereby authorize the USPTO to communicate with the undersigned and practitioners in accordance with 37 CFR 1.33 and 37 CFR 1.34 concerning any subject matter of this application by video conferencing, instant messaging, or electronic mail. I understand that a copy of these communications will be made of record in the application file.”
Please note that the above statement can only be submitted via Central Fax (not Examiner's Fax), Regular postal mail, or EFS Web using PTO/SB/439.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
In response to the claims amendment, in view of the Remarks filed 03/27/2026, the claims objection have been withdrawn.
In response to the applicant’s claims amendment, in view of the Remark, the 112, 101 and double patent rejection have been withdrawn.
Claim Objections
Claims 11 – 20 are objected to because of the following informalities:
Regarding claim 11; there appears to be a typographical error “output” of -- outputting – in line 13 of the claim.
Claims 12 – 20 are dependent claims and thus also objected.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3 – 6, 8 – 11, 13 – 16 and 18 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over the prior art of record, Shanbhogue et al., (US 2021/0311643 A1) (hereinafter “Shanbhogue”) in view of Lee at al., (US 2008/02322592 A1) (hereinafter “Lee”).
Regarding claim 1, Shanbhogue discloses; a memory device coupled to a computing device [i.e., (see figures 1 and 6)], the memory device comprising:
a volatile storage medium;
a non-volatile storage medium [i.e., non-volatile memories (NVM) 465 (see figure 4), (page 11, para 0092) i.e., persistent device memory 134 (see figure 1), (page 4, para 0034)]; and
a processor [i.e., processing component 602 (see figure 6), (page 12, para 0097)] configured to communicate with the volatile storage medium and the non-volatile storage medium [i.e., (see figure 6)], the processor being configured to:
store one or more keys [i.e., i.e., the memory device implements a random number generator to generate this random key and programs the generated random key into the Memory Encryption Engine (MEE) (a key table is implemented inside the MEE to hold these keys) (page 6, para 0064), (see figure 1) i.e., memory device support multiple memory encryption kyes. Each key…is identified by a key ID…(page 6, para 0053)];
receive transmitted data from the computing device [i.e., applicable transaction types for Type 3 include CXL mem, memory read (MemRd) and memory write (MemWr) transactions (page 2, para 0022), (see figure 1) i.e., secure access…by encrypting data transfers from the TEE VM to the memory device (see Abstract)];
identify a first key of the one or more keys associated with the transmitted data [i.e., the MEE uses the MKID of an incoming request to determine the key to use for encryption/decryption…(page 6, para 0064), (see figure 1) i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)];
encrypt the transmitted data based on the first key [i.e., memory encryption involves using a cryptographic cipher to enforce confidentiality of the data stored in the memory device (page 3, para 0026), (see figure 1) i.e., the MEE uses the MKID…to determine the key to use for encryption/decryption to the CXL attached memory (page 6, para 0064)], and output encrypted data [i.e., Note; the output of the encryption engine is encrypted data written to memory];
store the encrypted data in the non-volatile storage medium [i.e., in some cases, the keys may be ephemeral (e.g., when the memory media in device memory 134 is not persistent). In other cases, the memory media in device memory 134 is persistent…(page 4, para 0035) i.e., non-volatile memories (NVM) 465 (see figure 4), (page 11, para 0092) i.e., persistent device memory 134 (see figure 1), (page 4, para 0034)].
Shanbhogue does not disclose;
receive a memory access request; determine a cache miss for the memory access request; and
based on determining the cache miss: decrypt the encrypted data based on the first key and output decrypted data: and store the decrypted data in the volatile storage medium.
However, Lee discloses;
receive a memory access request [i.e., input/output layer 208 receives a data block from storage medium 210 in response to data storage system 130 executing an operation received from user 112 (page 3, para 0064), (page 5, para 0086), (see figures 2 – 3 and 6)];
determine a cache miss for the memory access request [i.e., each time a data storage system transaction or operation causes the storage management system to retrieves a data block from a storage medium, the storage management system decrypts the data block before storing the data block in a buffer cache (page 2, para 0024), (page 3, para 0063), (see figure 3) i.e., buffer cache 204, which includes volatile memory that is used to temporarily store a copy of a data that user 112 is currently accessing (pager 3, para 0052), (see figure 2) i.e., the process of writing a data block to a storage medium 210 occurs in response to buffer cache 204 being full…evicting a data block from buffer cache 204 (page 4, para 0081), (see figurer 5) Note; the system is retrieving the block from storage medium and then loading it into the volatile buffer cache based on a conventional cache fill/eviction model. Thus, there is a determination that the requested block is not present in the cache in usable form. In computer architecture/database technology, this operational condition corresponds to a cache miss or buffer cache miss]; and
based on determining the cache miss: decrypt the encrypted data based on the first key [i.e., decrypt the encrypted data block using the retrieved storage key (see ref. 308 – 310 of figure 3), (page 4, para 0066 and 0072)] and output decrypted data [i.e., output layer 208 (page 4, para 0072), (see figures 2 and 3)]: and store the decrypted data in the volatile storage medium [i.e., input/output layer 208 then stores the decrypted data block in buffer cache 204 (page 4, para 0072), (see ref. 312 of figure 3 and figure 2)].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the teachings of Shanbhogue by adapting the teachings of Lee for securing data in a data storage system without problem (See Lee; page 1, para 0006).
Regarding claim 3, Shanbhogue discloses; the memory device of claim 1, wherein the first key is assigned to a first region of the non-volatile storage medium, and a second key of the one or more keys is assigned to a second region of the non-volatile storage medium [i.e., each memory encryption key is identified by a key ID. TSM assigns a key ID to a TEE VM…memory requests…tagged with that key ID (page 3, para 0030)].
Regarding claim 4, Shanbhogue discloses; the memory device of claim 3, wherein the first region is allocated to a first virtual machine of the computing device, and the second region is allocated to a second virtual machine of the computing device [i.e., VMM 110 allocates memory (e.g., TEE VM1 memory 136, TEE VM2 memory 138…TEE VMN memory 140) for a TEE VM (e.g., TEE VM1 104, TEE VM2 106, TEE VMN 108) in device memory 134 of memory device 122 (page 6, para 0063)].
Regarding claim 5, Shanbhogue discloses; the memory device of claim 1, wherein a region of the non-volatile storage medium is allocated to a virtual machine [i.e., VMM 110 allocates memory (e.g., TEE VM1 memory 136, TEE VM2 memory 138…TEE VMN memory 140) for a TEE VM (e.g., TEE VM1 104, TEE VM2 106, TEE VMN 108) in device memory 134 of memory device 122 (page 6, para 0063)], wherein the computing device is configured to provide the first key based on allocating a region of the non-volatile storage medium to a virtual machine of the computing device [i.e., the MEE uses the MKID of an incoming request to determine the key to use for encryption/decryption…(page 6, para 0064), (see figure 1) i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)].
Regarding claim 6, Shanbhogue discloses; the memory device of claim 5, wherein the first key has a first status, wherein the processor is configured to mark the first key as having a second status different from the first status based on a command from the computing device [i.e., i.e., the memory device implements a random number generator to generate this random key and programs the generated random key into the Memory Encryption Engine (MEE) (a key table is implemented inside the MEE to hold these keys) (page 6, para 0064), (see figure 1) i.e., memory device support multiple memory encryption kyes. Each key…is identified by a key ID…(page 6, para 0053)].
Regarding claim 8, Shanbhogue discloses; the memory device of claim 1, wherein the processor is further configured to:
identify second data in the volatile storage medium for being removed from the volatile storage medium [i.e., the MEE uses the MKID of an incoming request to determine the key to use for encryption/decryption…(page 6, para 0064), (see figure 1) i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)];
encrypt the second data based on a second key of the one of the one or more keys, and output a second encrypted data [i.e., memory encryption involves using a cryptographic cipher to enforce confidentiality of the data stored in the memory device (page 3, para 0026), (see figure 1) i.e., the MEE uses the MKID…to determine the key to use for encryption/decryption to the CXL attached memory (page 6, para 0064)]; and
store the second encrypted data in the non-volatile storage medium [i.e., in some cases, the keys may be ephemeral (e.g., when the memory media in device memory 134 is not persistent). In other cases, the memory media in device memory 134 is persistent…(page 4, para 0035) i.e., non-volatile memories (NVM) 465 (see figure 4), (page 11, para 0092) i.e., persistent device memory 134 (see figure 1), (page 4, para 0034)].
Regarding claim 9, Shanbhogue discloses; the memory device of claim 1, wherein the computing device is configured to transmit a key identifier and the transmitted data in a request, wherein the processor is configured to identify the first key based on the key identifier [i.e., the MEE uses the MKID of an incoming request to determine the key to use for encryption/decryption…(page 6, para 0064), (see figure 1) i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)].
Regarding claim 10, Shanbhogue discloses; the memory device of claim 1, wherein the first key is associated with a first criterion related to the transmitted data, and a second key of the one or more keys is associated with a second criterion related to the data, wherein the processor is further configured to:
detect the first criterion [i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)]; and
select the first key based on detecting the first criterion [i.e., the MEE uses the MKID of an incoming request to determine the key to use for encryption/decryption…(page 6, para 0064), (see figure 1) i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)].
Regarding claim 11, Shanbhogue discloses; a method comprising:
storing by a memory device coupled to a computer device, one or more keys [i.e., i.e., the memory device implements a random number generator to generate this random key and programs the generated random key into the Memory Encryption Engine (MEE) (a key table is implemented inside the MEE to hold these keys) (page 6, para 0064), (see figure 1) i.e., memory device support multiple memory encryption kyes. Each key…is identified by a key ID…(page 6, para 0053)];
receiving by the memory device transmitted data from the computing device [i.e., applicable transaction types for Type 3 include CXL mem, memory read (MemRd) and memory write (MemWr) transactions (page 2, para 0022), (see figure 1) i.e., secure access…by encrypting data transfers from the TEE VM to the memory device (see Abstract)];
identifying by the memory device a first key of the one or more keys associated with the data [i.e., the MEE uses the MKID of an incoming request to determine the key to use for encryption/decryption…(page 6, para 0064), (see figure 1) i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)];
encrypting by the memory device the data based on the first key [i.e., memory encryption involves using a cryptographic cipher to enforce confidentiality of the data stored in the memory device (page 3, para 0026), (see figure 1) i.e., the MEE uses the MKID…to determine the key to use for encryption/decryption to the CXL attached memory (page 6, para 0064)], and outputting encrypted data [i.e., Note; the output of the encryption engine is encrypted data written to memory]; and
storing by memory device the encrypted data in a non-volatile storage medium of the memory device [i.e., in some cases, the keys may be ephemeral (e.g., when the memory media in device memory 134 is not persistent). In other cases, the memory media in device memory 134 is persistent…(page 4, para 0035) i.e., non-volatile memories (NVM) 465 (see figure 4), (page 11, para 0092) i.e., persistent device memory 134 (see figure 1), (page 4, para 0034)].
Shanbhogue does not disclose;
receive a memory access request; determine a cache miss for the memory access request; and
based on determining the cache miss: decrypt the encrypted data based on the first key and output decrypted data: and store the decrypted data in the volatile storage medium.
However, Lee discloses;
receiving a memory access request [i.e., input/output layer 208 receives a data block from storage medium 210 in response to data storage system 130 executing an operation received from user 112 (page 3, para 0064), (page 5, para 0086), (see figures 2 – 3 and 6)];
determining a cache miss for the memory access request [i.e., each time a data storage system transaction or operation causes the storage management system to retrieves a data block from a storage medium, the storage management system decrypts the data block before storing the data block in a buffer cache (page 2, para 0024), (page 3, para 0063), (see figure 3) i.e., buffer cache 204, which includes volatile memory that is used to temporarily store a copy of a data that user 112 is currently accessing (pager 3, para 0052), (see figure 2) i.e., the process of writing a data block to a storage medium 210 occurs in response to buffer cache 204 being full…evicting a data block from buffer cache 204 (page 4, para 0081), (see figurer 5) Note; the system is retrieving the block from storage medium and then loading it into the volatile buffer cache based on a conventional cache fill/eviction model. Thus, there is a determination that the requested block is not present in the cache in usable form. In computer architecture/database technology, this operational condition corresponds to a cache miss or buffer cache miss]; and
based on determining the cache miss: decrypting the encrypted data based on the first key [i.e., decrypt the encrypted data block using the retrieved storage key (see ref. 308 – 310 of figure 3), (page 4, para 0066 and 0072)] and output decrypted data [i.e., output layer 208 (page 4, para 0072), (see figures 2 and 3)]: and storing the decrypted data in the volatile storage medium [i.e., input/output layer 208 then stores the decrypted data block in buffer cache 204 (page 4, para 0072), (see ref. 312 of figure 3 and figure 2)].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify the teachings of Shanbhogue by adapting the teachings of Lee for securing data in a data storage system without problem (See Lee; page 1, para 0006).
Regarding claim 13, Shanbhogue discloses; the method of claim 11, wherein the first key is assigned to a first region of the non-volatile storage medium, and a second key of the one or more keys is assigned to a second region of the non-volatile storage medium [i.e., each memory encryption key is identified by a key ID. TSM assigns a key ID to a TEE VM…memory requests…tagged with that key ID (page 3, para 0030)].
Regarding claim 14, Shanbhogue discloses; the method of claim 13, wherein the first region is allocated to a first virtual machine of the computing device, and the second region is allocated to a second virtual machine of the computing device [i.e., VMM 110 allocates memory (e.g., TEE VM1 memory 136, TEE VM2 memory 138…TEE VMN memory 140) for a TEE VM (e.g., TEE VM1 104, TEE VM2 106, TEE VMN 108) in device memory 134 of memory device 122 (page 6, para 0063)].
Regarding claim 15, Shanbhogue discloses; the method of claim 11, wherein a region of the non-volatile storage medium is allocated to a virtual machine [i.e., VMM 110 allocates memory (e.g., TEE VM1 memory 136, TEE VM2 memory 138…TEE VMN memory 140) for a TEE VM (e.g., TEE VM1 104, TEE VM2 106, TEE VMN 108) in device memory 134 of memory device 122 (page 6, para 0063)], wherein the computing device is configured to provide the first key based on allocating a region of the non-volatile storage medium to a virtual machine of the computing device [i.e., the MEE uses the MKID of an incoming request to determine the key to use for encryption/decryption…(page 6, para 0064), (see figure 1) i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)].
Regarding claim 16, Shanbhogue discloses; the method of claim 15, wherein the first key has a first status, the method further comprising:
receiving by the memory device a command from the computing device [i.e., applicable transaction types for Type 3 include CXL mem, memory read (MemRd) and memory write (MemWr) transactions (page 2, para 0022), (see figure 1) i.e., secure access…by encrypting data transfers from the TEE VM to the memory device (see Abstract)]; and
marking by the memory device the first key as having a second status different from the first status based on the command [i.e., VMM 110 allocates memory (e.g., TEE VM1 memory 136, TEE VM2 memory 138…TEE VMN memory 140) for a TEE VM (e.g., TEE VM1 104, TEE VM2 106, TEE VMN 108) in device memory 134 of memory device 122 (page 6, para 0063)].
Regarding claim 18, Shanbhogue discloses; the method of claim 11 further comprising:
identifying second data in a volatile storage medium of the memory device for being removed from the volatile storage medium [i.e., the MEE uses the MKID of an incoming request to determine the key to use for encryption/decryption…(page 6, para 0064), (see figure 1) i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)];
encrypting the second data based on a second key of the one of the one or more keys, and output a second encrypted data [i.e., memory encryption involves using a cryptographic cipher to enforce confidentiality of the data stored in the memory device (page 3, para 0026), (see figure 1) i.e., the MEE uses the MKID…to determine the key to use for encryption/decryption to the CXL attached memory (page 6, para 0064)]; and
storing the second encrypted data in the non-volatile storage medium [i.e., in some cases, the keys may be ephemeral (e.g., when the memory media in device memory 134 is not persistent). In other cases, the memory media in device memory 134 is persistent…(page 4, para 0035) i.e., non-volatile memories (NVM) 465 (see figure 4), (page 11, para 0092) i.e., persistent device memory 134 (see figure 1), (page 4, para 0034)].
Regarding claim 19, Shanbhogue discloses; the method of claim 11, wherein the computing device is configured to transmit a key identifier and the transmitted data in a request, the method further comprising:
identifying by the memory device the first key based on the key identifier [i.e., the MEE uses the MKID of an incoming request to determine the key to use for encryption/decryption…(page 6, para 0064), (see figure 1) i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)].
Regarding claim 20, Shanbhogue discloses; the method of claim 11, wherein the first key is associated with a first criterion related to the transmitted data, and a second key of the one or more keys is associated with a second criterion related to the transmitted data, the method further comprising:
detecting by the memory device the first criterion [i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)]; and
selecting by the memory device the first key based on detecting the first criterion [i.e., the MEE uses the MKID of an incoming request to determine the key to use for encryption/decryption…(page 6, para 0064), (see figure 1) i.e., memory devices shall support the ability to extract the key ID to be used…from the most significant bits of the address associated with the memory transaction (page 6, para 0054), (see figure 2B)].
Claim(s) 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Shanbhogue in view of Lee as applied to claims 1 and 11 above, and further in view of the prior art of record, Puthiyedath et al., (US 2014/0297938 A1) (hereinafter “Puthiyedath”).
Regarding claim 2, Shanbhogue discloses; the memory device of claim 1 [i.e., (see claim 1 above)].
Shanbhogue and Lee do not disclose;
wherein the processor is configured to transmit capacity of the non-volatile storage medium for access by the computing device as volatile memory.
However Puthiyedath discloses;
a processor is configured to transmit capacity [i.e., during boot…the BIOS…builds a number of tables that contain the configuration table for OS to read (page 7, para 0080) i.e., decode table 133 stores…a base address and a length for each of the partitions in NVRAM 130 (page 6, para 0075) i.e., NVRAM storage 150…is directly addressable in the physical memory address space, and all instructions that use memory addresses…work with the addresses of NVRAM storage 150 (page 7, para 0084)] of the non-volatile storage medium for access by the computing device as volatile memory [i.e., the affinity table allows kernel level OS code to differentiate between different portions of the system memory…such as DRAM (NM 141A) and NVRAM (FM 142) (page 7, para 0081) i.e., NVRAM 130…can be accessed at the granularity of a byte and its access latency is close to today’s volatile RAM (page 7, para 0083)].
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the teachings of Shanbhogue and Lee to enable new usages such as expanded boot space and mass storage implementation (See Puthiyedath; page 2, para 0028).
Regarding claim 12, Shanbhogue discloses; the method of claim 11 [i.e., (see claim 11 above)].
Shanbhogue and Lee do not disclose;
transmitting capacity of the non-volatile storage medium for access by the computing device as volatile memory.
However, Puthiyedath discloses;
transmitting capacity [i.e., during boot…the BIOS…builds a number of tables that contain the configuration table for OS to read (page 7, para 0080) i.e., decode table 133 stores…a base address and a length for each of the partitions in NVRAM 130 (page 6, para 0075) i.e., NVRAM storage 150…is directly addressable in the physical memory address space, and all instructions that use memory addresses…work with the addresses of NVRAM storage 150 (page 7, para 0084)] of the non-volatile storage medium for access by the computing device as volatile memory [i.e., the affinity table allows kernel level OS code to differentiate between different portions of the system memory…such as DRAM (NM 141A) and NVRAM (FM 142) (page 7, para 0081) i.e., NVRAM 130…can be accessed at the granularity of a byte and its access latency is close to today’s volatile RAM (page 7, para 0083)].
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to modify the teachings of Shanbhogue and Lee to enable new usages such as expanded boot space and mass storage implementation (See Puthiyedath; page 2, para 0028).
Response to Arguments
Applicant’s arguments with respect to pending claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SYED A RONI whose telephone number is (571)270-7806. The examiner can normally be reached M-F 9:00-5:00 pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeffrey L Nickerson can be reached at (469) 295-9235. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SYED A RONI/Primary Examiner, Art Unit 2432
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