Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/30/2026 was filed after the mailing date of the Non-Final Office action on 4/07/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Status of the Claims
Claims 1-20 set forth in the amendment submitted 7/07/2026 form the basis of the present examination.
Response to Arguments
The objection to the drawing, set forth to the Non-Final Office action mailed on 4/07/2026 has been withdrawn because of the response/amendment to the claim filed on 7/07/2026.
The objection to the Abstract, set forth to the Non-Final Office action mailed on 4/07/2026 has been withdrawn because of the amendment to the claim filed on 7/07/2026.
Applicant’s arguments, see remarks page 7-9, filed 7/07/2026, with respect to the rejection(s) of Claim(s) 1-7 under 35 U.S.C. 102 (a) (1) as being anticipated by Roessler in the US Patent Application Publication Number US 20190343001 A1 and the rejection of Claim(s) 8-20 under 35 U.S.C. 103 as being unpatentable over Roessler ‘001 A1 in view of Ying et al. (Hereinafter, “Ying”) in the US Patent Application Publication Number US 20190319385 A1 have been fully considered as follows:
Applicant’s Argument:
Applicant argues on page 7-9, of the remarks, filed on 7/07/2026, regarding the rejection(s) of Claim(s) 1-7 under 35 U.S.C. 102 (a) (1) as being anticipated by Roessler in the US Patent Application Publication Number US 20190343001 A1 and the rejection of Claim(s) 8-20 under 35 U.S.C. 103 as being unpatentable over Roessler ‘001 A1 in view of Ying et al. (Hereinafter, “Ying”) in the US Patent Application Publication Number US 20190319385 A1, that “However, Roessler does not teach or suggest this feature. In Roessler, the first conductive pad 138 is "disposed within the first conductive layer 110." See Roessler, paragraph [0031]. The conductive pad 138 is part of the via structure within the same footprint as the conductive layers. There is no extending portion of the dielectric layer where separate pads are disposed. Roessler describes a printed circuit board having a uniform rectangular structure with no extending portions beyond the conductive layer area (Remarks-Page 7).
……..
Accordingly, withdrawal of the rejection of claim 1 and claims 2-7 depending therefrom is respectfully requested.
Regarding claim 8,
However, neither Roessler nor Ying teaches or suggests the amended limitation regarding the extending portion.
As discussed above with respect to claim 1, Roessler does not teach or suggest a dielectric layer having an extending portion extending beyond the plurality of first metal contacts, with the first metal pad disposed at the extending portion. In Roessler, the conductive pad 138 is "disposed within the first conductive layer 110." See Roessler, paragraph [0031].
Ying describes a printed circuit board with DRAM elements for use in a DIMM module. Ying is cited solely for teaching a memory system coupled to a PCB, not for any structural features of the circuit (Remarks-Page 8) board itself. Ying does not describe a circuit board having an extending portion extending beyond the metal contacts, with metal pads disposed at the extending portion.
Because neither Roessler nor Ying teaches or suggests the extending portion limitation, the combination of references fails to render obvious the claimed invention. Accordingly, withdrawal of the rejection of claim 8 and claims 9-19 depending therefrom is respectfully requested.
Claim 20
As amended, claim 20 sets forth the same extending portion limitation as claim 8. For at least the same reasons discussed above with respect to claim 8, neither Roessler nor Ying teaches or suggests this such as a test method. Accordingly, withdrawal of the rejection of claim 20 is respectfully requested (Remarks-Page 9).”
Examiner Response:
Applicant’s arguments, see remarks page 7-9 (stated above), filed 7/07/2026, with respect to the rejection(s) of Claim(s) 1-7 under 35 U.S.C. 102 (a) (1) as being anticipated by Roessler in the US Patent Application Publication Number US 20190343001 A1 and the rejection of Claim(s) 8-20 under 35 U.S.C. 103 as being unpatentable over Roessler ‘001 A1 in view of Ying et al. (Hereinafter, “Ying”) in the US Patent Application Publication Number US 20190319385 A1, as applied to the Non-Final Office Action mailed on 4/07/2026 have been fully considered and is persuasive because applicant has amended the claims 1, 8 and 20. Therefore, the rejection of independent claims 1, 8 and 20 and dependent claims 2-7, 9-19 has been withdrawn. However, applicant has amended the claim 1, and added the limitation, “wherein the first side of the dielectric layer includes an extending portion extending beyond the plurality of first metal contacts, and the at least one first metal pad is disposed at the extending portion” and similar amendment for independent claims 8 and 20, which necessitates a new ground of rejection. Lin et al. (Hereinafter, “Lin”) in the US Patent Application Publication Number US 20180146559 A1 is applied to meet at least the amended limitation of claims 1, 8 and 20. Therefore, the rejection of Claim(s) 1 under 35 U.S.C. 102 (a) (1) as being anticipated by Roessler in the US Patent Application Publication Number US 20190343001 A1 and the rejection of Claim(s) 8 and 20 under 35 U.S.C. 103 as being unpatentable over Roessler ‘001 A1 in view of Ying et al. (Hereinafter, “Ying”) in the US Patent Application Publication Number US 20190319385 A1, as applied to the Non-Final Office Action mailed on 4/07/2026 has been withdrawn. Claim 1 is now rejected under 35 U.S.C. 103 as being unpatentable over Roessler in the US Patent Application Publication Number US 20190343001 A1 in view of Lin et al. (Hereinafter, “Lin”) in the US Patent Application Publication Number US 20180146559 A1 and independent claims 8 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Roessler ‘001 A1 in view of Lin ‘559 A1 and further in view of Ying et al. (Hereinafter, “Ying”) in the US Patent Application Publication Number US 20190319385 A1, as set forth below. Applicant’s argument is moot in view of newly applied combination of references. See the rejection set forth below.
Dependent Claim(s) 2-7 are rejected under 35 U.S.C. 103 as being unpatentable over Roessler in the US Patent Application Publication Number US 20190343001 A1 in view of Lin et al. (Hereinafter, “Lin”) in the US Patent Application Publication Number US 20180146559 A1 and dependent claims 9-19 are rejected under 35 U.S.C. 103 as being unpatentable over Roessler ‘001 A1 in view of Lin ‘559 A1 and further in view of Ying et al. (Hereinafter, “Ying”) in the US Patent Application Publication Number US 20190319385 A1, as set forth below. See the rejection set forth below. Applicant’s argument is moot in view of newly applied combination of references. See the rejection set forth below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s)1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Roessler in the US Patent Application Publication Number US 20190343001 A1 in view of Lin et al. (Hereinafter, “Lin”) in the US Patent Application Publication Number US 20180146559 A1.
Regarding claim 1, Roessler teaches a circuit board (printed circuit boards, and more particularly, to printed circuit boards including thick-wall conductive vias and methods of manufacturing the same; Paragraph [0002] Line 2-4; FIG. 1 is a cross-section of an exemplary printed circuit board (PCB) assembly 100 including a printed circuit board 102; Paragraph [0017] Line 1-4), comprising:
a dielectric layer [108] (As shown in FIG. 1, printed circuit board 102 includes a plurality of conductive layers 106 coupled to an insulating member 108; Paragraph [0018] Line 1-3) including at least one conductive via [130/134] (As shown in FIG. 1, printed circuit board 102 also includes a plurality of conductive vias 128 electrically coupling two or more of conductive layers 106 together; Paragraph [0027] Line 1-3; The exemplary embodiment includes three conductive vias, including a first via 130, a second via 132, and a third via 134; Paragraph [0028] Line 1-3) extending through the dielectric layer [108] (First via 130 extends through the entire thickness of printed circuit board 102, and electrically couples first conductive layer 110 to second conductive layer 112; Paragraph [0028] Line 4-7; Conductive vias that extend through the entire thickness of a printed circuit board, such as first and third vias 130 and 134; Paragraph [0029] Line 1-3);
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Figure 1: Modified Figure 1 of Roessler
a plurality of first metal contacts [110, 106], (conductive layers 110, 106 on the first side of the dielectric layer 108 as the first metal contacts) disposed on a first side of the dielectric layer [108] (The plurality of conductive layers 106 includes a first conductive layer 110, a second conductive layer 112, a third conductive layer 114, a fourth conductive layer 116, a fifth conductive layer 118, and a sixth conductive layer 120; Paragraph [0018] Line 6-9) and a plurality of second metal contacts [112, 120] disposed on a second side of the dielectric layer [108] (The plurality of conductive layers 106 includes a first conductive layer 110, a second conductive layer 112, a third conductive layer 114, a fourth conductive layer 116, a fifth conductive layer 118, and a sixth conductive layer 120; Paragraph [0018] Line 6-9; For example, first conductive layer 110 and second conductive layer 112 are separated and spaced apart from one another by at least one insulating layer defined by insulating member 108; Paragraph [0024] Line 6-3),
wherein at least one of the plurality of first metal contacts [110] is coupled with the second metal contacts [112] through the at least one conductive via [130] (The exemplary embodiment includes three conductive vias, including a first via 130, a second via 132, and a third via 134. First via 130 extends through the entire thickness of printed circuit board 102, and electrically couples first conductive layer 110 to second conductive layer 112. First via 130 is also electrically coupled to third conductive layer 114 and fifth conductive layer 118, thereby electrically coupling first, second, third, and fifth conductive layers 110, 112, 114, and 116 together…... Third via 134 extends through the entire thickness of printed circuit board 102, and electrically couples first conductive layer 110 to second conductive layer 112. Third via 134 is also electrically coupled to third, fourth, and sixth conductive layers 114, 116, and 120, thereby electrically coupling first, second, third, fourth and sixth conductive layers 110, 112, 114, 116, and 120 together; Paragraph [0028] Line 1-21; Figure 1: Modified Figure 1 of Roessler above shows that at least one of the plurality of first metal contacts [110] is coupled with the second metal contacts [112] through the at least one conductive via [130]); and
at least one first metal pad [138] located on the first side of the dielectric layer [108] and at peripheries of the plurality of first metal contacts [110] (at least one conductive pad disposed within one of the outermost conductive layers (i.e., first conductive layer 110 or second conductive layer 112) of printed circuit board 102 and configured to be electrically coupled to an electronic component (e.g., by soldering); Paragraph [0030] Line 3-5; In the exemplary embodiment, first via 130 includes a first via sidewall 136, a first conductive pad 138 disposed within the first conductive layer 110, and a second conductive pad 140 disposed within the second conductive layer 112; Paragraph [0031] Line 1-5),
wherein the first metal pad [138] is coupled with at least one of the plurality of first metal contacts [110] through a first wiring (conductive traces on first conductive layer is the first wiring as the conductive traces connects the first conductive layer with the first conductive pad) in the dielectric layer [108] (conductive traces in the conductive layer function as the first wiring to connected first metal contacts as the first conductive layer and the first conductive pad; First conductive layer 110 and second conductive layer 112 may include any suitable number of conductive traces that enable printed circuit board 102; Paragraph [0019] Line 11-14; Printed circuit boards generally include a plurality of conductive traces formed from a conductive layer to provide an electrical connection between the electronic components; Paragraph [0003] Line 3-6; Claim 5: The printed circuit board of claim 1, wherein at least one of the first conductive layer and the second conductive layer is an outermost conductive layer of the printed circuit board, the outermost conductive layer comprising a plurality of conductive traces, the conductive pad disposed within the outermost conductive layer).
Roessler fails to teach wherein the first side of the dielectric layer includes an extending portion extending beyond the plurality of first metal contacts, and the at least one first metal pad is disposed at the extending portion.
Lin teaches methods of making a wiring board, more particularly, to a method of making a stackable wiring board having an electronic component confined in a recess of a dielectric base and the component-in-recess is surrounded by an array of metal posts or plated through holes (Paragraph [0002] Line 1-6),
wherein the first side of the dielectric layer [13] in Figure 19 includes an extending portion [130] (recess 130 as the extending portion of the dielectric base 13) extending beyond the plurality of first metal contacts [113] (metal posts 113 as the metal contacts), and the at least one first metal pad [185] (contact pads 185 as the metal pad) is disposed at the extending portion [130] (FIG. 19 is a cross-sectional view of the structure with an electronic component 18 placed in the recess 130 of the dielectric base 13. The electronic component 18 is inserted into the recess 130 and attached to the floor 136 of the recess 130 by an adhesive 16. In this embodiment, the electronic component 18 is illustrated as a bare chip and has contact pads 185 at its first surface 182. The first surface 182 of the electronic component 18 faces the dielectric base 13 and contacts the adhesive 16, whereas the second surface 184 of the electronic component 18 is substantially coplanar with the second surface 106 of the metal posts 113. The sidewalls 138 of the recess 130 are laterally aligned with and in close proximity to peripheral edges of the electronic component 18 and confine the dislocation of the electronic component 18 laterally; Paragraph [091] Line 1-15; Figure 19: Modified Figure 19 of Lin below shows the first side of the dielectric layer [13] in Figure 19 includes an extending portion [130] (recess 130 as the extending portion of the dielectric base 13) extending beyond the plurality of first metal contacts [113] (metal posts 113 as the metal contacts), and the at least one first metal pad [185] (contact pads 185 as the metal pad) is disposed at the extending portion [130]). The purpose of doing so is to address ultra-high packaging density, high signal integrity, low profile and high manufacturing yield issues, to reduce the minimal height of the metal posts needed for the vertical connection between the dual buildup circuitries at both opposite sides of the electronic component by an amount equal to the depth of the recess, to ensure the placement accuracy of the electronic component to avoid micro-via connection failure in the subsequent formation of the buildup circuitries.
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Figure 19: Modified Figure 19 of Lin
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the dielectric layer of Roessler by extending a portion of the dielectric layer as disclosed by Lin, because Lin teaches to include an extending portion at the first side of the dielectric layer and to dispose at least one first metal pad at the extending portion can address ultra-high packaging density, high signal integrity, low profile and high manufacturing yield issues (Paragraph [0004]), reduces the minimal height of the metal posts needed for the vertical connection between the dual buildup circuitries at both opposite sides of the electronic component by an amount equal to the depth of the recess, ensures the placement accuracy of the electronic component to avoid micro-via connection failure in the subsequent formation of the buildup circuitries (Paragraph [0011]).
Regarding claim 2, Roessler teaches a circuit board,
further including at least one second metal pad [140 located on the second side of the dielectric layer [108] and at peripheries of the plurality of second metal contacts [112] (In the exemplary embodiment, first via 130 includes a first via sidewall 136, a first conductive pad 138 disposed within the first conductive layer 110, and a second conductive pad 140 disposed within the second conductive layer 112; Paragraph [0031] Line 1-5),
wherein the second metal pad [140] is coupled with at least one of the plurality of second metal contacts [112] through a second wiring (conductive traces on second conductive layer is the second wiring as the conductive traces connects the second conductive layer with the second conductive pad) in the dielectric layer [108] (conductive traces in the conductive layer function as the second wiring to connected second metal contacts as the conductive layer and the second conductive pad; First conductive layer 110 and second conductive layer 112 may include any suitable number of conductive traces that enable printed circuit board 102; Paragraph [0019] Line 11-14; Printed circuit boards generally include a plurality of conductive traces formed from a conductive layer to provide an electrical connection between the electronic components; Paragraph [0003] Line 3-6; Claim 5: The printed circuit board of claim 1, wherein at least one of the first conductive layer and the second conductive layer is an outermost conductive layer of the printed circuit board, the outermost conductive layer comprising a plurality of conductive traces, the conductive pad disposed within the outermost conductive layer).
Regarding claim 3, Roessler teaches a circuit board,
wherein the at least one second metal pad [140] is disconnected from the at least one first metal pad [138] (Figure 1: Modified Figure 1 of Roessler above shows that the second metal pad [140] is not directly connected with the first metal pad [138] and therefore second metal pad [140] is disconnected from the at least one first metal pad [138]).
Regarding claim 4, Roessler teaches a circuit board,
wherein the at least one second metal pad [140] is coupled with the
at least one first metal pad [138] (Figure 1: Modified Figure 1 of Roessler above shows that the at least one second metal pad [140] is coupled with the at least one first metal pad [138] by a first plating layer 158, a second plating layer 160, and a third plating layer 162).
Regarding claim 5, Roessler teaches a circuit board,
wherein the peripheries of the plurality of first metal contacts [110, 106] include a plurality of first metal pads [138, 144…] disposed on a same side of the peripheries of the plurality of first metal contacts [110, 106] (Figure 1: Modified Figure 1 of Roessler above shows the peripheries of the plurality of first metal contacts [110, 106] include a plurality of first metal pads [138, 144…] disposed on a same side of the peripheries of the plurality of first metal contacts [110, 106]).
Regarding claim 6, Roessler teaches a circuit board,
wherein the peripheries of the plurality of first metal contacts [106, 122] include a plurality of first metal pads [138, 144] disposed on at least two sides (two sides of 122]) of the peripheries of the plurality of first metal contacts [106, 122, 110] respectively (Figure 1: Modified Figure 1 of Roessler above shows the peripheries of the plurality of first metal contacts [106, 110, 122] include a plurality of first metal pads [138, 144] disposed on at least two sides of the peripheries of the plurality of first metal contacts respectively).
Regarding claim 7, Roessler teaches a circuit board,
wherein the dielectric layer [108] includes recesses [134] (plurality of vias are the recesses in the dielectric layer) (Each of conductive vias 128 includes an annular via sidewall that extends vertically through insulating member 108; Paragraph [0030] Line 1-3) located on the second side of the dielectric layer [108] and at peripheries of the plurality of second metal contacts [112] (Conductive vias that extend through the entire thickness of a printed circuit board, such as first and third vias 130 and 134 are colloquially referred to as through-hole vias. Conductive vias that extend from an outer conductive layer to an inner conductive layer, such as second via 132; Paragraph [0029] Line 1-5).
Claim(s) 8-20 are rejected under 35 U.S.C. 103 as being unpatentable over Roessler ‘001 A1 in view of Lin ‘559 A1 and further in view of Ying et al. (Hereinafter, “Ying”) in the US Patent Application Publication Number US 20190319385 A1.
Regarding claim 8, Roessler teaches a test system [100] in Figure 1 (printed circuit boards, and more particularly, to printed circuit boards including thick-wall conductive vias and methods of manufacturing the same; Paragraph [0002] Line 2-4), comprising
a host [104] (electronic component 104 as the host) and a circuit board [102] stacked and coupled sequentially (FIG. 1 is a cross-section of an exemplary printed circuit board (PCB) assembly 100 including a printed circuit board 102 and an electronic component 104 coupled to printed circuit board 102; Paragraph [0017] Line 1-4), wherein the circuit board [102] comprises:
a dielectric layer [108] (As shown in FIG. 1, printed circuit board 102 includes a plurality of conductive layers 106 coupled to an insulating member 108; Paragraph [0018] Line 1-3) including at least one conductive via [130/134] (As shown in FIG. 1, printed circuit board 102 also includes a plurality of conductive vias 128 electrically coupling two or more of conductive layers 106 together; Paragraph [0027] Line 1-3; The exemplary embodiment includes three conductive vias, including a first via 130, a second via 132, and a third via 134; Paragraph [0028] Line 1-3) extending through the dielectric layer [108] (First via 130 extends through the entire thickness of printed circuit board 102, and electrically couples first conductive layer 110 to second conductive layer 112; Paragraph [0028] Line 4-7; Conductive vias that extend through the entire thickness of a printed circuit board, such as first and third vias 130 and 134; Paragraph [0029] Line 1-3);
a plurality of first metal contacts [110, 106], (conductive layers 110, 106 on the first side of the dielectric layer 108 as the first metal contacts) disposed on a first side of the dielectric layer [108] (The plurality of conductive layers 106 includes a first conductive layer 110, a second conductive layer 112, a third conductive layer 114, a fourth conductive layer 116, a fifth conductive layer 118, and a sixth conductive layer 120; Paragraph [0018] Line 6-9) and a plurality of second metal contacts [112, 120] disposed on a second side of the dielectric layer [108] (The plurality of conductive layers 106 includes a first conductive layer 110, a second conductive layer 112, a third conductive layer 114, a fourth conductive layer 116, a fifth conductive layer 118, and a sixth conductive layer 120; Paragraph [0018] Line 6-9; For example, first conductive layer 110 and second conductive layer 112 are separated and spaced apart from one another by at least one insulating layer defined by insulating member 108; Paragraph [0024] Line 6-3),
wherein at least one of the plurality of first metal contacts [110] is coupled with the second metal contacts [112] through the at least one conductive via [130] (The exemplary embodiment includes three conductive vias, including a first via 130, a second via 132, and a third via 134. First via 130 extends through the entire thickness of printed circuit board 102, and electrically couples first conductive layer 110 to second conductive layer 112. First via 130 is also electrically coupled to third conductive layer 114 and fifth conductive layer 118, thereby electrically coupling first, second, third, and fifth conductive layers 110, 112, 114, and 116 together…... Third via 134 extends through the entire thickness of printed circuit board 102, and electrically couples first conductive layer 110 to second conductive layer 112. Third via 134 is also electrically coupled to third, fourth, and sixth conductive layers 114, 116, and 120, thereby electrically coupling first, second, third, fourth and sixth conductive layers 110, 112, 114, 116, and 120 together; Paragraph [0028] Line 1-21; Figure 1: Modified Figure 1 of Roessler above shows that at least one of the plurality of first metal contacts [110] is coupled with the second metal contacts [112] through the at least one conductive via [130]); and
at least one first metal pad [138] located on the first side of the dielectric layer [108] and at peripheries of the plurality of first metal contacts [110] (at least one conductive pad disposed within one of the outermost conductive layers (i.e., first conductive layer 110 or second conductive layer 112) of printed circuit board 102 and configured to be electrically coupled to an electronic component (e.g., by soldering); Paragraph [0030] Line 3-5; In the exemplary embodiment, first via 130 includes a first via sidewall 136, a first conductive pad 138 disposed within the first conductive layer 110, and a second conductive pad 140 disposed within the second conductive layer 112; Paragraph [0031] Line 1-5),
wherein the first metal pad [138] is coupled with at least one of the plurality of first metal contacts [110] through a first wiring (conductive traces on first conductive layer is the first wiring as the conductive traces connects the first conductive layer with the first conductive pad) in the dielectric layer [108] (conductive traces in the conductive layer function as the first wiring to connected first metal contacts as the first conductive layer and the first conductive pad; First conductive layer 110 and second conductive layer 112 may include any suitable number of conductive traces that enable printed circuit board 102; Paragraph [0019] Line 11-14; Printed circuit boards generally include a plurality of conductive traces formed from a conductive layer to provide an electrical connection between the electronic components; Paragraph [0003] Line 3-6; Claim 5: The printed circuit board of claim 1, wherein at least one of the first conductive layer and the second conductive layer is an outermost conductive layer of the printed circuit board, the outermost conductive layer comprising a plurality of conductive traces, the conductive pad disposed within the outermost conductive layer);
wherein the circuit board [102] is coupled with the host [104] through the plurality of second metal contacts [112] (Figure 1: Modified Figure 1 of Roessler above shows that the printed circuit board, first metal contact and the second metal contact are connected with the host 104 through conductive traces 122 and conductive leads 124).
Roessler fails to teach wherein the first side of the dielectric layer includes an extending portion extending beyond the plurality of first metal contacts, and the at least one first metal pad is disposed at the extending portion and the plurality of first metal contacts are configured to be coupled with a memory system to be tested.
Lin teaches methods of making a wiring board, more particularly, to a method of making a stackable wiring board having an electronic component confined in a recess of a dielectric base and the component-in-recess is surrounded by an array of metal posts or plated through holes (Paragraph [0002] Line 1-6),
wherein the first side of the dielectric layer [13] in Figure 19 includes an extending portion [130] (recess 130 as the extending portion of the dielectric base 13) extending beyond the plurality of first metal contacts [113] (metal posts 113 as the metal contacts), and the at least one first metal pad [185] (contact pads 185 as the metal pad) is disposed at the extending portion [130] (FIG. 19 is a cross-sectional view of the structure with an electronic component 18 placed in the recess 130 of the dielectric base 13. The electronic component 18 is inserted into the recess 130 and attached to the floor 136 of the recess 130 by an adhesive 16. In this embodiment, the electronic component 18 is illustrated as a bare chip and has contact pads 185 at its first surface 182. The first surface 182 of the electronic component 18 faces the dielectric base 13 and contacts the adhesive 16, whereas the second surface 184 of the electronic component 18 is substantially coplanar with the second surface 106 of the metal posts 113. The sidewalls 138 of the recess 130 are laterally aligned with and in close proximity to peripheral edges of the electronic component 18 and confine the dislocation of the electronic component 18 laterally; Paragraph [091] Line 1-15; Figure 19: Modified Figure 19 of Lin above shows the first side of the dielectric layer [13] in Figure 19 includes an extending portion [130] (recess 130 as the extending portion of the dielectric base 13) extending beyond the plurality of first metal contacts [113] (metal posts 113 as the metal contacts), and the at least one first metal pad [185] (contact pads 185 as the metal pad) is disposed at the extending portion [130]). The purpose of doing so is to address ultra-high packaging density, high signal integrity, low profile and high manufacturing yield issues, to reduce the minimal height of the metal posts needed for the vertical connection between the dual buildup circuitries at both opposite sides of the electronic component by an amount equal to the depth of the recess, to ensure the placement accuracy of the electronic component to avoid micro-via connection failure in the subsequent formation of the buildup circuitries.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the dielectric layer of Roessler by extending a portion of the dielectric layer as disclosed by Lin, because Lin teaches to include an extending portion at the first side of the dielectric layer and to dispose at least one first metal pad at the extending portion can address ultra-high packaging density, high signal integrity, low profile and high manufacturing yield issues (Paragraph [0004]), reduces the minimal height of the metal posts needed for the vertical connection between the dual buildup circuitries at both opposite sides of the electronic component by an amount equal to the depth of the recess, ensures the placement accuracy of the electronic component to avoid micro-via connection failure in the subsequent formation of the buildup circuitries (Paragraph [0011]).
The combination of Roessler and Lin fails to teach that the plurality of first metal contacts are configured to be coupled with a memory system to be tested.
Ying teaches a printed circuit board (PCB) that includes a conductive layer extending from the printed circuit board to act as a heat sink for circuit components electrically and mechanically attached to the PCB. The conductive layer can be a copper ground layer of a multi-layered PCB. The PCB can include one or more circuit components, such as dynamic random access memory elements (Abstract),
wherein the plurality of first metal contacts are configured to be coupled with a memory system to be tested (Example 18 is a dual inline memory module (DIMM) that includes a multi-layered printed circuit board (MLPCB), the MLPCB comprising a conductive layer, the conductive layer extending from the printed circuit board and defining an air gap between the conductive layer and the exposed side of at least one of the first printed circuit board layer or the second printed circuit board layer; and at least one dynamic random access memory (DRAM) element electrically and mechanically coupled to the MLPCB, the at least one DRAM electrically coupled to the conductive layer; Paragraph [0056] Line 1-12). The purpose of doing so is to help cool the DIMM (memory), to allow for the DIMM compatibly with standard DIMM connector on the board, to provide for increasing the number of DIMMs on a package, to provide the advantage of no thermal interference material is required, which helps to reduce cost and overall form factor of the DIMM package.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Roessler and Lin in view of Ying, because Roessler teaches to couple the plurality of first metal contacts with a memory system to be tested helps cool the DIMM, allows for the DIMM compatibly with standard DIMM connector on the board, provides for increasing the number of DIMMs on a package, provides the advantage of no thermal interference material is required, which helps to reduce cost and overall form factor of the DIMM package (Paragraph [0015]).
Regarding claim 9, Roessler teaches a test system,
further including at least one second metal pad [140 located on the second side of the dielectric layer [108] and at peripheries of the plurality of second metal contacts [112] (In the exemplary embodiment, first via 130 includes a first via sidewall 136, a first conductive pad 138 disposed within the first conductive layer 110, and a second conductive pad 140 disposed within the second conductive layer 112; Paragraph [0031] Line 1-5),
wherein the second metal pad [140] is coupled with at least one of the plurality of second metal contacts [112] through a second wiring (conductive traces on second conductive layer is the second wiring as the conductive traces connects the second conductive layer with the second conductive pad) in the dielectric layer [108] (conductive traces in the conductive layer function as the second wiring to connected second metal contacts as the conductive layer and the second conductive pad; First conductive layer 110 and second conductive layer 112 may include any suitable number of conductive traces that enable printed circuit board 102; Paragraph [0019] Line 11-14; Printed circuit boards generally include a plurality of conductive traces formed from a conductive layer to provide an electrical connection between the electronic components; Paragraph [0003] Line 3-6; Claim 5: The printed circuit board of claim 1, wherein at least one of the first conductive layer and the second conductive layer is an outermost conductive layer of the printed circuit board, the outermost conductive layer comprising a plurality of conductive traces, the conductive pad disposed within the outermost conductive layer).
Regarding claim 10, Roessler teaches a test system,
wherein the at least one second metal pad [140] is disconnected from the at least one first metal pad [138] (Figure 1: Modified Figure 1 of Roessler above shows that the second metal pad [140] is not directly connected with the first metal pad [138] and therefore second metal pad [140] is disconnected from the at least one first metal pad [138]).
Regarding claim 11, Roessler teaches a test system,
wherein the at least one second metal pad [140] is coupled with the at least one first metal pad [138] (Figure 1: Modified Figure 1 of Roessler above shows that the at least one second metal pad [140] is coupled with the at least one first metal pad [138] by a first plating layer 158, a second plating layer 160, and a third plating layer 162).
Regarding claim 12, Roessler teaches a test system,
wherein the peripheries of the plurality of first metal contacts [110, 106] include a plurality of first metal pads [138, 144…] disposed on a same side of the peripheries of the plurality of first metal contacts [110, 106] (Figure 1: Modified Figure 1 of Roessler above shows the peripheries of the plurality of first metal contacts [110, 106] include a plurality of first metal pads [138, 144…] disposed on a same side of the peripheries of the plurality of first metal contacts [110, 106]).
Regarding claim 13, Roessler teaches a test system,
wherein the peripheries of the plurality of first metal contacts [106, 122] include a plurality of first metal pads [138, 144] disposed on at least two sides (two sides of 122]) of the peripheries of the plurality of first metal contacts [106, 122, 110] respectively (Figure 1: Modified Figure 1 of Roessler above shows the peripheries of the plurality of first metal contacts [106, 110, 122] include a plurality of first metal pads [138, 144] disposed on at least two sides of the peripheries of the plurality of first metal contacts respectively).
Regarding claim 14, the combination of Roessler and Lin fails to teach a test system, wherein the dielectric layer includes an extending portion extending towards any direction of a plane where the memory system is located, and the first metal pad is disposed at the extending portion. that the plurality of first metal contacts are configured to be coupled with a memory system to be tested.
Ying teaches a printed circuit board (PCB) that includes a conductive layer extending from the printed circuit board to act as a heat sink for circuit components electrically and mechanically attached to the PCB. The conductive layer can be a copper ground layer of a multi-layered PCB. The PCB can include one or more circuit components, such as dynamic random access memory elements (Abstract),
wherein the dielectric layer [102] (PCB as the dielectric layer as Roessler already discloses dielectric layer in the PCB) includes an extending portion (Figure 1) extending towards any direction of a plane where the memory system [104] is located, and the first metal pad is disposed at the extending portion. (Example 18 is a dual inline memory module (DIMM) that includes a multi-layered printed circuit board (MLPCB), the MLPCB comprising a conductive layer, the conductive layer extending from the printed circuit board and defining an air gap between the conductive layer and the exposed side of at least one of the first printed circuit board layer or the second printed circuit board layer; and at least one dynamic random access memory (DRAM) element electrically and mechanically coupled to the MLPCB, the at least one DRAM electrically coupled to the conductive layer; Paragraph [0056] Line 1-12; FIG. 1 is an example dual inline memory module (DIMM) 100 that includes a full DIMM heat spreader (FDHS) 106. The DIMM 100 includes a raw card 102 that can be a printed circuit board or other type of board that can hold a DRAM 104 and other integrated circuit elements; Paragraph [0013] Line 1-5). The purpose of doing so is to help cool the DIMM, to allow for the DIMM compatibly with standard DIMM connector on the board, to provide for increasing the number of DIMMs on a package, to provide the advantage of no thermal interference material is required, which helps to reduce cost and overall form factor of the DIMM package.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Roessler and Lin in view of Ying, because Roessler teaches to include an extending portion of the dielectric layer to extend towards any direction of a plane where the memory system is located helps cool the DIMM, allows for the DIMM compatibly with standard DIMM connector on the board, provides for increasing the number of DIMMs on a package, provides the advantage of no thermal interference material is required, which helps to reduce cost and overall form factor of the DIMM package (Paragraph [0015]).
Regarding claim 15, Roessler teaches a test system,
wherein the dielectric layer [108] includes recesses [134] (plurality of vias are the recesses in the dielectric layer) (Each of conductive vias 128 includes an annular via sidewall that extends vertically through insulating member 108; Paragraph [0030] Line 1-3) located on the second side of the dielectric layer [108] and at peripheries of the plurality of second metal contacts [112] (Conductive vias that extend through the entire thickness of a printed circuit board, such as first and third vias 130 and 134 are colloquially referred to as through-hole vias. Conductive vias that extend from an outer conductive layer to an inner conductive layer, such as second via 132; Paragraph [0029] Line 1-5).
Regarding claim 16, Roessler teaches a test system,
further including an intermediate plate [122+124] (conductive traces and conductive leads as the intermediate plate) disposed between the host [104] and the circuit board [102] (Electronic component 104 is mechanically and electrically coupled to printed circuit board 102 by a pair of conductive leads 124. Each of conductive leads 124 is electrically coupled to one of conductive traces 122 in first conductive layer 110 (e.g., by soldering). The pair of conductive leads 124 has a center-to-center spacing 126, also referred to as “pitch”. Although only one electronic component is shown in FIG. 1, PCB assembly 100 may include more than one electronic component. In some embodiments, electronic component 104 is a power electronic component, such as an inductor, a transformer, or a power MOSFET; Paragraph [0025] Line 1-11),
wherein the circuit board [102], the intermediate plate [122+124]and the host [104] are stacked and coupled sequentially (Figure 1: Modified Figure 1 of Roessler above shows the circuit board [102], the intermediate plate [122+124]and the host [104] are stacked and coupled sequentially).
Regarding claim 17, Roessler in view Ying teaches a test system,
wherein the host is coupled to the memory system to be tested through the circuit board (Roessler teaches that the host is coupled to the printed circuit board and Ying teaches memory is in the printed circuit board and therefore in combination Roessler in view Ying teaches a test system, wherein the host is coupled to the memory system to be tested through the circuit board).
Regarding claim 18, the combination of Roessler and Lin fails to teach a test system, wherein the memory system comprises one of a solid state drive (SSD), an universal flash storage (UFS), and an embedded multimedia card (eMMC).
Ying teaches a printed circuit board (PCB) that includes a conductive layer extending from the printed circuit board to act as a heat sink for circuit components electrically and mechanically attached to the PCB. The conductive layer can be a copper ground layer of a multi-layered PCB. The PCB can include one or more circuit components, such as dynamic random access memory elements (Abstract),
wherein the memory system comprises one of a solid state drive (SSD), an universal flash storage (UFS), and an embedded multimedia card (eMMC) (Computing device 900 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 910 (e.g., DRAM), non-volatile memory 912 (e.g., ROM or flash memory); Paragraph [0032] Line 1-6). The purpose of doing so is to help cool the DIMM, to allow for the DIMM compatibly with standard DIMM connector on the board, to provide for increasing the number of DIMMs on a package, to provide the advantage of no thermal interference material is required, which helps to reduce cost and overall form factor of the DIMM package and to maintain overall form factors and to cool DIMMs onboard.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Roessler and Lin in view of Ying, because Roessler teaches to include an universal flash storage (UFS), and an embedded multimedia card (eMMC), allows for the DIMM compatibly with standard DIMM connector on the board, provides for increasing the number of DIMMs on a package, provides the advantage of no thermal interference material is required, which helps to reduce cost and overall form factor of the DIMM package (Paragraph [0015]), maintains overall form factors and to cool DIMMs onboard (Paragraph [0002]).
Regarding claim 19, the combination of Roessler and Lin fails to teach a test system, wherein a size of the circuit board is greater than or equal to a size of the memory system to be tested.
Ying teaches a printed circuit board (PCB) that includes a conductive layer extending from the printed circuit board to act as a heat sink for circuit components electrically and mechanically attached to the PCB. The conductive layer can be a copper ground layer of a multi-layered PCB. The PCB can include one or more circuit components, such as dynamic random access memory elements (Abstract),
wherein a size of the circuit board is greater than or equal to a size of the memory system to be tested (FIG. 1 is an example dual inline memory module (DIMM) 100 that includes a full DIMM heat spreader (FDHS) 106. The DIMM 100 includes a raw card 102 that can be a printed circuit board or other type of board that can hold a DRAM 104 and other integrated circuit elements; Paragraph [0013] Line 1-5; Therefore, a size of the circuit board is greater than or equal to a size of the memory system to be tested). The purpose of doing so is to accommodate various PCB thicknesses so that the PCB can be electrically connected to an edge connector.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Roessler and Lin in view of Ying, because Roessler teaches to include a size of the circuit board greater than or equal to a size of the memory system to be tested accommodates various PCB thicknesses so that the PCB can be electrically connected to an edge connector (Abstract).
Regarding claim 20, Roessler teaches a test method applied to a test system [100] in Figure 1 (printed circuit boards, and more particularly, to printed circuit boards including thick-wall conductive vias and methods of manufacturing the same; Paragraph [0002] Line 2-4) including a host [104] (electronic component 104 as the host) and a circuit board [102] stacked and coupled sequentially (FIG. 1 is a cross-section of an exemplary printed circuit board (PCB) assembly 100 including a printed circuit board 102 and an electronic component 104 coupled to printed circuit board 102; Paragraph [0017] Line 1-4), wherein the circuit board [102] comprises:
a dielectric layer [108] (As shown in FIG. 1, printed circuit board 102 includes a plurality of conductive layers 106 coupled to an insulating member 108; Paragraph [0018] Line 1-3) including at least one conductive via [130/134] (As shown in FIG. 1, printed circuit board 102 also includes a plurality of conductive vias 128 electrically coupling two or more of conductive layers 106 together; Paragraph [0027] Line 1-3; The exemplary embodiment includes three conductive vias, including a first via 130, a second via 132, and a third via 134; Paragraph [0028] Line 1-3) extending through the dielectric layer [108] (First via 130 extends through the entire thickness of printed circuit board 102, and electrically couples first conductive layer 110 to second conductive layer 112; Paragraph [0028] Line 4-7; Conductive vias that extend through the entire thickness of a printed circuit board, such as first and third vias 130 and 134; Paragraph [0029] Line 1-3);
a plurality of first metal contacts [110, 106], (conductive layers 110, 106 on the first side of the dielectric layer 108 as the first metal contacts) disposed on a first side of the dielectric layer [108] (The plurality of conductive layers 106 includes a first conductive layer 110, a second conductive layer 112, a third conductive layer 114, a fourth conductive layer 116, a fifth conductive layer 118, and a sixth conductive layer 120; Paragraph [0018] Line 6-9) and a plurality of second metal contacts [112, 120] disposed on a second side of the dielectric layer [108] (The plurality of conductive layers 106 includes a first conductive layer 110, a second conductive layer 112, a third conductive layer 114, a fourth conductive layer 116, a fifth conductive layer 118, and a sixth conductive layer 120; Paragraph [0018] Line 6-9; For example, first conductive layer 110 and second conductive layer 112 are separated and spaced apart from one another by at least one insulating layer defined by insulating member 108; Paragraph [0024] Line 6-3),
wherein at least one of the plurality of first metal contacts [110] is coupled with the second metal contacts [112] through the at least one conductive via [130] (The exemplary embodiment includes three conductive vias, including a first via 130, a second via 132, and a third via 134. First via 130 extends through the entire thickness of printed circuit board 102, and electrically couples first conductive layer 110 to second conductive layer 112. First via 130 is also electrically coupled to third conductive layer 114 and fifth conductive layer 118, thereby electrically coupling first, second, third, and fifth conductive layers 110, 112, 114, and 116 together…... Third via 134 extends through the entire thickness of printed circuit board 102, and electrically couples first conductive layer 110 to second conductive layer 112. Third via 134 is also electrically coupled to third, fourth, and sixth conductive layers 114, 116, and 120, thereby electrically coupling first, second, third, fourth and sixth conductive layers 110, 112, 114, 116, and 120 together; Paragraph [0028] Line 1-21; Figure 1: Modified Figure 1 of Roessler above shows that at least one of the plurality of first metal contacts [110] is coupled with the second metal contacts [112] through the at least one conductive via [130]); and
at least one first metal pad [138] located on the first side of the dielectric layer [108] and at peripheries of the plurality of first metal contacts [110] (at least one conductive pad disposed within one of the outermost conductive layers (i.e., first conductive layer 110 or second conductive layer 112) of printed circuit board 102 and configured to be electrically coupled to an electronic component (e.g., by soldering); Paragraph [0030] Line 3-5; In the exemplary embodiment, first via 130 includes a first via sidewall 136, a first conductive pad 138 disposed within the first conductive layer 110, and a second conductive pad 140 disposed within the second conductive layer 112; Paragraph [0031] Line 1-5),
wherein the first metal pad [138] is coupled with at least one of the plurality of first metal contacts [110] through a first wiring (conductive traces on first conductive layer is the first wiring as the conductive traces connects the first conductive layer with the first conductive pad) in the dielectric layer [108] (conductive traces in the conductive layer function as the first wiring to connected first metal contacts as the first conductive layer and the first conductive pad; First conductive layer 110 and second conductive layer 112 may include any suitable number of conductive traces that enable printed circuit board 102; Paragraph [0019] Line 11-14; Printed circuit boards generally include a plurality of conductive traces formed from a conductive layer to provide an electrical connection between the electronic components; Paragraph [0003] Line 3-6; Claim 5: The printed circuit board of claim 1, wherein at least one of the first conductive layer and the second conductive layer is an outermost conductive layer of the printed circuit board, the outermost conductive layer comprising a plurality of conductive traces, the conductive pad disposed within the outermost conductive layer);
wherein the circuit board [102] is coupled with the host [104] through the plurality of second metal contacts [112] (Figure 1 shows that the printed circuit board, first metal contact and the second metal contact are connected with the host 104 through conductive traces 122 and conductive leads 124).
Roessler fails to teach wherein the first side of the dielectric layer includes an extending portion extending beyond the plurality of first metal contacts, and the at least one first metal pad is disposed at the extending portion and the plurality of first metal contacts are configured to be coupled with a memory system to be tested and wherein the test method includes: acquiring an operation state signal of the memory system to be tested from a metal pad of the circuit board, wherein the operation state signal is configured to indicate operation state information of the memory system to be tested; and obtaining the operation state information of the memory system to be tested, according to the operation state signal.
Lin teaches methods of making a wiring board, more particularly, to a method of making a stackable wiring board having an electronic component confined in a recess of a dielectric base and the component-in-recess is surrounded by an array of metal posts or plated through holes (Paragraph [0002] Line 1-6),
wherein the first side of the dielectric layer [13] in Figure 19 includes an extending portion [130] (recess 130 as the extending portion of the dielectric base 13) extending beyond the plurality of first metal contacts [113] (metal posts 113 as the metal contacts), and the at least one first metal pad [185] (contact pads 185 as the metal pad) is disposed at the extending portion [130] (FIG. 19 is a cross-sectional view of the structure with an electronic component 18 placed in the recess 130 of the dielectric base 13. The electronic component 18 is inserted into the recess 130 and attached to the floor 136 of the recess 130 by an adhesive 16. In this embodiment, the electronic component 18 is illustrated as a bare chip and has contact pads 185 at its first surface 182. The first surface 182 of the electronic component 18 faces the dielectric base 13 and contacts the adhesive 16, whereas the second surface 184 of the electronic component 18 is substantially coplanar with the second surface 106 of the metal posts 113. The sidewalls 138 of the recess 130 are laterally aligned with and in close proximity to peripheral edges of the electronic component 18 and confine the dislocation of the electronic component 18 laterally; Paragraph [091] Line 1-15; Figure 19: Modified Figure 19 of Lin above shows the first side of the dielectric layer [13] in Figure 19 includes an extending portion [130] (recess 130 as the extending portion of the dielectric base 13) extending beyond the plurality of first metal contacts [113] (metal posts 113 as the metal contacts), and the at least one first metal pad [185] (contact pads 185 as the metal pad) is disposed at the extending portion [130]). The purpose of doing so is to address ultra-high packaging density, high signal integrity, low profile and high manufacturing yield issues, to reduce the minimal height of the metal posts needed for the vertical connection between the dual buildup circuitries at both opposite sides of the electronic component by an amount equal to the depth of the recess, to ensure the placement accuracy of the electronic component to avoid micro-via connection failure in the subsequent formation of the buildup circuitries.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify the dielectric layer of Roessler by extending a portion of the dielectric layer as disclosed by Lin, because Lin teaches to include an extending portion at the first side of the dielectric layer and to dispose at least one first metal pad at the extending portion can address ultra-high packaging density, high signal integrity, low profile and high manufacturing yield issues (Paragraph [0004]), reduces the minimal height of the metal posts needed for the vertical connection between the dual buildup circuitries at both opposite sides of the electronic component by an amount equal to the depth of the recess, ensures the placement accuracy of the electronic component to avoid micro-via connection failure in the subsequent formation of the buildup circuitries (Paragraph [0011]).
The combination of Roessler and Lin fails to teach that the plurality of first metal contacts are configured to be coupled with a memory system to be tested and wherein the test method includes: acquiring an operation state signal of the memory system to be tested from a metal pad of the circuit board, wherein the operation state signal is configured to indicate operation state information of the memory system to be tested; and obtaining the operation state information of the memory system to be tested, according to the operation state signal.
Ying teaches a printed circuit board (PCB) that includes a conductive layer extending from the printed circuit board to act as a heat sink for circuit components electrically and mechanically attached to the PCB. The conductive layer can be a copper ground layer of a multi-layered PCB. The PCB can include one or more circuit components, such as dynamic random access memory elements (Abstract),
wherein the plurality of first metal contacts are configured to be coupled with a memory system to be tested (Example 18 is a dual inline memory module (DIMM) that includes a multi-layered printed circuit board (MLPCB), the MLPCB comprising a conductive layer, the conductive layer extending from the printed circuit board and defining an air gap between the conductive layer and the exposed side of at least one of the first printed circuit board layer or the second printed circuit board layer; and at least one dynamic random access memory (DRAM) element electrically and mechanically coupled to the MLPCB, the at least one DRAM electrically coupled to the conductive layer; Paragraph [0056] Line 1-12); and
wherein the test method (FIG. 9 illustrates a computing device 900 in accordance with one embodiment of the disclosure; Paragraph [0031] Line 1-2) includes:
acquiring an operation state signal of the memory system to be tested from a metal pad of the circuit board, wherein the operation state signal is configured to indicate operation state information of the memory system to be tested (The communications logic unit 908 enables wireless communications for the transfer of data to and from the computing device 900. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium; Paragraph [0033] Line 1-8); and
obtaining the operation state information of the memory system to be tested, according to the operation state signal (One example here is to compare 5 scenarios: DIMM without a heatsink, DIMM with 1 mm FDHS, DIMM with 0.5 mm FDHS, DIMM with 0.15 mm Ground Heatsink (GND HS) and DIMM with 0.3 mm GND Heatsink. The table below shows thermal and DIMM thickness result comparison between these 5 scenarios. Given ambient as 40 C, DIMM power as 14.6 w (DRAM 0.35 w*36 and Buffer 2.0 w). The thermal resistance of hottest DRAM and Buffer at each velocity can be compared. The table also shows the comparison of support power for each scenario; Paragraph [0025] Line 1-10; These are the operation state information of the DIMM as the memory system). The purpose of doing so is to help cool the DIMM, to allow for the DIMM compatibly with standard DIMM connector on the board, to provide for increasing the number of DIMMs on a package, to provide the advantage of no thermal interference material is required, which helps to reduce cost and overall form factor of the DIMM package and to maintain overall form factors and to cool DIMMs onboard.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Roessler and Lin in view of Ying, because Roessler teaches to include a memory system and to obtain the operation state information of the memory system to be tested allows for the DIMM compatibly with standard DIMM connector on the board, provides for increasing the number of DIMMs on a package, provides the advantage of no thermal interference material is required, which helps to reduce cost and overall form factor of the DIMM package (Paragraph [0015]), maintains overall form factors and to cool DIMMs onboard (Paragraph [0002]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Karnezos (US 20040195667 A1) discloses, “Semiconductor Multipackage Module Including Processor And Memory Package Assemblies-[0002] This invention relates to semiconductor packaging. In particular this invention relates to semiconductor packages that include processor and memory chips in the package. [0055] In the illustrative embodiment of FIG. 2, a module substrate 216, also 236, has a "lower" surface onto which solder balls 218 are attached, for connection by solder reflow to, for example, a motherboard (not shown). A processor 220 is mounted onto a processor mounting portion of the lower surface of the module 216. As shown in this example, the processor 220 has a flip-chip configuration; it includes a die 224 electrically connected by way of balls or bumps 228 to interconnect sites (not shown) in the lower surface of the module substrate, and affixed to the surface using an adhesive underfill material 225. A plurality of memory packages 230, 230' (there may typically be four memory packages; two are shown in the view of FIG. 2) are mounted on the upper surface of the module substrate 236. In the embodiment illustrated in FIG. 2 the memory packages are inverted saw-singulated land grid array (LGA) packages. Referring particularly to LGA package 230, each memory LGA package includes a die 234 affixed using an adhesive to a memory package substrate 235. The package substrate is a two-metal layer laminate, having patterned electrically conductive traces on the upper and lower surfaces of a dielectric layer; selected upper and lower traces are connected by way of vias (not shown) through the dielectric layer. The downward-facing active surface of the die is electrically connected to traces on the die attach (lower) surface of the package substrate 235 by wire bonds 232. The active surface of the die and the wire bonds are protected by an encapsulant 237-However Karnezos does not disclose wherein the first side of the dielectric layer includes an extending portion extending beyond the plurality of first metal contacts, and the at least one first metal pad is disposed at the extending portion.”
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NASIMA MONSUR whose telephone number is (571)272-8497. The examiner can normally be reached 10:00 am-6:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eman Alkafawi can be reached at (571) 272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NASIMA MONSUR/Primary Examiner, Art Unit 2858
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