DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 1 of U.S. Patent No. USP 12,107,591. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,107,591 discloses similar limitations and function as claimed in the instant application, such as: a plurality of ordered mirroring MOS transistors having respective gate terminals connected to a current reference node and respective drain terminals alternatively couplable either to a first current node or to a second current node as a function of a plurality of respective ordered control signals, wherein a first mirroring MOS transistor in the plurality of ordered mirroring MOS transistors has a source terminal directly connected to a reference voltage node; and a plurality of current control MOS transistors having respective gate terminals connected to the current reference node, wherein each current control MOS transistor is arranged between source terminals of two consecutive mirroring MOS transistors in the plurality of ordered mirroring MOS transistors, wherein mirroring MOS transistors of the plurality of ordered mirroring MOS transistors whose source terminals are not directly connected to the reference voltage node have respective bulk terminals configured to receive one or more compensation signals, the one or more compensation signals having respective values that decrease with increasing temperature.
Claim 2 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 2 of U.S. Patent No. USP 12,107,591. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,107,591 discloses similar limitations and function as claimed in the instant application, such as: wherein the one or more compensation signals are linearly dependent on temperature.
Claim 3 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 3 of U.S. Patent No. USP 12,107,591. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,107,591 discloses similar limitations and function as claimed in the instant application, such as: a compensation circuit configured to produce the one or more compensation signals, the compensation circuit comprising: an inversely proportional-to-absolute-temperature current generator arrangement configured to produce a compensation voltage signal that decreases linearly as a function of increasing temperature; a voltage divider circuit; and a buffer stage configured to supply the compensation voltage signal to the voltage divider circuit, wherein the one or more compensation signals are produced at one or more intermediate nodes of the voltage divider circuit.
Claim 4 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 5 of U.S. Patent No. USP 12,107,591. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,107,591 discloses similar limitations and function as claimed in the instant application, such as: wherein the buffer stage comprises an amplifier circuit having an output terminal coupled to the voltage divider circuit, a non-inverting input terminal configured to receive the compensation voltage signal, and an inverting input terminal coupled to its output terminal.
Claim 5 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 6 of U.S. Patent No. USP 12,107,591. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,107,591 discloses similar limitations and function as claimed in the instant application, such as: wherein the mirroring MOS transistors of the plurality of ordered mirroring MOS transistors whose source terminals are not directly connected to the reference voltage node include triple-well n-channel MOS transistors.
Claim 6 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 7 of U.S. Patent No. USP 12,107,591. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,107,591 discloses similar limitations and function as claimed in the instant application, such as: wherein a source terminal of a last mirroring MOS transistor in the plurality of ordered mirroring MOS transistors is directly connected to a source terminal of a second-to-last mirroring MOS transistor in the plurality of ordered mirroring MOS transistors.
Claim 7 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 8 of U.S. Patent No. USP 12,107,591. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,107,591 discloses similar limitations and function as claimed in the instant application, such as: wherein the last mirroring MOS transistor and the second-to-last mirroring MOS transistor have respective bulk terminals configured to receive a same compensation signal.
Claim 8 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 9 of U.S. Patent No. USP 12,107,591. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,107,591 discloses similar limitations and function as claimed in the instant application, such as: wherein a drain terminal of a last mirroring MOS transistor in the plurality of ordered mirroring MOS transistors and a drain terminal of a second-to-last mirroring MOS transistor in the plurality of ordered mirroring MOS transistors are steadily coupled to the second current node.
Claim 9 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 10 of U.S. Patent No. USP 12,107,591. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,107,591 discloses similar limitations and function as claimed in the instant application, such as: wherein the drain terminals of the plurality of ordered mirroring MOS transistors are alternatively couplable to the first current node or to the second current node via respective switches activatable as a function of the respective ordered control signals.
Claim 10 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 12 of U.S. Patent No. USP 12,107,591. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,107,591 discloses similar limitations and function as claimed in the instant application, such as: a first output diode-connected MOS transistor having a drain terminal connected to the first current node and source terminal connected to a supply voltage node, and a second output diode-connected MOS transistor having a drain terminal connected to the second current node and a source terminal connected to the supply voltage node.
Claim 12 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 13 of U.S. Patent No. USP 12,107,591. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,107,591 discloses similar limitations and function as claimed in the instant application, such as: a W-2W current mirror comprising a first plurality of MOS transistors and a second plurality of MOS transistors, wherein ones of the second plurality of MOS transistors are coupled between adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.
Claim 13 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 14 of U.S. Patent No. USP 12,107,591. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,107,591 discloses similar limitations and function as claimed in the instant application, such as: an output coupling network coupled to output nodes of the first plurality of MOS transistors, the output coupling network configured to selectively couple the output nodes of the first plurality of MOS transistors to an output node of the DAC in accordance with a digital DAC input word.
Claim 14 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 15 of U.S. Patent No. USP 12,107,591. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,107,591 discloses similar limitations and function as claimed in the instant application, such as: wherein the bulk bias generator comprises: a voltage generator configured to provide an inversely proportional to temperature reference voltage; and a resistor ladder coupled to an output of the voltage generator, the resistor ladder comprising a plurality of taps, wherein output nodes of the plurality of output nodes of the bulk bias generator are coupled to corresponding taps of the plurality of taps.
Claim 15 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 16 of U.S. Patent No. USP 12,107,591. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,107,591 discloses similar limitations and function as claimed in the instant application, such as: wherein the voltage generator comprises: an input MOS transistor having a gate coupled to a reference voltage generator; a diode connected MOS transistor having; a current mirror having an input coupled to an output node of the input MOS transistor and an output node coupled to a gate and drain of the diode connected MOS transistor; and a voltage buffer coupled between the gate and drain of the diode connected MOS transistor and the resistor ladder.
Claim 16 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 17 of U.S. Patent No. USP 12,107,591. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,107,591 discloses similar limitations and function as claimed in the instant application, such as: wherein voltage levels of the voltages provided by the bulk bias generator and a temperature coefficient of the voltages provided by the bulk bias generator are selected to increase a linear behavior of the W-2W current mirror.
Claim 18 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 18 of U.S. Patent No. USP 12,107,591. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,107,591 discloses similar limitations and function as claimed in the instant application, such as: a W-2W current mirror comprising a first plurality of MOS transistors and a second plurality of MOS transistors, wherein ones of the second plurality of MOS transistors are coupled between adjacent ones of the first plurality of MOS transistors, the method comprising: biasing bulk nodes of the first plurality of MOS transistors with a corresponding plurality of inversely proportional to temperature bias voltages.
Claim 19 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 19 of U.S. Patent No. USP 12,107,591. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,107,591 discloses similar limitations and function as claimed in the instant application, such as: receiving a DAC input word; and selecting output branches of the W-2W current mirror in accordance with the DAC input word.
Claim 20 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 20 of U.S. Patent No. USP 12,107,591. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,107,591 discloses similar limitations and function as claimed in the instant application, such as: generating a first bias voltage that is inversely proportional to temperature; and applying the first bias voltage to a resister ladder.
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein each of the plurality of ordered mirroring MOS transistors has a first width-to-length ratio, and each of the plurality of current control MOS transistors has a second width-to-length ratio that is twice the first width-to-length ratio.
Claim 17 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein each of the first plurality of MOS transistors has a first width-to-length ratio, and each of the second plurality of MOS transistors has a second width-to-length ratio that is twice the first width-to-length ratio.
Cited References
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cited references are related to instant application subject matters.
Conclusion
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/LAM T MAI/Primary Examiner, Art Unit 2845