DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular paragraphs or columns and lines in the references as applied to the claims below for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by this Examiner.
Response to Amendment
This final Office action is in response to the amendment filed 14 July 2026. Claims 1-20 are pending. All objections and rejections not repeated below are withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-11 and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jibaja et al. [Patent No.: US 10,452,444] (hereinafter “Jibaja”).
Independent Claims:
Per independent claim 1, Jibaja teaches:
A memory device (see Fig. 2B, 2C for storage node 150; also see Fig. 3B and 4-6 for storage system 406, which corresponds to storage node 150), comprising:
a memory array (see Fig. 4-6 for storage devices 430-434; see Fig. 2C-2D for Flash Memory array 206, or Flash dies 222, depending on the interpretation of claimed one or more latches);
one or more processing resources (see Fig. 4-6, processing resources 416-420; also see Fig. 2A and 2C for CPU 156; also see col. 37, lines 62-64 and Figs 4-6, the processing resource executing the data producer 402 on the storage system 406 is also one of the claimed processing resources); and
control circuitry coupled to the memory array and the one or more processing resources (see Fig. 2A and 2C-2D for controller 212/246 and PLD 208; also see Fig. 4-6 for processing resources 416-420 comprising Analytics Application 422), the control circuitry configured to cause the memory device to:
receive a command at the memory device (see col. 20, lines 49-50 for storage devices in storage node 150 receiving command to read, write or erase data; also see col. 38, lines 25-29, there must be a command/instruction received at the storage system that results in the execution of the transformation of unstructured data into structured data);
process, by the one or more processing resources, raw data transferred from the memory array in response to receiving the command (see col. 38, lines 25-29, transform unstructured data into structured data; also see col. 32, lines 10-13 for ingesting raw data and transforming the raw data to a format convenient for training. Also see Fig. 4, the unstructured Dataset 410 is first stored in step 410 as Dataset Slices 424-428 in Storage Devices 430-434. Step 412 then allocates processing resources to Analytics Application 422, which transforms unstructured/raw data stored in step 410 into structured data, see col. 38, lines 25-29); and
store a result of the processing (the structured data that is the result of the transformation) in one or more latches coupled with the one or more processing resources (see Fig. 2C-2G, NVRAM 204, also see Fig. 2A, Mem 154 and Fig. 1B, RAM 111, which are all different embodiments of higher speed buffers/latches connected to one or more processing device (storage devices 430-434 in Figs. 4-6 are SSD/HDD devices, see col. 37, lines 35-37, while storage system 406 in Fig. 4-6 is equivalent to the storage systems shown in Figs. 1A-1D, 2A-2G and 3A-3B, see col. 37, lines 19-21. As such NVRAM 204 are latches/buffers to SSD/HDD devices 430-434 in Fig. 7; also see col. 20, lines 5-21, “the NVRAM 204 is implemented … as high speed volatile memory, such as … (DRAM) 216” and transfer of DRAM content to flash 206, see col. 21, lines 20-35 and col. 22, lines 36-38 for “NVRAM 204 is a … block of .. DRAM 216” and “store every update in their NVRAM 204 partitions … until the update has been written to flash 206”). Also see Fig. 2C and paragraph 20, lines 25-37, DRAM 216/NVRAM 204 is coupled to the processing resource CPU 156 through I/O port 210, and coupled to the flash dies 222 through flash I/O port 220 and DMA 214. In another interpretation of the prior art, Register 226 in Fig. 2C may be viewed as the claimed one or more latches, because all read/writes to the flash die 222 must go through Register 226, and Register 226 is connected to the processing resource 156 through Flash I/O 220 and I/O 210, also see paragraph 20, lines 25-37. Note that under this interpretation, the claimed memory array is mapped to Jibaja’s Flash dies 222), wherein the one or more latches are coupled to data lines of the memory array (see Fig. 2C, the lines between PLD 208 and Flash Memory Array 206 are connected to the data lines of Flash Memory Array 206; or, under the interpretation that the claimed one or more latches is Register 226, Flash dies 222’s data lines must be connected to Register 226 as all data reads and writes to the Flash dies 222 must go through Register 226) and configured to temporarily store charges representing data (see col. 3, line 54 to col. 4, line 7, col. 6, lines 47-50, col. 8, line 55 to col. 9, line 6, col. 9, lines 31-35, col. 13, lines 8-13, col. 20, lines 36-37 and col. 21, lines 20-35; NVRAM 204 only maintains the state of the RAM after main power loss long enough to write the RAM data to persistent SSD/HDD, as such it only temporarily stores data; note that electronic data in Jibaja must be stored as charges representing data) from the memory array during one or more operations (see col. 21, lines 20-35; on the next power-on, NVRAM 204 recovers/reads data from the flash memory array 206. Furthermore, NVRAM 204 buffers data read from SSD/HDD for higher speed access for Jibaja’s processing devices).
Per independent claim 18, the claim is the method performed by the memory device of claim 1, as such it is rejected on the same grounds mutatis mutandis.
Dependent Claims:
Per claim 2, Jibaja further teaches an input of a second processing resource of the one or more processing resources is configured to receive an output of a first processing resource of the one or more processing resources (see Figs. 4-7, col. 37, lines 62-64, and col. 40, lines 16-22, data producer 402 executes on storage system 406 by one of the processing resources 416-420, and the data producer 402 outputs or writes dataset 404, which is ingested by a processing resource allocated to an analytics application).
Per claim 3, Jibaja further teaches the control circuitry is configured to cause the memory device to: configure at least one of the one or more processing resources as a respective node of a network (see col. 31, lines 17-36, and col. 34, lines 8-34, the processing resources such as GPUs within each storage note 150 may be nodes of a neural network with networking connectivity).
Per claim 6, Jibaja further teaches a first processing resource of the one or more processing resources is coupled with a first set of memory cells of the memory array; and a second processing resource of the one or more processing resources is coupled with a second set of memory cells of the memory array (see Figs. 4-7, each processing resource 416-420 is coupled to a storage device 430-434).
Per claim 7, Jibaja further teaches the control circuitry is further configured to cause the memory device to: determine operations performed by the one or more processing resources to process the raw data (see Fig. 4-7, the circuitry for performing the steps 408, 410, 412 and 414 can be construed as control circuitry, as such Jibaja’s control circuitry determines operations to be performed by the processing resources 716-720 to process the unstructured datasets).
Per claim 8, Jibaja further teaches the control circuitry is further configured to cause the memory device to: activate the one or more processing resources in response to receiving the command (see col. 38, lines 20-29, note that Jibaja’s allocating of processing resources is construed as activating the processing resources).
Per claim 9, Jibaja further teaches the control circuitry is further configured to cause the memory device to: output the processed data from the memory device (see col. 33, lines 48-52 for preprocessing audio or image files, which are the type of files to be output from a memory device when requested by a client or user; also see col. 32, lines 53-67 for spanning the dataset training over multiple systems and a teach of data scientists sharing the datasets).
Per claim 10, Jibaja further teaches the control circuitry is further configured to cause the memory device to: write the processed data to memory cells of the memory array (see Fig. 7, “Store The Structured Dataset Within The Storage System 706”; also see Fig. 2C and col. 9, lines 46-51 for Flash memory cells).
Per claim 11, Jibaja further teaches the memory array comprises dynamic random access memory (DRAM) memory cells (see Fig. 2C and col. 20, lines 5-7, the storage unit 152 may comprise DRAM 216).
Per claim 19, Jibaja further teaches processing the raw data comprises: receiving an output of a first processing resource of the one or more processing resources at an input of a second processing resource of the one or more processing resources (see Figs. 4-7, col. 37, lines 62-64, and col. 40, lines 16-22, data producer 402 executes on storage system 406 by one of the processing resources 416-420, and the data producer 402 outputs or writes dataset 404, which is ingested by a processing resource allocated to an analytics application).
Per claim 20, Jibaja further teaches configuring at least one of the one or more processing resources as a respective node of a network (see col. 31, lines 17-36, and col. 34, lines 8-34, the processing resources such as GPUs within each storage note 150 may be nodes of a neural network with networking connectivity).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Jibaja, and further in view of Cosgrove et al. [Pub.No.: US 20200057933 A1] (hereinafter “Cosgrove”).
Per claim 4, Jibaja does not specifically teach: to process the raw data, the control circuitry is configured to cause the memory device to: configure the at least one of the one or more processing resources to combine inputs received by the respective nodes and weights corresponding to the respective nodes. However, Jibaja already teaches using a neural network of processing nodes to perform dataset training (see Jibaja, col. 31, lines 30-67). Combining inputs and weights from a plurality of neural network processing nodes was well known in the art before the filing of the claimed invention as a technique for training datasets. In an analogous art, Cosgrove teaches a neural network of processing nodes wherein weighted metric values and inputs of the nodes are mathematically combined to generate combined metric values for training (see Cosgrove, paragraphs [0063]-[0068]). It would have been obvious to one ordinarily skilled in the art before the effective filing date of the claimed invention to apply Cosgrove’s training method of combining weights and inputs of the nodes for training in Jibaja’s neural network system.
Per claim 5, Jibaja in view of Cosgrove further suggest the memory array is configured to store weights of the network and inputs to the network. Note that Jibaja already teaches the converted dataset is stored in storage system 406/706 for use by the Analytics Application (see Jibaja, Fig. 7, “Store The Structured Dataset Within The Storage System 706”). It would have been obvious to one ordinarily skilled in the art before the effective filing date of the claimed invention to further store the weights and inputs to Jibaja’s neural network in storage system 406/706 as together with the structured dataset they are also used for neural network training.
Response to Arguments
Applicant’s arguments filed on 14 July 2026 regarding claims 1-11 and 18-20 have been considered but are not persuasive. The rejections of independent claims 1 and 18 have been updated in response to the newly amended limitations in each said claim. In particular, the mapping of the Jibaja reference to the claimed term “latches” has been updated in response to the claim amendments. Applicant’s argument mainly focuses on the claimed “one or more latches” by stating “a non-volatile memory system is not the same as a latch because a latch is inherently volatile”, and “Jibaja’s NVRAM is a sub-component of the storage system described as a buffer to SSDs/HDDs, the NVRAM is not coupled to data lines of the memory array and configured to temporarily store charges representing data from the memory array”. In response, the Examiner clarifies that the storage system (406) depended in Fig. 4-7 of Jibaja corresponds to the storage node 150 depicted in Fig. 2C (see Jibaja, col. 37, lines 19-21). The Unstructured Dataset disclosed in col. 38, lines 25-29 is mapped to the claimed raw data, which is first stored in Storage devices 430-434 of Fig. 4 (or Flash Memory Array 206 or Flash dies 222 in Fig. 2C) in step 410 of Fig. 4. After processing resources are allocated to Analytics Application 422 in step 412 of Fig. 4, the Analytics Application 422 transforms unstructured/raw data into structured data (see col. 38, lines 25-29). The transformed/structured data must be stored back into Storage devices 430-434 of Fig. 4 (or Flash Memory Array 206 or Flash dies 222 in Fig. 2C) for permanent storage. Because DRAM 216 (or NVRAM 204) stores every update until the update has been written to flash 206 (see col. 21, lines 20-35 and col. 22, lines 36-38), and all read/writes to the flash die 222 must go through Register 226, either the DRAM 216/NVRAM 204 or Register 226 may be viewed as the claimed one or more latches. Because all data read/write operations to the flash array or flash dies must go through DRAM 216 and/or Register 226, DRAM 216 and/or Register 226 must be coupled to data lines of the memory array (Storage devices 430-434 of Fig. 4, or Flash Memory Array 206 or Flash dies 222 in Fig. 2C) and temporarily store charges representing data from the memory array.
Also note although Applicant’s statement that “a latch is inherently volatile” is outside the scope and meaning of the claim language, Jibaja nevertheless teaches that NVRAM 204 is a high speed volatile memory such as DRAM 216 (see col. 20, lines 5-7), and Jibaja’s Register 226 clearly fits the definition of a volatile latch.
Allowable Subject Matter
Claims 12-17 are allowed over prior art.
The following is a statement of reasons for the indication of allowable subject matter:
Per independent claim 12, Jibaja substantially teaches the claim, but fails to teach or render obvious the crossed-out portions as follows:
A memory device (see Fig. 2B, 2C for storage node 150; also see Fig. 3B and 4-6 for storage system 406, which corresponds to storage node 150), comprising:
a memory array (see Fig. 4-6 for storage devices 430-434; see Fig. 2C-2D for Flash Memory array 206);
one or more processing resources (see Fig. 4-6, processing resources 416-420; also see Fig. 2A and 2C for CPU 156; also see col. 37, lines 62-64 and Figs 4-6, the processing resource executing the data producer 402 on the storage system 406 is also one of the claimed processing resources); and
control circuitry coupled to the memory array and the one or more processing resources (see Fig. 2C for PLD 208; also see Fig. 4-6, the circuitry for performing the steps 408, 410, 412 and 414 can be construed as control circuitry), the control circuitry configured to cause the memory device to:
receive a command from a host device (see col. 20, lines 49-50 for storage devices in storage node 150 receiving command to read, write or erase data; also see col. 38, lines 25-29, one of the processing resources 416-420 allocated to the Analytics Application 422 can be mapped to the claimed host device)
transfer raw data from the memory array (see Fig. 4, the unstructured Dataset 410 is first stored in step 410 as Dataset Slices 424-428 in Storage Devices 430-434. Step 412 then allocates processing resources to Analytics Application 422, which transforms unstructured/raw data stored in step 410 into structured data, see col. 38, lines 25-29) to the one or more processing resources in response to the command from the host device (see col. 38, lines 25-29, to transform unstructured data stored in step 410 into structured data, the unstructured data must be provided from Storage Devices 430-434 to Analytics Application 422 running on the processing resources 416-420 or CPU 156 );
process the raw data at the one or more processing resources by executing instructions from the host device (see col. 38, lines 25-29, transform unstructured data into structured data; also see col. 32, lines 10-13 for ingesting raw data and transforming the raw data to a format convenient for training. Also see Fig. 4, the unstructured Dataset 410 is first stored in step 410 as Dataset Slices 424-428 in Storage Devices 430-434. Step 412 then allocates processing resources to Analytics Application 422, which transforms unstructured/raw data into structured data, see col. 38, lines 25-29); and
transfer the processed data from one or more latches coupled with the one or more processing resources to the host device (all data read from flash memory must go through NVRAM 204/DRAM 216 or Register 226, and the transformed data stored on flash memory are later used for big data analysis), wherein the latches are configured to temporarily store data (see col. 3, line 54 to col. 4, line 7, col. 6, lines 47-50, col. 8, line 55 to col. 9, line 6, col. 9, lines 31-35, col. 13, lines 8-13, col. 20, lines 36-37 and col. 21, lines 20-35; NVRAM 204 only maintains the state of the RAM after main power loss long enough to write the RAM data to persistent SSD/HDD, as such it only temporarily stores data) from the memory array during one or more operations (see col. 21, lines 20-35; on the next power-on, NVRAM 204 recovers/reads data from the flash memory array 206. Furthermore, NVRAM 204 buffers data read from SSD/HDD for higher speed access for Jibaja’s processing devices).
Jibaja fails to teach or render obvious that its host device is different than the one or more processing resources, because one of Jibaja’s processing resources 416-420 allocated to the Analytics Application 422 can be mapped to the claimed host device. In another interpretation of Jibaja, a specific processing resource such as Processing Sources 420 may be mapped to the claimed host device, while the other Processing Resources 416 and 418 are mapped to the claimed one or more processing resources. Although this may satisfy the limitation “a host device that is different than the one or more processing resources”, it fails to teach or render obvious “transfer raw data from the memory array to the one or more processing resources in response to the command from the host device”, or “process the raw data at the one or more processing resources by executing instructions from the host device”. Jibaja’s processing resources do not perform data transfer or raw data processing on behave of one another.
Cosgrove et al. [Pub.No.: US 20200057933 A1] (hereinafter “Cosgrove”) teaches a neural network of processing nodes wherein weighted metric values and inputs of the nodes are mathematically combined to generate combined metric values for training, but fails to address Jibaja’s deficiencies set forth above.
Thimmegowda et al. [Pub.No.: US 20190043874 A1] (hereinafter “Thimmegowda”) teaches an analogous memory device wherein processing resources are fabricated under memory arrays using CMOS under array techniques, but fails to address Jibaja’s deficiencies set forth above.
Dependent claims 13-17 are dependent on claim 12 and are allowable for at least the same reasons.
Conclusion
Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN X GU whose telephone number is (571)272-0703. The examiner can normally be reached on 9am-5pm, Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN X GU/
Primary Examiner
Art Unit 2138
9 September 2026
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