DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular paragraphs or columns and lines in the references as applied to the claims below for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by this Examiner.
Response to Amendment
This Office action is in response to the amendment and remarks filed 4 March 2026. Claims 1-20 are pending. All objections and rejections not repeated below are withdrawn.
Terminal Disclaimer
The terminal disclaimer filed on 12 December 2025 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration dates of U.S. Patent Nos. 11055003 and 12086443 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 12-17 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Per claim 12, line 12, “the latches” is indefinite as the term indicates multiple latches. However, line 11 of the instant claim teaches the term “one or more latches”, which can be interpreted to indicate a single latch. Under this interpretation there is insufficient antecedent basis for “the latches” on line 12. It would be more appropriate to insert “one or more” before “latches” on line 12.
All dependent claims are rejected as inheriting the same deficiencies as the claims they depend from. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-15 and 18-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jibaja et al. [Patent No.: US 10,452,444] (hereinafter “Jibaja”).
Independent Claims:
Per independent claim 1, Jibaja teaches:
A memory device (see Fig. 2B, 2C for storage node 150; also see Fig. 3B and 4-7 for storage system 406, which corresponds to storage node 150), comprising:
a memory array (see Fig. 4-7 for storage devices 430-434; see Fig. 2C-2D for Flash Memory array 206);
one or more processing resources (see Fig. 4-7, processing resources 416-420; also see Fig. 2A and 2C for CPU 156; also see col. 37, lines 62-64 and Figs 4-7, the processing resource executing the data producer 402 on the storage system 406 is also one of the claimed processing resources); and
control circuitry coupled to the memory array and the one or more processing resources (see Fig. 2A and 2C-2D for controller 212/246 and PLD 208; also see Fig. 4-7 for processing resources 416-420 comprising Analytics Application 422), the control circuitry configured to cause the memory device to:
receive a command at the memory device (see col. 20, lines 49-50 for storage devices in storage node 150 receiving command to read, write or erase data; see col. 36, lines 12-67 for storage system supporting big data analytical applications 422 in Fig. 7; also see col. 42, lines 5-10, there must be a command/instruction received at the storage system that results in the execution of the converting step 704);
process, by the one or more processing resources, raw data transferred from the memory array in response to receiving the command (see Fig. 7, “Convert The Unstructured Dataset Into A Structured Dataset 704” and col. 41, lines 48-67; also see col. 32, lines 10-13 for ingesting raw data and transforming the raw data to a format convenient for training); and
store a result of the processing (see Fig. 7, “Store The Structured Dataset Within The Storage System 706”) in latches coupled with the one or more processing resources (see Fig. 2C-2G, NVRAM 204, also see Fig. 2A, Mem 154 and Fig. 1B, RAM 111, which are all different embodiments of higher speed buffers/latches connected to one or more processing device (storage devices 430-434 in Fig. 7 are SSD/HDD devices, see col. 37, lines 35-37, while storage system 406 in Fig. 7 is equivalent to the storage systems shown in Figs. 1A-1D, 2A-2G and 3A-3B, see col. 37, lines 19-21. As such NVRAM 204 are latches/buffers to SSD/HDD devices 430-434 in Fig. 7). Also note that each storage unit of NVRAM 204 may be viewed as a latch), wherein the latches are configured to temporarily store data (see col. 3, line 54 to col. 4, line 7, col. 6, lines 47-50, col. 8, line 55 to col. 9, line 6, col. 9, lines 31-35, col. 13, lines 8-13, col. 20, lines 36-37 and col. 21, lines 20-35; NVRAM 204 only maintains the state of the RAM after main power loss long enough to write the RAM data to persistent SSD/HDD, as such it only temporarily stores data) from the memory array during one or more operations (see col. 21, lines 20-35; on the next power-on, NVRAM 204 recovers/reads data from the flash memory array 206. Furthermore, NVRAM 204 buffers data read from SSD/HDD for higher speed access for Jibaja’s processing devices).
Per independent claim 12, Jibaja teaches:
A memory device (see Fig. 2B, 2C for storage node 150; also see Fig. 3B and 4-7 for storage system 406, which corresponds to storage node 150), comprising:
a memory array (see Fig. 4-7 for storage devices 430-434; see Fig. 2C-2D for Flash Memory array 206);
one or more processing resources (see Fig. 4-7, processing resources 416-420; also see Fig. 2A and 2C for CPU 156; also see col. 37, lines 62-64 and Figs 4-7, the processing resource executing the data producer 402 on the storage system 406 is also one of the claimed processing resources); and
control circuitry coupled to the memory array and the one or more processing resources (see Fig. 2C for PLD 208; also see Fig. 4-7, the circuitry for performing the steps 408, 410, 412 and 414 can be construed as control circuitry), the control circuitry configured to cause the memory device to:
receive a command from a host device (see col. 38, lines 19-29, col. 39, lines 17-21, and Fig. 7, step 414, the Analytics Applications 422 and 506 read, ingest, transform/convert and examine the dataset, therefore the claimed host device may be construed as the combination of analytics applications and the processing resource executing these applications. The Analytics Applications also issues commands/requests for accessing unstructured datasets stored within the Storage System 406 for conversion/preprocessing and examination, and these commands/requests may be considered as being received by the Storage system 406 as it is received by devices such as Storage Devices 430-434 within the Storage system 406);
transfer raw data from the memory array (see col. 32, lines 10-12 and col. 46, lines 30-32, the ingested raw data is first stored in raw form in the storage system 406 before being preprocessed; also see col. 41, line 48 to col. 42, line 23, the unstructured dataset consists of substantially quantities of data and is preprocessed into structured data through data mining techniques. Such quantities of data cannot exist in a vacuum and must be stored in data storage devices. As Jibaja shows Storage Devices 430-434 storing Dataset Slices 424-428 in Fig. 7, raw/unstructured datasets must also be stored in Jibaja’s memory array/Storage Devices 430-434) to the one or more processing resources in response to the command from the host device (see col. 38, lines 21-28 and lines 54-57, the analytics application 422 run by processing resources 416-420 issues commands to read unstructured dataset from the storage system 406/Storage Devices 430-434; also see col. 39, lines 10-25, real-time analytics application 506 executing on processing resources 418 transforms unstructured data into structured data and examines datasets. The unstructured datasets are transferred to the processing resources for processing/analysis by the analytics applications 422 and 506, as such are they are transferred from the Data Devices 430-434 to the processing resources 416-420 in response to the command/request from the host, which is mapped to the combination of analytics applications and the processing resource executing these applications);
process the raw data at the one or more processing resources by executing instructions from the host device (see Fig. 7, “Convert The Unstructured Dataset Into A Structured Dataset 704” and col. 41, lines 48-67; also see col. 32, lines 10-13 for ingesting raw data and transforming the raw data to a format convenient for training; also see col. 38, lines 21-28 and lines 54-57, the Analytics Application 422 run by processing resources 416-420 issues commands to read unstructured dataset and transform it into structured dataset); and
transfer the processed data from one or more latches coupled with the one or more processing resources to the host device (see Fig. 7, steps 704, 706 and 414, the converted structured data set is transferred to the processing resources executing the Analytics Application to be examined. Note that the analytics applications 422 and 506 are executed on one or more of the processing resources 416, 418 and 420 (see col. 38, lines 30-49 and col. 39, lines 10-32) as part of a system for big data analysis and machine learning, where raw/unstructured data are first preprocessed into structured dataset and stored in the storage system 406 for subsequent or real time big data analysis and machine learning, see col. 36, lines 12-21, col. 38, lines 19-29 and col. 39, lines 10-25. The converted structured data is stored in a latch/buffer memory such as NVRAM 204 in Fig. 2C-2G. Also see Fig. 2A, Mem 154 and Fig. 1B, RAM 111, which are all different embodiments of higher speed buffers/latches connected to one or more processing device. Note that each storage unit of NVRAM 204 may be viewed as a latch. Also note that storage devices 430-434 in Fig. 7 are SSD/HDD devices, see col. 37, lines 35-37, while storage system 406 in Fig. 7 is equivalent to the storage systems shown in Figs. 1A-1D, 2A-2G and 3A-3B, see col. 37, lines 19-21. As such NVRAM 204 are latches/buffers to SSD/HDD devices 430-434 in Fig. 7), wherein the latches are configured to temporarily store data (see col. 3, line 54 to col. 4, line 7, col. 6, lines 47-50, col. 8, line 55 to col. 9, line 6, col. 9, lines 31-35, col. 13, lines 8-13, col. 20, lines 36-37 and col. 21, lines 20-35; NVRAM 204 only maintains the state of the RAM after main power loss long enough to write the RAM data to persistent SSD/HDD, as such it only temporarily stores data) from the memory array during one or more operations (see col. 21, lines 20-35; on the next power-on, NVRAM 204 recovers/reads data from the flash memory array 206. Furthermore, NVRAM 204 buffers data read from SSD/HDD for higher speed access for Jibaja’s processing devices).
Per independent claim 18, Jibaja teaches:
A method at a memory device (see Fig. 2B, 2C for storage node 150; also see Fig. 3B and 4-7 for storage system 406, which corresponds to storage node 150), comprising:
receiving a command at the memory device (see col. 20, lines 49-50 for storage devices in storage node 150 receiving command to read, write or erase data; see col. 36, lines 12-67 for storage system supporting big data analytical applications 422 in Fig. 7; also see col. 42, lines 5-10, there must be a command/instruction received at the storage system that results in the execution of the converting step 704);
processing, by one or more processing resources of the memory device (see Fig. 4-7, processing resources 416-420; also see Fig. 2C for CPU 156; also see col. 37, lines 62-64 and Figs 4-7, the processing resource executing the data producer 402 on the storage system 406 is also one of the claimed processing resources), raw data transferred from a memory array (see Fig. 4-7 for storage devices 430-434) of the memory device in response to receiving the command (see Fig. 7, “Convert The Unstructured Dataset Into A Structured Dataset 704” and col. 41, lines 48-67; also see col. 32, lines 10-13 for ingesting raw data and transforming the raw data to a format convenient for training); and
storing a result of the processing in latches of the memory device coupled with the one or more processing resources (see Fig. 7, “Store The Structured Dataset Within The Storage System 706”; see Fig. 7 for storage device 430-434 coupled to processing resources 416-420. The converted/processed structured dataset is stored in a latch/buffer memory such as NVRAM 204 in Fig. 2C-2G for faster access. Also see Fig. 2A, Mem 154 and Fig. 1B, RAM 111, which are all different embodiments of higher speed buffers/latches connected to one or more processing device. Note that each storage unit of NVRAM 204 may be viewed as a latch. Also note that storage devices 430-434 in Fig. 7 are SSD/HDD devices, see col. 37, lines 35-37, while storage system 406 in Fig. 7 is equivalent to the storage systems shown in Figs. 1A-1D, 2A-2G and 3A-3B, see col. 37, lines 19-21. As such NVRAM 204 are latches/buffers to SSD/HDD devices 430-434 in Fig. 7), wherein the latches are configured to temporarily store data (see col. 3, line 54 to col. 4, line 7, col. 6, lines 47-50, col. 8, line 55 to col. 9, line 6, col. 9, lines 31-35, col. 13, lines 8-13, col. 20, lines 36-37 and col. 21, lines 20-35; NVRAM 204 only maintains the state of the RAM after main power loss long enough to write the RAM data to persistent SSD/HDD, as such it only temporarily stores data) from the memory array during one or more operations (see col. 21, lines 20-35; on the next power-on, NVRAM 204 recovers/reads data from the flash memory array 206. Furthermore, NVRAM 204 buffers data read from SSD/HDD for higher speed access for Jibaja’s processing devices).
Dependent Claims:
Per claim 2, Jibaja further teaches an input of a second processing resource of the one or more processing resources is configured to receive an output of a first processing resource of the one or more processing resources (see Figs. 4-7, col. 37, lines 62-64, and col. 40, lines 16-22, data producer 402 executes on storage system 406 by one of the processing resources 416-420, and the data producer 402 outputs or writes dataset 404, which is ingested by a processing resource allocated to an analytics application).
Per claim 3, Jibaja further teaches the control circuitry is configured to cause the memory device to: configure at least one of the one or more processing resources as a respective node of a network (see col. 31, lines 17-36, and col. 34, lines 8-34, the processing resources such as GPUs within each storage note 150 may be nodes of a neural network with networking connectivity).
Per claim 6, Jibaja further teaches a first processing resource of the one or more processing resources is coupled with a first set of memory cells of the memory array; and a second processing resource of the one or more processing resources is coupled with a second set of memory cells of the memory array (see Figs. 4-7, each processing resource 416-420 is coupled to a storage device 430-434).
Per claim 7, Jibaja further teaches the control circuitry is further configured to cause the memory device to: determine operations performed by the one or more processing resources to process the raw data (see Fig. 4-7, the circuitry for performing the steps 408, 410, 412 and 414 can be construed as control circuitry, as such Jibaja’s control circuitry determines operations to be performed by the processing resources 716-720 to process the unstructured datasets).
Per claim 8, Jibaja further teaches the control circuitry is further configured to cause the memory device to: activate the one or more processing resources in response to receiving the command (see col. 38, lines 20-29, note that Jibaja’s allocating of processing resources is construed as activating the processing resources).
Per claim 9, Jibaja further teaches the control circuitry is further configured to cause the memory device to: output the processed data from the memory device (see col. 33, lines 48-52 for preprocessing audio or image files, which are the type of files to be output from a memory device when requested by a client or user; also see col. 32, lines 53-67 for spanning the dataset training over multiple systems and a teach of data scientists sharing the datasets).
Per claim 10, Jibaja further teaches the control circuitry is further configured to cause the memory device to: write the processed data to memory cells of the memory array (see Fig. 7, “Store The Structured Dataset Within The Storage System 706”; also see Fig. 2C and col. 9, lines 46-51 for Flash memory cells).
Per claim 11, Jibaja further teaches the memory array comprises dynamic random access memory (DRAM) memory cells (see Fig. 2C and col. 20, lines 5-7, the storage unit 152 may comprise DRAM 216).
Per claim 13, Jibaja further teaches the control circuitry is further configured to cause the memory device to: activate the one or more processing resources in response to receiving the command (see col. 38, lines 20-29, note that Jibaja’s allocating of processing resources is construed as activating the processing resources).
Per claim 14, Jibaja further teaches to process the raw data, the control circuitry is configured to cause the memory device to: receive, by the one or more processing resources, the raw data in a first format; and generate, by the one or more processing resources, the processed data in a second format (see col. 32, lines 10-13, transform raw data into a format convenient for training, see Fig. 7, “Convert The Unstructured Dataset Into A Structured Dataset 704”).
Per claim 15, Jibaja further teaches the memory array is included in a first chip (see col. 20, lines 16-21 for single die per package) and at least one of the one or more processing resources is included in a second chip (see col. 29, lines 34-41 for systems on a chip/SoCs).
Per claim 19, Jibaja further teaches processing the raw data comprises: receiving an output of a first processing resource of the one or more processing resources at an input of a second processing resource of the one or more processing resources (see Figs. 4-7, col. 37, lines 62-64, and col. 40, lines 16-22, data producer 402 executes on storage system 406 by one of the processing resources 416-420, and the data producer 402 outputs or writes dataset 404, which is ingested by a processing resource allocated to an analytics application).
Per claim 20, Jibaja further teaches configuring at least one of the one or more processing resources as a respective node of a network (see col. 31, lines 17-36, and col. 34, lines 8-34, the processing resources such as GPUs within each storage note 150 may be nodes of a neural network with networking connectivity).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Jibaja, and further in view of Cosgrove et al. [Pub.No.: US 20200057933 A1] (hereinafter “Cosgrove”).
Per claim 4, Jibaja does not specifically teach: to process the raw data, the control circuitry is configured to cause the memory device to: configure the at least one of the one or more processing resources to combine inputs received by the respective nodes and weights corresponding to the respective nodes. However, Jibaja already teaches using a neural network of processing nodes to perform dataset training (see Jibaja, col. 31, lines 30-67). Combining inputs and weights from a plurality of neural network processing nodes was well known in the art before the filing of the claimed invention as a technique for training datasets. In an analogous art, Cosgrove teaches a neural network of processing nodes wherein weighted metric values and inputs of the nodes are mathematically combined to generate combined metric values for training (see Cosgrove, paragraphs [0063]-[0068]). It would have been obvious to one ordinarily skilled in the art before the effective filing date of the claimed invention to apply Cosgrove’s training method of combining weights and inputs of the nodes for training in Jibaja’s neural network system.
Per claim 5, Jibaja in view of Cosgrove further suggest the memory array is configured to store weights of the network and inputs to the network. Note that Jibaja already teaches the converted dataset is stored in storage system 406/706 for use by the Analytics Application (see Jibaja, Fig. 7, “Store The Structured Dataset Within The Storage System 706”). It would have been obvious to one ordinarily skilled in the art before the effective filing date of the claimed invention to further store the weights and inputs to Jibaja’s neural network in storage system 406/706 as together with the structured dataset they are also used for neural network training.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Jibaja, and further in view of Thimmegowda et al. [Pub.No.: US 20190043874 A1] (hereinafter “Thimmegowda”).
Per claim 17, Jibaja does not specifically teach at least one of the one or more processing resources is configured as a complementary metal-oxide-semiconductor (CMOS) under the memory array. CMOS under array type fabrication technology was well known in the art before the filing of the claimed invention for reducing device size and power consumption. Thimmegowda teaches an analogous memory device wherein processing resources are fabricated under memory arrays using CMOS under array techniques (see Thimmegowda, paragraph [0023], lines 17-20). It would have been obvious to one ordinarily skilled in the art before the effective filing date of the claimed invention to apply Thimmegowda’s CMOS under array fabrication technique in Jibaja’s memory device to reduce physical device size and power consumption.
Per claim 16, Jibaja does not specifically teach the memory array and at least one of the one or more processing resources is included in a same chip, however Jibaja teaches implementing the processing resources 312 with system-on-chip technology (see Jibaja, col. 29, lines 34-41). Applying the same motivation for combining Jibaja and Thimmegowda set forth above for claim 17, it would have been obvious to one ordinarily skilled in the art before the effective filing date of the claimed invention to apply Thimmegowda’s CMOS under array fabrication technique in Jibaja’s memory device to reduce physical device size and power consumption (note that Thimmegowda’s memory array and processing circuitry are included in the same chip, see Thimmegowda, Fig. 2, memory die 200 including memory array 202 and peripheral circuitry 204).
Response to Arguments
Applicant’s arguments filed on 4 March 2026 regarding claims 1-20 have been considered but are not persuasive. The rejections of each amended independent claims 1, 12 and 18 have been updated in response to the newly amended limitations in each said claim. In particular, the mapping of the Jibaja reference to the claimed term “latches” has been updated in response to the claim amendments. As the Applicant’s arguments are entirely directed to the amended limitations of said claims, the updated rejections are considered to be sufficient response to the arguments.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN X GU whose telephone number is (571)272-0703. The examiner can normally be reached on 9am-5pm, Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on 571-272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN X GU/
Primary Examiner
Art Unit 2138
27 April 2026
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