DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Herein after “it would have been obvious” should be read as “it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention”.
Response to Arguments
Applicant's arguments filed 6/15/26 have been fully considered but they are not persuasive.
In regards to applicants argument that Naffzinger teaches a method of limiting power consumption by limiting frequency operation: the examiner agrees. Naffzinger limits both voltage V.sub.1 and frequency using a variable V.sub.1 that controls a voltage controlled oscillator [0036] “As shown in FIG. 1, in one embodiment, the received voltage signal V.sub.1 and ground signal G.sub.1 are fed both to core chip circuitry 112 and oscillator 108. In such embodiment, oscillator 108 adjusts the frequency of clock CLK.sub.1 generated thereby based on the value of voltage V.sub.1” [0037] “For instance, as voltage V.sub.1 decreases, the frequency of CLK.sub.1 output by oscillator 108 decreases. As a result, voltage controlled oscillator 108 of this embodiment allows for chip 106 to self-regulate its power consumption”. In figure 4 the voltage V.sub.1 is supplied to both the power chip 402 and the core 403.).
In regards to applicants argument regarding the lookup table 601 of figure 6: The examiner agrees that Naffzinger teaches an alternative embodiment where the frequency is controlled by a lookup table. The rejection however was addressed to figure 4, 1, and 2 [0051] “Chip 401 further comprises power management logic 402 for self-regulating its power consumption. Preferably, such power management logic 402 may be implemented in the manner described in FIG. 1 or FIG. 2 above. For instance, such power management logic 402 may comprise a voltage controlled frequency oscillator (e.g., oscillator 108 of FIG. 1 or 2 above) that generates a clock signal (e.g., CLK.sub.1 in above examples of FIGS. 1 and 2) that is utilized as the clock signal for the core chip circuitry 403”). Naffzinger clearly teaches for the embodiment of figure 4 the clock Clk.sub.1 is based upon the voltage V.sub.1 that powers the core 403.
In regards to applicants argument that Naffzinger does not teach “providing a variable voltage to the processor”. In the rejection the examiner identified 401 or alternatively 403 as the processor. V.sub.1 supplied to processor 401 and 403 is a variable voltage ([0037] “For instance, as voltage V.sub.1 decreases, the frequency of CLK.sub.1 output by oscillator 108 decreases”).
In regards to applicants argument that Naffzinger does not teach “Generate, based on the variable voltage, a variable operating frequency and to provide the variable frequency clock signal to the processing module”: Naffzinger teaches [0036] “As shown in FIG. 1, in one embodiment, the received voltage signal V.sub.1 and ground signal G.sub.1 are fed both to core chip circuitry 112 and oscillator 108. In such embodiment, oscillator 108 adjusts the frequency of clock CLK.sub.1 generated thereby based on the value of voltage V.sub.1”
In regards to applicants argument that Naffzinger does not teach “providing a variable voltage to the processor “Operate (the processing module) at the varied voltage AND frequency”: Naffzinger teaches [0037] “V represents operating voltage (e.g., voltage V.sub.1), and F represents the clock frequency of chip 106 (e.g., frequency of CLK.sub.1)”. This is operating at voltage V.sub.1 and clk.sub.1.
In regards to applicants argument that the embodiment of figure 5 is not the same as applicants claimed invention. The embodiments of figures 1-4 are the same as applicants claimed invention.
In regards to applicants argument regarding in the present application the “operating voltage” is the voltage at the processing module after transmission is lost. Claim 1 never mentions transmission much less the transmission being lost.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the “operating voltage” is the voltage at the processing module after transmission is lost) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
The claim language only requires an operating variable voltage being applied to a processor (V.sub.1 is variable) and a frequency (CLK.sub.1) applied being based upon the variable voltage (V.sub.1) which is what Naffzinger teaches.
In regards to applicants argument that claim 2 requires a mapped relationship between voltage and frequency, not power and frequency as Naffzinger teaches. Naffzinger clearly reaches the relationship between voltage and frequency. It is expressly a voltage controller oscillator which controls frequency based upon voltage. Power is voltage time current.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 8-9, 16is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Naffziger PN 2012/0054521.
In regards to claims 1, 9: Naffziger teaches a power supply circuit, comprising: a power supply module (102 or 102 and 104 taken together); a processing module (401 or 403); a clock generator module (401 [0051] "For instance, such power management logic 402 may comprise a voltage controlled frequency oscillator (e.g., oscillator 108 of FIG. 1 or 2 above) that generates a clock signal (e.g., CLK.sub. 1 in above examples of FIGS. 1 and 2)" voltage controlled frequency oscillator 108 (figure 1)); and wherein: the power supply module is configured to supply power (V.sub.1) to the processing module (401 or 403 (V.sub.1) is supplied to the microprocessor 401 and to the processor core 403 figure 4) at a variable operating voltage ([0051] "Additionally, as described below, power management logic 402 is preferably operable to control power supply 102 to dynamically change the supply voltage ("VDD") supplied to chip 401"); the clock generator module is configured to: generate, based on the operating voltage ([0036] "As shown in FIG. 1, in one embodiment, the received voltage signal V.sub. 1 and ground signal G.sub. 1 are fed both to core chip circuitry 112 and oscillator 108. In such embodiment, oscillator 108 adjusts the frequency of clock CLK.sub.1 generated thereby based on the value of voltage V.sub. 1."), a clock signal with a variable operating frequency (adjusts the frequency), and provide the clock signal to the processing module (CLK₁); and the processing module is configured to run based on the operating voltage and the operating frequency (Claim 4: "The integrated circuit of claim 1, wherein the power management logic is to dynamically set the clock signal to the determined frequency value based at least in part on adjusting a voltage supplied to the core circuitry". The examiner notes the claim language does not state the clock generator module cannot be internal to the processor module thus either the entire microprocessor (401) or just the processor core (403) can be read on the claimed "processing module".
In regards to claim 2: Nafziger teaches a preset mapping between power and frequency. ([0067] "So, if the maximum power limit of the chip is 100 W, setting it to 80 W (0.8 in the graph of FIG. 5), would result in the frequency being set to 0.9 times the maximum frequency. The exact relationship between power and frequency is preferably determined by characterization of typical silicon such that across all manufacturing variations and temperatures, the chip can be guaranteed to be within some tolerance (e.g., approximately 5% or less) of the specified frequencies for a given power limit"). Power is voltage times current thus the relationship is also between voltage and frequency.
In regards to claims 8, 16: Naffziger teaches the clock generator (108) is internal to the processing module (106 figure 1 or 401 figure 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Naffziger PN 2012/0054521 in view of Knotts PN 2005/0105660 and Block et al PN 2008/0258700.
In regards to claims 3, 11: Naffziger teaches measuring the power consumption [0078] for controlling the voltage and frequency as opposed to measuring the frequency. Naffziger also mention a voltage regulator [0009] but does not state that the voltage regulation is based on the target frequency and the average frequency. Knotts teaches ([0044] "In one implementation, a frequency correction cycle has two phases, a measurement phase (.DELTA.' and a correction phase (.DELTA.T.sub.2). During the measurement phase, the average frequency of the VCO signal during the time .DELTA.T.sub.1 is measured. During the correction phase, the VCO controlling voltage, V.sub.tune, is changed by an amount equal to .DELTA.V, where .DELTA.V=I.sub.F*.DELTA.T.sub.2/C”). It would have been obvious to measure the average frequency to control the VCO because this would have provided a phase locked loop (PLL). Knotts does not mention a voltage regulator. Block teaches comparing a target frequency with an operating frequency to control a voltage regulator. ([0008] "The voltage regulator, which is external to the integrated circuit chip, provides the chip with a supply voltage having a level based on a control signal. A comparator circuit supplies the control signal to the voltage regulator based on a comparison between a frequency of the clock output and a frequency of the reference clock"). It would have been obvious to control the regulated voltage based upon the frequency because this would have addressed ([0001] "changes in on-chip delays due to changes in process, voltage and temperature of the chip").
Claim(s) 4, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Naffziger PN 2012/0054521 in view of Knotts PN 2005/0105660 and Block et al PN 2008/0258700 as applied to claim 3 above, and further in view of King PN 2006/0119339.
In regards to claims 4, 12: Naffziger teaches the power supply is a battery for a computer. A battery is a DC power source. Naffziger et al also teaches the voltage is adjustable and voltage droop is addressed. While batteries for computers are routinely "smart" batteries that include internal digital voltage regulators, Naffziger does not state that power supply includes a "digital" voltage regulator/stabilizer. King teaches a digital voltage regulator for a power supply ([0110] "The abrupt resumption of load (from a low-load state) presents the more serious challenge to designers of power supply regulators. In the case of a buck converter, for example, the slam is typically detected when the (slam-induced) droop in the output voltage triggers a threshold detection mechanism"). The voltage level before the droop is the desired voltage level. Thus King teaches the digital voltage stabilizer after a droop increases the operating voltage to the desired voltage value which is the voltage value before the dip. [0110] "The transition from PFM to PWM may then be accomplished straightforwardly, by holding the switch ON until the energy stored in the converter is sufficient to supply the new load at the desired output voltage (via the PWM duty cycle control mechanism)"). It would have been obvious to include a digital voltage regulator/stabilizer in the power supply because this would have addressed voltage droop "that amplitude of the output voltage error is continually minimized" as well as a variable output voltage "desired output voltage".
In regards to claims 5, 13: King teaches sending an alarm/"voltage error signal" to the voltage regulator when the dip occurs, the voltage regulator then increases the voltage supplied "by holding the switch ON until the energy stored in the converter is sufficient to supply the new load at the desired output voltage" ([0096] "The duty cycle control mechanism is comprised of a target duty cycle estimator/output voltage error estimator 234, a mechanism for estimating, from an output voltage error signal or an input voltage signal or a combination of both, the target duty cycle, DT, and the uncorrupted output voltage error, VE; a variable-frequency duty cycle quantizer 224 for determining the quantized duty cycle DQ closest to the target duty cycle estimate, DT; and an output-voltage-error-driven duty cycle selector 214, a mechanism for determining the turn ON and turn OFF times of switching device 114 by generating, for each value of DQ, a set of six quantized duty cycles (DQmin, DQmn, DQn, DQx, DQmx, and DQmax, ordered from lowest to highest) and by choosing, cycle by cycle, DQmin or DQmn or DQn or DQx or DQmx or DQmax (and its corresponding ON time/OFF time pair), choosing in such a manner that amplitude of the output voltage error is continually minimized").
In regards to claim 15: Naffziger teaches the clock generator (108) is internal to the processing module (106 figure 1 or 401 figure 4) integrated on a chip. See also MPEP 2144.04 V.B. Making integral is not a patentable distinction. It would have been obvious to integrate the digital voltage stabilizer and the processor onto a chip because this would have reduced size.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Naffziger PN 2012/0054521 in view of Knotts PN 2005/0105660, Block et al PN 2008/0258700, and King PN 2006/0119339 as applied to claim 4 above, and further in view of Schrom et al PN 2013/0113444 and Kalyanam et al PN 2020/0081479.
In regards to claims 7, 14: Naffziger teaches 1 processing modules, 1 clock generator modules, 1 clock measurement modules, and one or 1 voltage regulator modules, the power supply module comprises one direct current power supply unit (battery) King teaches and 1 digital voltage stabilizer units, and the direct current power supply unit is configured to supply power to the 1 digital voltage stabilizer units, wherein N is a positive integer equal to 1. Naffziger and King do not teach more than on of each unit. Schrom et al teaches a single power supply supplying power to plural voltage regulators each for their own processing core (claim 15: "An integrated circuit comprising: a processor having multiple processing cores; and a plurality of voltage regulators, each of which to provide a corresponding regulated power supply voltage to a corresponding processing core from among the multiple processing cores"). Kalyanam et al teaches ([0070] "In FIG. 2B, multiple gated clock signals 137 may be generated by the clock circuitry 198 for each of a plurality of N processors (where N indicates a positive integer greater than one)"). MPEP 2144./04 VIB. states a duplication of parts "has no patentable significance unless a new and unexpected result is produced.". It would have been obvious to have plural voltage regulators and clock generators corresponding to each processing core because this would have allowed for separate control of each processing cores clock and voltage.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL R MYERS whose telephone number is (571)272-3639. The examiner can normally be reached telework M-F start 7-8 leave 4-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Paul R. MYERS/ Primary Examiner, Art Unit 2176
Prosecution Insights