DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim(s) 1 – 20 have been canceled.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant's arguments filed 03/11/2026 regarding the prior art rejections of Claims 21 – 40 have been fully considered and are persuasive.
The Remarks argue that:
Claims 1-20 were rejected under 35 U.S.C. §103 as being unpatentable over Miller in
view of Gupta. Without a disclaimer to any other reason that may have been previously raised or can be raised for traversal of this rejection, this rejection is respectfully traversed for at least the following reasons.
Independent claims 1, 10 and 17 stand rejected in the non-final Office Action under 35
U.S.C. §103 as being unpatentable over Miller in view of Gupta. Independent claims 21, 30, and 37 include features similar to those of cancelled claims 1, 10, and 17 and accordingly the Applicant will address the arguments raised by the Examiner in the Office Action with respect to these claims and distinguishing features of claims 21, 30, and 37.
In the non-final Office Action (pgs. 2-3), the Examiner asserted that Gupta's disclosure
regarding the handling of data latches during a program suspend operation reads on the claimed
features of repairing the input data and applying the set logic operation. The Applicant respectfully submits that these rejections are moot in view of the claimed amendments presented herein.
Claim 21 as added includes distinguishable subject matter to the cited references. In
particular, claim 21, as added, recites:
"A memory system comprising:
a memory device including a plurality of memory cells coupled between a
plurality of word lines and a plurality of bit lines and a plurality of latches
coupled to the bit lines, and configured to
program input data stored in the latches into memory cells of a selected word line during a program operation, and
output, as information data, at least one or more data among first data stored in the latches and second data stored in the memory cells of the selected word line during a program suspend operation for suspending the
program operation; and
a controller configured to
repair the input data by performing a set logic operation on the information data from the memory device,
detect the number of cells whose threshold voltage level has reached a target level among the memory cells of the selected word line at
an execution moment of the program suspend operation, and
selectively apply a different type of the set logic operation according to the detected number of cells."
Independent claims 30 and 37 are added similarly to claim 21.
Applicant respectfully submits that the Examiner failed to establish a prima facie case of
obviousness because Miller and Gupta do not teach or suggest every element of the claimed
invention. "To establish a prima facie case of obviousness, the Board must, inter alia, show15
some objective teaching in the prior art or that knowledge generally available to one of ordinary skill in the art would lead that individual to combine the relevant teachings of the references." In re Thrift, 298 F.3d 1357 (Fed. Cir. 2002).
In the Office Action, the Examiner acknowledged that Miller fails to disclose repairing the input data by performing a set logic operation on at least one data among first data stored in the latches and second data stored in the memory cells of the selected word line during a program suspend operation, and further fails to disclose applying the set logic operation whose type is different according to an execution moment of the program suspend operation (Office Action - page 3). Accordingly, Miller merely discloses controlling an error masking operation based on an operation temperature and cannot be read as disclosing or suggesting the features of independent claims 21, 30, and 37. Since the Examiner relied on Gupta to cure this deficiency, the patentability of the pending claims hinges on whether Gupta teaches the claimed features.
Referring to paragraph [0009], Gupta discloses that "Various embodiments include a method for identifying a faulty memory die in a non-volatile memory system that comprises: commencing a programming operation of a multi-state block of a subject die, wherein the multi- state block includes a transfer data latch (XDL) and at least first and second data latches, and the programming operation comprises populating the transfer data latch (XDL) with a first set of data and transferring that first set of data to the first data latch, populating the transfer data latch (XDL) with a second set of data and transferring the second set of data to the second data latch, arranging the first and second sets of data in a format suitable for the multi-state block, and writing the first and second sets of data to the multi-state block; performing a program suspend and read operation after the transferring of the first set of data to the first data latch and before16 the populating of the transfer data latch (XDL) with the second set of data, thereby populating the transfer data latch (XDL) with a set of read data; comparing the read data contained in the transfer data latch (XDL) and the data contained in the first data latch; and if the data contained in the first data latch matches the read data, identifying the subject die as faulty."
Here, Gupta performs a read operation to verify the data currently stored in the latches when performing a program suspend. Based on this verification result (e.g., whether the data is valid or the die is faulty), Gupta determines a subsequent action (e.g., whether to identify a fault or reload data).
However, Gupta fails to disclose detecting the execution moment of the program suspend operation (e.g., the number of cells reaching a target level) and "selectively applying a different type of set logic operation according to the detection result" as recited by independent claims 21, 30, and 37.
In contrast, the added independent claim 21 specifically requires that the controller be configured to: 'detect the number of cells whose threshold voltage level has reached a target level among the memory cells of the selected word line at an execution moment of the program suspend operation, and selectively apply a different type of the set logic operation according to the detected number of cells.'
Gupta does not teach or suggest this specific technical solution. Gupta's operation is merely an integrity check involving a read operation after the program suspend operation to identify faults or data corruption. Gupta fails to disclose utilizing the detected number of cells (i.e., quantitative progress) to selectively apply a different type of set logic operation (e.g., first, second, third, or fourth logic operations) as explicitly recited in the added claim 21.
Accordingly, the combination of Miller and Gupta does not render the pending claims obvious.
For at least the foregoing reasons, it is respectfully submitted that a prima facie case of obviousness has not been established under 35 U.S.C. § 103 with respect to independent claim 21 and its dependent claims. Accordingly, the Examiner is respectfully requested to withdraw the rejection of independent claim 21 and its dependent claims and to allow these claims.
Independent claims 30 and 37 each recite features similar to those discussed above for claim 21. Thus, for at least the same reasons set forth earlier with respect to claim 21, the proposed combination of Miller and Gupta fails to teach all of the features of independent claims 30 and 37. Accordingly, it is respectfully submitted that a prima facie case of obviousness has not been established under 35 U.S.C. § 103 with respect to independent claims 30 and 37 and their respective dependent claims. The Examiner is respectfully requested to withdraw the rejection of independent claims 30 and 37 and their respective dependent claims and to allow these claims.
Newly Added Claim(s)
New claims 21-40 has been added to further define the scope of the invention. Features of added claim 21-40 are submitted to be allowable over the cited prior art of record.
The Examiner agrees claim 21 overcomes the prior art of Miller in view of Gupta.
The Examiner agrees Gupta fails to disclose detecting the execution moment of the program suspend operation (e.g., the number of cells reaching a target level) and "selectively applying a different type of set logic operation according to the detection result" as recited by independent claims 21, 30, and 37.
Miller in view of Gupta fail to teach independent claims 21, 30, and 37. However, Miller in view of Gupta in view of Di Vincenzo teach these claims as shown below. The previous prior art rejection is maintained.
Claims 22 – 29 which depend from claim 21, have been considered and rejected.
Claims 31 – 36 which depend from claim 30, have been considered and rejected.
Claims 38 – 40 which corresponds to claim 37 have been considered and rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21 – 40 are rejected under 35 U.S.C. 103 as being unpatentable over Miller (US 2024/0127901 A1) in view of Gupta (US 10832789 B1) in view of Di Vincenzo (US 2022/0230697 A1).
In regards to claim 21, Miller teaches:
A memory system comprising: a memory device including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of latches coupled to the bit lines (0015, The apparatus 100 may include an array of memory cells, such as memory array 150. The memory array 150 may include a plurality of banks (e.g., banks 0-15), and each bank may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells arranged at intersections of the word-lines and the bit lines); and configured to: program input data stored in the latches into memory cells of a selected word line during a program operation, and output, as information data, at least one or more data among first data stored in the latches (0026, latches can be configured to use the stored test results to configure on-die repair resources and/or to output the rest results); and a controller configured to: repair the input data by performing a set logic operation on the information data from the memory device (0010, test results stored in error latches can be used to perform on-die repairs of the memory array);
Miller fails to teach:
and second data stored in the memory cells of the selected word line during a program suspend operation for suspending the program operation;
However, Gupta teaches:
and second data stored in the memory cells of the selected word line during a program suspend operation for suspending the program operation (9, performing a program suspend and read operation after the transferring of the first set of data to the first data latch and before the populating of the transfer data latch (XDL) with the second set of data);
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the system of Miller which teaches a memory system including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of latches with the teaching of Gupta which teaches suspend and other logic operations in order to identify faulty memory die (Gupta: Abstract, Identifying a faulty memory die in a non-volatile memory storage system. Various methods include: commencing a programming operation of a multi-state block of a subject die).
Miller in view of Gupta fails to teach:
detect the number of cells whose threshold voltage level has reached a target level among the memory cells of the selected word line at an execution moment of the program suspend operation, and selectively apply a different type of the set logic operation according to the detected number of cells.
However, Di Vincenzo teaches:
detect the number of cells whose threshold voltage level has reached a target level among the memory cells of the selected word line at an execution moment of the program suspend operation, and selectively apply a different type of the set logic operation according to the detected number of cells. (0020-0021, and the number of memory cells in the logic state 1 is determined during the reference voltage ramp; the reference voltage is decreased until the count of cells in the logic states 1 is the same as the number of cells that were programmed to that logic state. Once the criterium is satisfied, the reading operation ends and data may be presented for output at the I/O terminals of the memory device; for example, when the number of cells read in the predefined logic states matches the expected number, an output is provided based on the determination of the logic states according to the last modified reference voltage.)
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the system of Miller which teaches a memory system including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of latches with the teaching of Di Vincenzo which teaches memory devices with counter-based reading capability and methods in order to identify faulty memory die (Di Vincenzo: 0003 & 0005 To store information, a component of the electronic device may write, or program, the state in the memory device. Improving reading reliability and performance of memory devices is desirable.)
In regards to claim 22, Miller in view of Gupta teaches the system of claim 21.
Miller teaches:
wherein the controller includes: first and second buffers; a suspend operation detector configured to detect the execution moment of the program suspend operation to produce a detection result and generate a suspend confirmation signal based on the detection result (0031 & 0047, The main memory 202 and/or the individual memory units 220 can also include other circuit components, such as multiplexers, decoders, buffers, read/write drivers, address registers, data out/data in registers, etc., for accessing and/or programming (e.g., writing) the memory cells; The process 400 begins at block 405, where the process detects the start of the mBIST operation 402 used to test a memory. The process 400 can detect the start of the mBIST operation 402 based on a change in value of a signal, such as BistEnF 325 illustrated in FIG. 3); and an operation executer configured to store the information data in the first buffer, repair the information data of the first buffer to generate the input data by performing the set logic operation corresponding to the suspend confirmation signal on the information data, and store, in the second buffer, temporary data generated by performing the set logic operation (0010, test results stored in error latches can be used to perform on-die repairs of the memory array. The mBIST mechanism can store the test results at designated locations).
In regards to claim 23, Miller in view of Gupta teaches the system of claim 22.
Miller teaches:
wherein the controller further includes a request generator configured to generate and transfer one request among a first request and a second request as the information data to the memory device in response to the suspend confirmation signal, the first request requesting for the first data, the second request requesting for both first data and second data (0034, The host device 208 can send various requests (in the form of, e.g., a packet or stream of packets) to the control circuitry 206. A request can include a command to read, write, erase, return information, and/or to perform a particular operation (e.g., a refresh operation, a TRIM operation, a precharge operation, an activate operation, a wear-leveling operation, a garbage collection operation, etc.)).
In regards to claim 24, Miller in view of Gupta teaches the system of claim 23.
Miller teaches:
wherein, when the second request is received from the controller, the memory device outputs, to the controller, the first data stored in the latches, reads the second data from the memory cells to store in the latches and outputs the second data in the latches to the controller (0026, The one or more error latches can be configured to use the stored test results to configure on-die repair resources and/or to output the rest results).
In regards to claim 25, Miller in view of Gupta teaches the system of claim 24.
Miller fails to teach:
wherein, when the first request is received from the controller, the memory device outputs, to the controller, the first data stored in the latches and does not read the second data from the memory cells.
However, Gupta teaches:
wherein, when the first request is received from the controller, the memory device outputs, to the controller, the first data stored in the latches and does not read the second data from the memory cells (9, performing a program suspend and read operation after the transferring of the first set of data to the first data latch and before the populating of the transfer data latch (XDL) with the second set of data);
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the system of Miller which teaches a memory system including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of latches with the teaching of Gupta which teaches suspend and other logic operations in order to identify faulty memory die (Gupta: Abstract, Identifying a faulty memory die in a non-volatile memory storage system. Various methods include: commencing a programming operation of a multi-state block of a subject die).
In regards to claim 26, Miller in view of Gupta teaches the system of claim 22.
Miller fails to teach:
wherein the operation executer determines that a first logic operation is required to be performed on the first data and a third logic operation is required to be performed on the second data in response to a first value of the suspend confirmation signal corresponding to a case where the number of the cells whose threshold voltage level has reached the target level among the memory cells of the selected word line is one or more and less than or equal to a predetermined number, determines that a second logic operation is required to be performed on the first data and the third logic operation is required to be performed on the second data in response to a second value of the suspend confirmation signal corresponding to a case where the number of the cells whose threshold voltage level has reached the target level among the memory cells of the selected word line exceeds the predetermined number, and determines that a fourth logic operation is required to be performed on the first data in response to a third value of the suspend confirmation signal corresponding to a case where there are no cells whose threshold voltage level has reached the target level among the memory cells of the selected word line.
However, Gupta teaches:
wherein the operation executer determines that a first logic operation is required to be performed on the first data and a third logic operation is required to be performed on the second data in response to a first value of the suspend confirmation signal corresponding to a case where the number of the cells whose threshold voltage level has reached the target level among the memory cells of the selected word line is one or more and less than or equal to a predetermined number, determines that a second logic operation is required to be performed on the first data and the third logic operation is required to be performed on the second data in response to a second value of the suspend confirmation signal corresponding to a case where the number of the cells whose threshold voltage level has reached the target level among the memory cells of the selected word line exceeds the predetermined number, and determines that a fourth logic operation is required to be performed on the first data in response to a third value of the suspend confirmation signal corresponding to a case where there are no cells whose threshold voltage level has reached the target level among the memory cells of the selected word line. (3, 9, & 73, As a result, bit-value data can be programmed onto and erased from the memory cell by changing the level of charge on a floating gate in order to change the threshold voltage characteristic of the transistor. suspend and read command Sense module 480 also includes a bit line latch 482 that is used to set a voltage condition on the connected bit line. For example, a predetermined state latched in bit line latch 482 will result in the connected bit line being pulled to a state designating program inhibit (e.g., 1.5-3 V). As an example, a flag=0 can inhibit programming, while flag=1 does not inhibit programming.)
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the system of Miller which teaches a memory system including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of latches with the teaching of Gupta which teaches suspend and other logic operations in order to identify faulty memory die (Gupta: Abstract, Identifying a faulty memory die in a non-volatile memory storage system. Various methods include: commencing a programming operation of a multi-state block of a subject die).
In regards to claim 27, Miller in view of Gupta teaches the system of claim 26.
Miller teaches:
wherein the operation executer allocates, in the first buffer, two spaces for storing the first data and the second data in response to the suspend confirmation signal, and performs: a first repair operation for repairing the first data of the first buffer to generate intermediate repair data by storing, in the first buffer, the first and second data input from the memory device and then performing one logic operation on the first data stored in the first buffer, the one logic operation corresponding to the suspend confirmation signal among a first logic operation and a second logic operation, and a second repair operation for repairing the intermediate repair data of the first buffer to generate the input data by performing a third logic operation on the intermediate repair data and the second data after the first repair operation is completed. (0026, The one or more error latches can be configured to use the stored test results to configure on- die repair resources and/or to output the rest results).
In regards to claim 28, Miller in view of Gupta teaches the system of claim 26.
Miller teaches:
wherein the operation executer allocates, in the first buffer, one space for storing the first data in response to the suspend confirmation signal, stores, in the first buffer, the first data input from the memory device, and performs a fourth logic operation on the first data to repair the first data of the first buffer to generate the input data. (0031 & 0029, The main memory 202 and/or the individual memory units 220 can also include other circuit components, such as multiplexers, decoders, buffers, read/write drivers, address registers, data out/data in registers, etc., for accessing and/or programming (e.g., writing) the memory cells. The control circuitry 206 may include aspects of various components described with reference to FIG. 1. For example, the control circuitry 206 may include aspects of the command/address input circuit 105, the address decoder 110, and the command decoder 115, among others).
In regards to claim 29, Miller in view of Gupta teaches the system of claim 22.
Miller teaches:
wherein the suspend operation detector detects the number of cells whose threshold voltage level has reached a target level among the memory cells of the selected word line to produce the detection result, and generates the suspend confirmation signal based on the detection result (0051, At block 425, the process 400 sets a flag indicating that the threshold temperature was exceeded by the apparatus during the mBIST operation. The flag can be used, for example, by a customer using the apparatus to let them know that the apparatus hit an operating temperature limit.).
In regards to claim 9, Miller in view of Gupta teaches the system of claim 8.
Miller teaches:
wherein the operation executer determines that the fourth logic operation is required to be performed on the first data in response to the suspend confirmation signal corresponding to a case where there are no cells whose threshold voltage level has reached the target level among the memory cells of the selected word line, determines that the first logic operation is required to be performed on the first data and the third logic operation is required to be performed on the second data in response to the suspend confirmation signal corresponding to a case where the number of the cells whose threshold voltage level has reached the target level among the memory cells of the selected word line is one or more and less than or equal to a predetermined number, and determines that the second logic operation is required to be performed on the first data and the third logic operation is required to be performed on the second data in response to the suspend confirmation signal corresponding to a case where the number of the cells whose threshold voltage level has reached the target level among the memory cells of the selected word line exceeds the predetermined number. (0051 & 0011, At block 425, the process 400 sets a flag indicating that the threshold temperature was exceeded by the apparatus during the mBIST operation. The flag can be used, for example, by a customer using the apparatus to let them know that the apparatus hit an operating temperature limit. mBIST, may be performed while the apparatus is subjected to various conditions).
In regards to claim 30, Miller teaches:
A memory device comprising: a memory cell array including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines (0015, The apparatus 100 may include an array of memory cells, such as memory array 150. The memory array 150 may include a plurality of banks (e.g., banks 0-15), and each bank may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells arranged at intersections of the word-lines and the bit lines); a page buffer including a plurality of first latches corresponding to the bit lines, respectively; and a control logic configured to: program input data stored in the first latches into memory cells of a selected word line during a program operation (0024, Input buffers included in the clock input circuit 120 can receive the external clock signals. an input buffer can receive the clock/enable signals); repair the input data by performing a set logic operation on at least one or more data among first data and second data (0010, test results stored in error latches can be used to perform on-die repairs of the memory array);
Miller fails to teach:
during a program suspend operation for suspending the program operation, the first data stored in the first latches, the second data stored in the memory cells of the selected word line,
However, Gupta teaches:
during a program suspend operation for suspending the program operation, the first data stored in the first latches, the second data stored in the memory cells of the selected word line, (59, in a memory device of the SLC-type in which one bit of data is stored in each memory cell 10; in a memory device of the MLC-type in which two bits of data are stored in each memory cell 10);
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the system of Miller which teaches a memory device including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of latches with the teaching of Gupta which teaches suspend and other logic operations in order to identify faulty memory die (Gupta: Abstract, Identifying a faulty memory die in a non-volatile memory storage system. Various methods include: commencing a programming operation of a multi-state block of a subject die).
Miller in view of Gupta fails to teach:
detect the number of cells whose threshold voltage level has reached a target level among the memory cells of the selected word line at an execution moment of the program suspend operation, and selectively apply a different type of the set logic operation according to the detected number of cells.
However, Di Vincenzo teaches:
detect the number of cells whose threshold voltage level has reached a target level among the memory cells of the selected word line at an execution moment of the program suspend operation, and selectively apply a different type of the set logic operation according to the detected number of cells. (0020-0021, and the number of memory cells in the logic state 1 is determined during the reference voltage ramp; the reference voltage is decreased until the count of cells in the logic states 1 is the same as the number of cells that were programmed to that logic state. Once the criterium is satisfied, the reading operation ends and data may be presented for output at the I/O terminals of the memory device; for example, when the number of cells read in the predefined logic states matches the expected number, an output is provided based on the determination of the logic states according to the last modified reference voltage.)
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the system of Miller which teaches a memory system including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of latches with the teaching of Di Vincenzo which teaches memory devices with counter-based reading capability and methods in order to identify faulty memory die (Di Vincenzo: 0003 & 0005 To store information, a component of the electronic device may write, or program, the state in the memory device. Improving reading reliability and performance of memory devices is desirable.)
In regards to claim 31, Miller in view of Gupta teaches the memory device of claim 30.
Miller fails to teach:
wherein the page buffer further includes a plurality of second latches and a plurality of third latches respectively corresponding to the bit lines, and the control logic includes: a suspend operation detector configured to detect the execution moment of the program suspend operation to produce a detection result and generate a suspend confirmation signal based on the detection result; and an operation executer configured to read the second data from the memory cells of the selected word line and store the read second data in the second latches, perform the set logic operation corresponding to the suspend confirmation signal on the first and second data stored in the first and second latches, respectively, and store, in the third latches, temporary data generated by performing the set logic operation, when the set logic operation is required to be performed on both first data and second data according to the suspend confirmation signal.
However, Gupta teaches:
wherein the page buffer further includes a plurality of second latches and a plurality of third latches respectively corresponding to the bit lines, and the control logic includes: a suspend operation detector configured to detect the execution moment of the program suspend operation to produce a detection result and generate a suspend confirmation signal based on the detection result; and an operation executer configured to read the second data from the memory cells of the selected word line and store the read second data in the second latches, perform the set logic operation corresponding to the suspend confirmation signal on the first and second data stored in the first and second latches, respectively, and store, in the third latches, temporary data generated by performing the set logic operation, when the set logic operation is required to be performed on both first data and second data according to the suspend confirmation signal. (6 & 9, Accordingly, a plurality of data latches may be employed in a flash memory system that programs data to single-state memory cells and, in some cases, to multi-state memory cells. performing a program suspend and read operation after the transferring of the first set of data to the first data latch and before the populating of the transfer data latch (XDL) with the second set of data)
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the system of Miller which teaches a memory system including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of latches with the teaching of Gupta which teaches suspend and other logic operations in order to identify faulty memory die (Gupta: Abstract, Identifying a faulty memory die in a non-volatile memory storage system. Various methods include: commencing a programming operation of a multi-state block of a subject die).
In regards to claim 32, Miller in view of Gupta teaches the memory device of claim 31.
Miller teaches:
wherein the operation executer determines that a first logic operation is required to be performed on the first data and a third logic operation is required to be performed on the second data in response to a first value of the suspend confirmation signal corresponding to a case; determines that a second logic operation is required to be performed on the first data and the third logic operation is required to be performed on the second data in response to a second value of the suspend confirmation signal corresponding to a case where the number of the cells whose threshold voltage level has reached the target level among the memory cells of the selected word line exceeds the predetermined number, and determines that a fourth logic operation is required to be performed on the first data in response to a third value of the suspend confirmation signal corresponding to a case (0047, The process 400 begins at block 405, where the process detects the start of the mBIST operation 402 used to test a memory. The process 400 can detect the start of the mBIST operation 402 based on a change in value of a signal, such as BistEnF 325 illustrated in FIG. 3).
Miller fails to teach:
where the number of the cells whose threshold voltage level has reached the target level among the memory cells of the selected word line is one or more and less than or equal to a predetermined number; where there are no cells whose threshold voltage level has reached the target level among the memory cells of the selected word line.
However, Gupta teaches:
where the number of the cells whose threshold voltage level has reached the target level among the memory cells of the selected word line is one or more and less than or equal to a predetermined number; where there are no cells whose threshold voltage level has reached the target level among the memory cells of the selected word line. (5, the threshold voltage window of a cell may be partitioned into four distinct voltage ranges (or states), wherein each range is assigned a bit value equal to, for example, “11,” “10,” “01,” and “00.”)
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the system of Miller which teaches a memory system including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of latches with the teaching of Gupta which teaches suspend and other logic operations in order to identify faulty memory die (Gupta: Abstract, Identifying a faulty memory die in a non-volatile memory storage system. Various methods include: commencing a programming operation of a multi-state block of a subject die).
In regards to claim 33, Miller in view of Gupta teaches the memory device of claim 32.
Miller teaches:
wherein, when the set logic operation is required to be performed on the first data according to the third value of the suspend confirmation signal, the operation executer performs the set logic operation corresponding to the third value of the suspend confirmation signal on the first data stored in the first latches without reading the second data from the memory cells of the selected word line. (0047, The process 400 begins at block 405, where the process detects the start of the mBIST operation 402 used to test a memory. The process 400 can detect the start of the mBIST operation 402 based on a change in value of a signal, such as BistEnF 325 illustrated in FIG. 3).
In regards to claim 34, Miller in view of Gupta teaches the memory device of claim 11.
Miller teaches:
wherein, when the set logic operation is required to be performed on both first data and second data according to the suspend confirmation signal, the operation executer performs a first repair operation of repairing the first data of the first latches to generate intermediate repair data by performing one logic operation on the first data stored in the first latches (0010, test results stored in error latches can be used to perform on-die repairs of the memory array);
Miller fails to teach:
the one logic operation corresponding to the suspend confirmation signal among the first logic operation and the second logic operation, and a second repair operation of repairing the intermediate repair data of the first latches to generate the input data by performing a third logic operation on the intermediate repair data stored in the first latches and the second data stored in the second latches, after the first repair operation is completed.
However, Gupta teaches:
the one logic operation corresponding to the suspend confirmation signal among the first logic operation and the second logic operation, and a second repair operation of repairing the intermediate repair data of the first latches to generate the input data by performing a third logic operation on the intermediate repair data stored in the first latches and the second data stored in the second latches, after the first repair operation is completed (59, in a memory device of the SLC-type in which one bit of data is stored in each memory cell 10; in a memory device of the MLC-type in which two bits of data are stored in each memory cell 10).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the system of Miller which teaches a memory system including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of latches with the teaching of Gupta which teaches suspend and other logic operations in order to identify faulty memory die (Gupta: Abstract, Identifying a faulty memory die in a non-volatile memory storage system. Various methods include: commencing a programming operation of a multi-state block of a subject die).
In regards to claim 35, Miller in view of Gupta teaches the memory device of claim 32.
Miller fails to teach:
wherein, when the set logic operation is required to be performed on the first data according to the suspend confirmation signal, the operation executer repairs the first data of the first latches to generate the input data by performing a fourth logic operation on the first data stored in the first latches.
However, Gupta teaches:
wherein, when the set logic operation is required to be performed on the first data according to the suspend confirmation signal, the operation executer repairs the first data of the first latches to generate the input data by performing a fourth logic operation on the first data stored in the first latches (9, performing a program suspend and read operation after the transferring of the first set of data to the first data latch and before the populating of the transfer data latch (XDL) with the second set of data, thereby populating the transfer data latch (XDL) with a set of read data; comparing the read data contained in the transfer data latch (XDL) and the data contained in the first data latch);
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the system of Miller which teaches a memory system including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of latches with the teaching of Gupta which teaches suspend and other logic operations in order to identify faulty memory die (Gupta: Abstract, Identifying a faulty memory die in a non-volatile memory storage system. Various methods include: commencing a programming operation of a multi-state block of a subject die).
In regards to claim 36, Miller in view of Gupta teaches the memory device of claim 31.
Miller fails to teach:
wherein the suspend operation detector detects the number of cells whose threshold voltage level has reached a target level among the memory cells of the selected word line to produce the detection result and generates the suspend confirmation signal based on the detection result.
However, Gupta teaches:
wherein the suspend operation detector detects the number of cells whose threshold voltage level has reached a target level among the memory cells of the selected word line to produce the detection result and generates the suspend confirmation signal based on the detection result (3, the minimum amount of voltage that must be applied to the control gate before the transistor is activated to permit conduction between its source and drain is determined by the level of charge retained on the floating gate. As a result, bit-value data can be programmed onto and erased from the memory cell by changing the level of charge on a floating gate in order to change the threshold voltage characteristic of the transistor).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the system of Miller which teaches a memory system including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of latches with the teaching of Gupta which teaches suspend and other logic operations in order to identify faulty memory die (Gupta: Abstract, Identifying a faulty memory die in a non-volatile memory storage system. Various methods include: commencing a programming operation of a multi-state block of a subject die).
In regards to claim 37, Miller teaches:
A method for operating a memory device, the method comprising: performing a program operation of programming input data stored in a page buffer into a memory cell selected as a program target (0024, Input buffers included in the clock input circuit 120 can receive the external clock signals. an input buffer can receive the clock/enable signals); repairing the input data (0010, test results stored in error latches can be used to perform on-die repairs of the memory array);
Miller fails to teach:
at an execution moment of a program suspend operation after the program operation; during the program suspend operation.
However, Gupta teaches:
at an execution moment of a program suspend operation after the program operation; during the program suspend operation. (9, performing a program suspend and read operation after the transferring of the first set of data to the first data latch and before the populating of the transfer data latch (XDL) with the second set of data);
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the system of Miller which teaches a memory system including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of latches with the teaching of Gupta which teaches suspend and other logic operations in order to identify faulty memory die (Gupta: Abstract, Identifying a faulty memory die in a non-volatile memory storage system. Various methods include: commencing a programming operation of a multi-state block of a subject die).
Miller in view of Gupta fails to teach:
detecting the number of cells whose threshold voltage level has reached a target level among the selected memory cells; by selectively applying a different type of a set logic operation on at least one data among first data stored in the page buffer and second data stored in the selected memory cells according to the detected number of cells;
However, Di Vincenzo teaches:
detecting the number of cells whose threshold voltage level has reached a target level among the selected memory cells; by selectively applying a different type of a set logic operation on at least one data among first data stored in the page buffer and second data stored in the selected memory cells according to the detected number of cells; (0020-0021, and the number of memory cells in the logic state 1 is determined during the reference voltage ramp; the reference voltage is decreased until the count of cells in the logic states 1 is the same as the number of cells that were programmed to that logic state. Once the criterium is satisfied, the reading operation ends and data may be presented for output at the I/O terminals of the memory device; for example, when the number of cells read in the predefined logic states matches the expected number, an output is provided based on the determination of the logic states according to the last modified reference voltage.)
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the system of Miller which teaches a memory system including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of latches with the teaching of Di Vincenzo which teaches memory devices with counter-based reading capability and methods in order to identify faulty memory die (Di Vincenzo: 0003 & 0005 To store information, a component of the electronic device may write, or program, the state in the memory device. Improving reading reliability and performance of memory devices is desirable.)
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the system of Miller which teaches a method for operating a memory system with the teaching of Gupta which teaches suspend and other logic operations in order to identify faulty memory die (Gupta: Abstract, Identifying a faulty memory die in a non-volatile memory storage system. Various methods include: commencing a programming operation of a multi-state block of a subject die).
In regards to claim 38, Miller in view of Gupta teaches the method of claim 38.
Miller fails to teach:
wherein repairing the input data further includes: determining that a first logic operation is required to be performed on the first data and a third logic operation is required to be performed on the second data, when the execution moment of the program suspend operation is detected in a program operation of a state in which the number of the cells whose threshold voltage level has reached the target level among the selected memory cells is one or more and less than or equal to a predetermined number; determining that a second logic operation is required to be performed on the first data and the third logic operation is required to be performed on the second data, when the execution moment of the program suspend operation is detected in a program operation of a state in which the number of the cells whose threshold voltage level has reached the target level among the selected memory cells exceeds the predetermined number; and determining that a fourth logic operation is required to be performed on the first data, when the execution moment of the program suspend operation is detected in a program operation of a state in which there are no cells whose threshold voltage level has reached the target level among the selected memory cells.
However, Gupta teaches:
wherein repairing the input data further includes: determining that a first logic operation is required to be performed on the first data and a third logic operation is required to be performed on the second data, when the execution moment of the program suspend operation is detected in a program operation of a state in which the number of the cells whose threshold voltage level has reached the target level among the selected memory cells is one or more and less than or equal to a predetermined number; determining that a second logic operation is required to be performed on the first data and the third logic operation is required to be performed on the second data, when the execution moment of the program suspend operation is detected in a program operation of a state in which the number of the cells whose threshold voltage level has reached the target level among the selected memory cells exceeds the predetermined number; and determining that a fourth logic operation is required to be performed on the first data, when the execution moment of the program suspend operation is detected in a program operation of a state in which there are no cells whose threshold voltage level has reached the target level among the selected memory cells. (3, 9, & 73, As a result, bit-value data can be programmed onto and erased from the memory cell by changing the level of charge on a floating gate in order to change the threshold voltage characteristic of the transistor. suspend and read command Sense module 480 also includes a bit line latch 482 that is used to set a voltage condition on the connected bit line. For example, a predetermined state latched in bit line latch 482 will result in the connected bit line being pulled to a state designating program inhibit (e.g., 1.5-3 V). As an example, a flag=0 can inhibit programming, while flag=1 does not inhibit programming.)
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to modify the system of Miller which teaches a memory system including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of latches with the teaching of Gupta which teaches suspend and other logic operations in order to identify faulty memory die (Gupta: Abstract, Identifying a faulty memory die in a non-volatile memory storage system. Various methods include: commencing a programming operation of a multi-state block of a subject die).
In regards to claim 39, Miller in view of Gupta teaches the method of claim 38.
Miller teaches:
wherein, when the set logic operation is required to be performed on both first data and second data, the repairing of the input data includes: performing a first repair operation of repairing the first data to generate intermediate repair data by performing one logic operation among the first logic operation and the second logic operation on the first data stored in the page buffer; and performing a second repair operation of repairing the intermediate repair data to generate the input data by performing the third logic operation on the intermediate repair data stored in the page buffer and the second data stored in the selected memory cells after the first repair operation (0026, The one or more error latches can be configured to use the stored test results to configure on-die repair resources and/or to output the rest results (e.g., by providing the test results via terminals of the apparatus 100 and/or by writing to a status register the contents of which are accessible via terminals of the apparatus)).
In regards to claim 40, Miller in view of Gupta teaches the method of claim 38.
Miller teaches:
wherein, when the set logic operation is required to be performed on the first data, repairing the input data further includes performing a third repair operation of repairing the input data by performing the fourth logic operation on the first data stored in the page buffer. (0036 & 0026, The temperature-based masking circuit 300 can include logic devices (e.g., buffers, delays, flip-flops, NOT gates, NAND gates, NOR gates, XNOR gates, AND gates, OR gates, XOR gates, or a combination thereof) and circuits configured to control error masking during mBIST operation. The one or more error latches can be configured to use the stored test results to configure on-die repair resources and/or to output the rest results (e.g., by providing the test results via terminals of the apparatus 100 and/or by writing to a status register the contents of which are accessible via terminals of the apparatus)
Prior Art Made of Record
The prior art mode of record and not relied upon is considered pertinent to
Applicant’s disclosure:
AKAMINE (US 2017/0221569 A1): A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again.
Arai (US 2020/0227132 A1): A memory chip includes a memory cell array and first circuitry. The first circuitry executes a first operation of reading data from a target area of the memory cell array, using a parameter. After the first operation, the first circuitry executes a second operation of changing a set value of the parameter to read the data.
Conclusion
Applicant's arguments filed 03/11/2026 regarding the prior art rejections of Claims 21 – 40 have been fully considered and are persuasive.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner
should be directed to VICTOR PERRY whose telephone number is (571)272-6319. The examiner can
normally be reached Monday - Friday 8:00 - 5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor,
Mark Featherstone can be reached on (571) 270-3750. The fax phone number for the organization
where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from
Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit
https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and
https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional
questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like
assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/V.P./Examiner, Art Unit 2111
/GUERRIER MERANT/Primary Examiner, Art Unit 2111 5/29/2026
Prosecution Insights