Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, and 3-8 are rejected under 35 U.S.C. 103 as being unpatentable over Ohara et al., US 20160210892 A1 (hereinafter “Ohara”), in view of Wu et al., CN 117542286 A (hereinafter “Wu”).
Regarding claim 1, Ohara discloses a display panel (fig. 2, paragraph 130, display device 1), comprising:
a plurality of emission circuits (fig. 10, plurality of emission unit circuit 40(k-1) ~ 40(k+1) in emission driver 400, paragraph 155, “The emission driver 400 is composed of a shift register 4 of n stages including n unit circuits 40. Note that FIG. 10 Shows unit circuits 40 (k−1) to 40 (k+1) of a (k−1) th stage to a (k+1)th stage. Here, k is an even number between 2 and (n−2), inclusive”), receiving a plurality of clock signals (fig. 10, paragraph 156-158, CK1 and CK2, “Two-phase clock signals (a first clock signal CK1 and a second clock signal CK2) such as those shown in FIG. 11 are provided as an emission clock signal ECK to the shift register 4 composing the emission driver 400”) to provide a plurality of emission signals (fig. 10, emission signals GGem(k-1) ~ GGem(k+1), paragraphs 151, 152, each GGem signal corresponds to emission signal for one stage of plurality of row/stage);
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a plurality of emission control circuits, respectively receiving one of the emission signals (fig. 1, 8, 9, paragraphs 151-152, emission signal input switching circuit with associated Tem1~Tem3 corresponding to each row/stage, circuits associated with EM1~EM3(1) to EM1~EM3(n) in fig. 8, each receiving one of GGem signal), and receiving a plurality of emission control signals (fig. 1, 8, 9, paragraphs 141, 150, 151, plurality of emission control signals SEL1~SEL3) to provide a plurality of pixel emission signals based on the received emission signal and the emission control signals (paragraph 151, “the emission signal input switching circuit 600 brings one of the three selection signals SEL1, SEL2, and SEL3 to a high level every subframe. When the selection signal SEL1 is at a high level, the transistor Tem1 goes into an on state, and a light-emission enable signal GGem outputted from the emission driver 400 is supplied to the first emission line EM1. When the selection signal SEL2 is at a high level, the transistor Tem2 goes into an on state, and the light-emission enable signal GGem outputted from the emission driver 400 is supplied to the second emission line EM2. When the selection signal SEL3 is at a high level, the transistor Tem3 goes into an on state, and the light-emission enable signal GGem outputted from the emission driver 400 is supplied to the third emission line EM3”);
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a plurality of pixel circuits, arranged in an array (fig. 3, paragraph 132, “In the display unit 500, as shown in FIG. 3, m data lines DL(1) to DL(m) and n scanning signal lines SL(1) to SL(n) are disposed so as to intersect each other. Pixel circuits 50 are provided at the respective intersections of the data lines DL(1) to DL(m) and the scanning signal lines SL(1) to SL(n). That is, in the display unit 500, the pixel circuits 50 are arranged in a matrix form so as to form a plurality of rows (n rows) and a plurality of columns (m columns)”);
a plurality of emission control lines (fig. 9, control lines corresponding to EM1~EM3 for each row/stage), respectively coupled to one of the emission control circuits and pixel circuits of a same color among the pixel circuits in a row to transmit a corresponding one of the pixel emission signals to the coupled pixel circuits (fig. 7, 9, red pixel coupled to emission control line corresponding to nodes T3 and EM1, green pixel coupled to emission control line corresponding to node T4 and EM2, blue pixels coupled to emission control line corresponding to node T5 and EM3).
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Ohara does not disclose in particular the emission signal received is based on a previous emission signal, that the plurality of pixel emission signals provided is based on the previous emission signal.
In similar field of endeavor of controlling emission of pixels in display device, Wu discloses that activation of emission signal of one stage/row may be based on previous emission signal (fig. 9, paragraph 81, “FIG. 9 is another timing diagram of the light emitting control signals and the clock control signals provided by the shift register unit in FIG. 7. In this embodiment, the initial shift signal VSTV provided by the initial shift signal input terminal STV is used as the input signal of the first stage shift register unit. the light emitting control signal output end of the shift register unit of the first stage not only provides the light emitting control signal to the corresponding first sub-pixel row, but also is connected to the shift register unit of the second stage as the input control signal, the light emitting control signal output end of the shift register unit of the second stage not only provides the light emitting control signal to the corresponding second sub-pixel row, but also is connected to the shift register unit of the third stage as the input control signal, by parity of reasoning, The light emitting control signal output end of the shift register unit of the last stage not only provides the light emitting control signal to the sub-pixel row corresponding to the shift register unit of the last stage, but also is connected to the shift register unit of the current stage as the input control signal. In FIG. 9, the light emission control signal corresponding to 301E (n-2) is the input control signal of the shift register unit of the previous stage, and the light emission control signal corresponding to 301E (n-1) is the input control signal of the shift register unit of the current stage; The luminescence control signal corresponding to 301E (n-1) is the input control signal of the shift register unit of the previous stage, and the luminescence control signal corresponding to 301E (n) is the input control signal of the shift register unit of the current stage.”).
It would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of cascading emission signals by controlling emission signal of next stage based on previous emission signal, such as disclosed by Wu, into the device of Ohara, to constitute wherein the emission signal received is based on a previous emission signal, that the plurality of pixel emission signals provided is based on the previous emission signal, such is incorporation of known concept into a known device to yield predictable result, the result would have been predictable and would allow control of display device to sequentially activate different rows of pixels in order to display desired image.
Regarding claims 3 and 4, Ohara in view of Wu discloses (from claim 3) the display panel according to claim 1, wherein the emission control signals are a low-frequency signal, and (from claim 4) wherein a number of transitions of the low-frequency signal during a single screen period is less than or equal to 1 (fig. 15, paragraph 171, note that screen period may be interpreted as any time period wherein the screen is in operation, and emission control signals may remain inactive, i.e. low-frequency during one period, for example, SEL1 made no transitions during period SF2 and SF3).
Regarding claims 5 and 6, Ohara in view of Wu discloses (from claim 5) the display panel according to claim 1, wherein the emission control signals are a high-frequency signal and (from claim 6) wherein a number of transitions of the high-frequency signal during a single screen period is greater than or equal to 2 (fig. 15, paragraph 171, note that screen period may be interpreted as any time period wherein the screen is in operation, and emission control signals may transition from low to high, and high to low, i.e. high-frequency during one period, for example, SEL1 made two transitions during and after SF1).
Regarding claim 7, Ohara in view of Wu discloses the display panel according to claim 1, further comprising a plurality of clock signal lines and a plurality of control signal lines, wherein the clock signal lines transmit the clock signals (fig. 10, signal lines corresponding to clock signals CK1 and CK2 as clock signal lines, paragraphs 156-158), and the control signal lines transmit the emission control signals (fig. 1, 8, 9, paragraphs 141, 150, 151, plurality of emission control signals lines corresponding to signals SEL1~SEL3).
Regarding claim 8, Ohara in view of Wu discloses the display panel according to claim 1, wherein the pixel circuits comprise a plurality of red light emitting diode pixel circuits, a plurality of green light emitting diode pixel circuits, and a plurality of blue light emitting diode pixel circuits (fig. 3, 7, paragraphs 132, 142, plurality of pixel circuits comprises red, green and blue light emitting diode circuits, “The organic EL element OLED(R) functions as an electro-optical element that emits red light. The organic EL element OLED(G) functions as an electro-optical element that emits green light. The organic EL element OLED(B) functions as an electro-optical element that emits blue light”).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ohara in view of Wu, as in claim 1 above, and in further view of Lee et al., US 20250218350 A1 (hereinafter “Lee”).
Regarding claim 9, Ohara in view of Wu discloses the display panel according to claim 1.
Ohara does not specifically disclose wherein a pulse width of at least one of the emission control signals is different from pulse widths of the other emission control signals.
In similar field of endeavor of emission control of pixels, Lee discloses the concept of individually controlling pulse width of emission control signals for pixels of different colors to accommodate for different luminous efficiency (paragraphs 14, 15, 100, “The pulse of the first EM signal EM_R is applied to the first switch element M1 of the red sub-pixel to control the emission time of the red sub-pixel. The pulse of the second EM signal EM_G is applied to the first switch element M1 of the green sub-pixel to control the emission time of the green sub-pixel. The pulse of the third EM signal EM_B is applied to the first switch element M1 of the blue sub-pixel to control the emission time of the blue sub-pixel. The pulse widths of the second EM signal EM_G and the third EM signal EM_B are different from each other. The pulse width may be interpreted as the duration of the gate-on voltage. For example, within one frame period, a pulse width W1 of the first EM signal EM_R may be smaller than pulse widths W2 and W3 of the second and third EM signals EM_G and EM_B. The pulse width W2 of the second EM signal EM_G may be larger than the pulse widths W1 and W3 of the first and third EM signals EM_R and EM_B. The pulse width W3 of the third EM signal EM_B may be larger than the pulse width W1 of the first EM signal EM_R and smaller than the pulse width W2 of the second EM signal EM_G. In this case, in each frame period, among the red sub-pixel, the green sub-pixel, and the blue sub-pixel, the emission time of the red sub-pixel may be the shortest and the emission time of the green sub-pixel may be the longest”).
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Both Ohara in view of Wu and Lee individually controlling emission of different colored pixels, it would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of controlling emission signal width for different colors, such as disclosed by Lee, into the display device of Ohara, to constitute wherein a pulse width of at least one of the emission control signals is different from pulse widths of the other emission control signals, such is incorporation of a known technique into a known device to yield predictable result, the result would have been predictable and would allow pixel emission to accommodate different luminous efficiencies of different color pixels while achieving the same intended function of allowing emission of pixel circuits to be individually controlled.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ohara in view of Wu, as in claim 1 above, and in further view of Lee et al., US 20210206841 A1 (hereinafter “Lee’841”).
Regarding claim 10, Ohara in view of Wu discloses the display panel according to claim 1.
Ohara in view of Wu does not disclose the specific structure of pixel circuit, wherein the pixel circuits respectively comprise:
a light emitting diode, having an anode and a cathode receiving a system low voltage;
a seventh transistor, having a first terminal receiving an initial voltage, a control terminal receiving a scan signal, and a second terminal;
an eighth transistor, having a first terminal, a control terminal receiving the scan signal, and a second terminal receiving a data voltage;
a seventh capacitor, coupled between the second terminal of the seventh transistor and the first terminal of the eighth transistor;
a ninth transistor, having a first terminal receiving a system high voltage, a control terminal receiving the corresponding one of the pixel emission signals, and a second terminal coupled to the second terminal of the seventh transistor;
a tenth transistor, having a first terminal coupled to the second terminal of the seventh transistor, a control terminal coupled to the first terminal of the eighth transistor, and a second terminal; and
an eleventh transistor, having a first terminal coupled to the second terminal of the tenth transistor, a control terminal receiving the corresponding one of the pixel emission signals, and a second terminal coupled to the anode of the light emitting diode.
In similar field of endeavor of pixel circuit, Lee’841 discloses display device with plurality of pixel circuits (paragraph 10), wherein the pixel circuits respectively comprise (fig. 9A, paragraph 171, see annotated figure below):
a light emitting diode (fig. 9A, LED), having an anode and a cathode receiving a system low voltage (fig. 9A, VSS);
a seventh transistor (fig. 9A, T5), having a first terminal receiving an initial voltage (fig. 9A, Vini), a control terminal receiving a scan signal (fig. 9A, SCAN), and a second terminal;
an eighth transistor (fig. 9A, T1), having a first terminal, a control terminal receiving the scan signal (fig. 9A, SCAN), and a second terminal receiving a data voltage (fig. 9A, Vdata);
a seventh capacitor (fig. 9A, Cst), coupled between the second terminal of the seventh transistor (fig. 9A, T5) and the first terminal of the eighth transistor (fig. 9A, T1, Cst coupled between T5 and T1 via T2 and T3);
a ninth transistor (fig. 9A, T3), having a first terminal receiving a system high voltage (fig. 9A, VDD), a control terminal receiving the corresponding one of the pixel emission signals (fig. 9A, EM), and a second terminal coupled to the second terminal of the seventh transistor (fig. 9A, T5, coupled to T3 via T4 and DT);
a tenth transistor (fig. 9A, DT), having a first terminal coupled to the second terminal of the seventh transistor (fig. 9A, T5, coupled to DT via T4), a control terminal coupled to the first terminal of the eighth transistor (fig. 9A, T1, coupled to DT via Cst, T3), and a second terminal; and
an eleventh transistor (fig. 9A, T4), having a first terminal coupled to the second terminal of the tenth transistor (fig. 9A, DT), a control terminal receiving the corresponding one of the pixel emission signals (fig. 9A, EM), and a second terminal coupled to the anode of the light emitting diode (fig. 9A, LED).
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Both Ohara in view of Wu and Lee’841 discloses pixel circuit with light emitting diode similarly controlled via scan, data, and emission signals, it would have been obvious to one of ordinary skill in the art at the time of filing to incorporate the concept of pixel circuits as taught in Lee’841, into the display device of Ohara, to constitute wherein the pixel circuits respectively comprise: a light emitting diode, having an anode and a cathode receiving a system low voltage; a seventh transistor, having a first terminal receiving an initial voltage, a control terminal receiving a scan signal, and a second terminal; an eighth transistor, having a first terminal, a control terminal receiving the scan signal, and a second terminal receiving a data voltage; a seventh capacitor, coupled between the second terminal of the seventh transistor and the first terminal of the eighth transistor; a ninth transistor, having a first terminal receiving a system high voltage, a control terminal receiving the corresponding one of the pixel emission signals, and a second terminal coupled to the second terminal of the seventh transistor; a tenth transistor, having a first terminal coupled to the second terminal of the seventh transistor, a control terminal coupled to the first terminal of the eighth transistor, and a second terminal; and an eleventh transistor, having a first terminal coupled to the second terminal of the tenth transistor, a control terminal receiving the corresponding one of the pixel emission signals, and a second terminal coupled to the anode of the light emitting diode, such is incorporation of a known technique into a known device to yield predictable result, the result would have been predictable and would allow pixel circuit to be initialized with initialization voltage during scanning of pixel row while achieving the same intended function of allowing emission of pixel circuits to be individually controlled.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEIJIE SHEN whose telephone number is (571)272-5522. The examiner can normally be reached Monday - Friday 10AM - 6PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at 5712727603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PEIJIE SHEN/Examiner, Art Unit 2622
/PATRICK N EDOUARD/Supervisory Patent Examiner, Art Unit 2622