DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 9, 11, 13-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zheng (US 20140254779 A1).
In regard to Claim 1:
Zheng discloses a differential amplifier, figure 10, comprising: a main amplifier (900) configured to generate at least one pair of differential output signals (Vout + , Vout -) by amplifying at least one pair of differential input signals (Vin+, Vin-), and to generate an output common-mode signal (Vout,Cm) based on the at least one pair of differential output signals (Vout+, Vout-), the main amplifier including a first current mirror (P1 & Gm2 transistors) that generates first currents (P1 & Gm2 transistor currents);
a first feedback loop circuit (loop going into amplifier Gm0), connected to an output node of the main amplifier (negative terminal of Gm0 connected to Vout,CM) which outputs the output common-mode signal (I_CMFB,CTL), and configured to form a first feedback loop that feeds back the output common-mode signal (I_CMFB,CTL feedback into Gm0); and
a second feedback loop circuit (loop going into A1) configured to generate a control signal (V_CMFB,CTL) controlling the first currents (current through P1 and Gm2) based on the output common-mode signal (Vout,CM), and form a second feedback loop (loop going from Vout,CM to A1).
In regard to Claim 2:
Zheng discloses the differential amplifier wherein the first feedback loop circuit (loop going from Vout,CM to Gm0) configured to receive a target signal (signal going into the positive terminal of Gm0) and the output common-mode signal (Vout,CM) as input signals (feedback from Gm0 output back into the negative terminal of Gm0) and output the output common-mode signal as an output signal (V_CMFB,CTL).
In regard to Claim 3:
Zheng discloses wherein the second feedback loop (loop going into A1) includes a second operational amplifier (A1 amplifier) configured to compare a target signal (signal going into the negative terminal of A1 amplifier) with the output common-mode signal (Vout,CM) and output the control signal based on the comparison (V_CMFB,CTL).
In regard to Claim 5:
Zheng discloses wherein the main amplifier (900) further includes input transistor (P6/P7) configured to generate the at least one pair of differential output signals (Vout+, Vout-) by amplifying the at least one pair of differential input signals (Vin+, Vin-); and a second current mirror circuit (N1/N2) configured to supply second current currents (currents through N1/N2) to the input transistors (P6/P7), and the control signal (V_CMFB,CTL) controls the first current mirror circuit (Gm2/P1) such that each of the first currents is equal to each of the second currents: in paragraph 43, Zheng discloses reducing the common mode offset which is achieved by having matching currents.
In regard to Claim 7:
Zheng discloses wherein the first current mirror circuit (P1 and Gm2 transistors) includes two P-type transistors, the second current mirror circuit includes two N- type transistors (N1 and N2), and the second feedback loop circuit (loop from Vout,CM to A1) provides the control signal (V_CMFB,CTL) to gate terminals of the two N-type transistors (V_CMFB,CTl biasing the gates of Gm2/P1 transistors).
In regard to Claim 8:
Zheng discloses wherein the main amplifier circuit (900) further includes input transistors (P6/P7) configured to generate the at least one pair of differential output signals (Vout+, Vout-) by amplifying the at least one pair of differential input signals (Vin+, Vin-); The first current mirror (P1/Gm2 transistors) includes two P-type transistors (P1/Gm2 transistors), and the second feedback loop circuit (loop from Vout,CM to A1) provides the control signal (V_CMFB,CTL) to gate terminals of the two P-type transistors (V_CMFB,CTL biasing the gates of Gm2/P1 transistors).
In regard to Claim 9:
Zheng discloses wherein the main amplifier circuit (900) further includes a common-mode signal senor (Rc resistors) configured to generate the output common-mode signal (Vout,CM) based on the at least one pair of differential output signals (Vout+, Vout-).
In regard to Claim 10:
Zheng discloses, in figure 10, wherein the common-mod signal (Rc resistors) includes a first resistor (Rc) and a second resistor (Rc), and the output node (Vout,Cm) is located between the first resistor (Rc) and the second resistor (Rc).
In regard to Claim 11:
Zheng discloses an electronic device comprising: a main amplifier (900) configured to generate at least one pair of differential output signals (Vout+, Vout-) by amplifying at least one pair of differential input signals (Vin+, Vin-), the main amplifier (900) including a first current mirror (P1/Gm2 transistors that includes a plurality of transistors (P1/Gm2 transistors). A common-mode signal sensor (Rc transistor) configured to provide an output common-mode signal (Vout,CM) based on the at least one pair of differential output signals (Vout+,Vout-).
A first feedback loop circuit (loop from Vout,CM to Gm0) connected to an output node of the common-mode signal (Vout,CM) sensor which outputs the output common-mode signal (Vout,CM), and configured to provide a feedback loop (loop from Vout,CM to Gm0) for the output common-mode signal (Vout,CM; and a second feedback loop (loop from Vout,CM to A1) configured to generate a control signal (V_CMFB,CTL) controlling the first current mirror (P1/Gm2 transistors) based on the output common-mode signals (Vout,CM) and to provide the control signal (V_CMFB,CTL) to gate terminals of the plurality of transistors (V_CMFB,CTL biasing the gates of Gm2/P1 transistors).
In regard to Claim 12:
Zheng discloses wherein the first feedback loop circuit (loop from Vout,CM to A1) includes a first operational amplifier (A1) configured to receive a target signal (signal going into negative terminal of A1) and the output common-mode (Vout,CM) as input signals and output the output common-mode signal as an output signal (V_CMFB,CTL).
In regard to Claim 13:
Zheng discloses wherein the second feedback loop circuit (loop from Vout,CM to A1) includes a second operational amplifier (A1) configured to compare a target signal (negative terminal of A1) with the output common-mode signal (Vout,Cm) going into the negative terminal of A1) and output the control signal (V_CMFB,CTL) based on the comparison.
In regard to Claim 14:
Zheng discloses wherein the main amplifier (900) circuit further includes: input transistors (P6 & P7) configured to generate the at least one pair of differential output signals (Vout+, Vout-) by amplifying the at least one pair of differential input signals (Vin+, Vin -); and a second current mirror circuit (N1, N2) configured to supply second currents (current supplied from N1 and N2) to the input transistors (P6 & P7), and the control signal (V_CMFB,CTL) controls the first current mirror circuit (N1/N2) such that the first currents are equal to the second currents: paragraph 43, Zheng discloses that an attempt is made to reduce the common mode offset which is done by having matches currents.
In regard to Claim 15:
Zheng discloses wherein the main amplifier (900) circuit further includes input transistors (P6/P7) configured to generate the at least one pair of differential output signals by amplifying the at least one pair of differential input signals (Vin+, Vin-); the first current mirror circuit (P1/Gm2 transistors) includes two P-type transistors, and the second feedback loop circuit (loop from Vout,CM to A1) provides the control signal (V_CMFB,CTL) to gate terminals of the two P-type transistors (V_CMFB,CTL biasing the gates of Gm2/P1 transistors).
In regard to Claim 16:
Zheng discloses the common-mode signal sensor includes a first resistor (Rc) and a second resistor (Rc), and the output node (Vout,CM) is located between the first resistor (Rc) and the second resistor (Rc).
In regard to Claim 17:
Zheng discloses an operating method of a differential amplifier (900), the method comprising: receiving at least one pair of differential input signals (Vin+, Vin-) through input transistors (P6 & P7) connected to terminals of one or more current mirrors (P1/Gm2 current mirror and N1/N2); generating an output common-mode signal (Vout,CM) based on the at least one pair of differential input signals (Vin+, Vin-);
controlling impedance of an output mode (Vout,CM) at which the output common-mode signal (Vout,CM) is provided, based on the output common-mode signal (Vout,CM) and a target signal (signal going into negative terminal of A1 amplifier) through a first feedback loop (loop going from Vout,CM to Gm0); generating a control signal (V_CMFB,CTL) and a target signal (signal going into negative terminal of A1) through a second feedback loop (loop from Vout,CM to A1); and controlling the one or more current mirrors (P1/Gm2 & N1/N2) based on the control signal (output signal of second feedback loop, V_CMFB,CTL, feeds current mirrors P1/Gm2).
In regard to Claim 18:
Zheng discloses wherein the generating of the control signal (V_CMFB,CTL) includes comparing the output common-mode signal (Vout,CM) with the target signal (negative terminal of A1/Positive terminal of Gm0) and generating the control signal (V_CMFB,CTL).
In regard to Claim 19:
Zheng discloses wherein the differential amplifier circuit (900) includes:
A first current mirror (P1/Gm2 transistors) generating first currents; and a second current mirror circuit (N1/N2 transistors) generating second currents, and the controlling of the current mirror circuits (P1/Gm2 & N1/N2) based on the control signal (V_CMFB,CTL) includes controlling the first current mirror circuit (P1/Gm2) based on the control signal (V_CMFB,CTL) such that the first currents are equal to the second currents: paragraph 43, Zheng discloses reducing the common mode offset which is achieved by having matching currents.
In regard to Claim 20:
Zheng discloses wherein the generating of the output common-mode signal (Vout,CM) includes: generating at least one pair of differential output signals (Vout+, Vout-) by amplifying at least one pair of differential input signal (Vin+, Vin-); and generating the output common-mode signal (Vout,CM) based on the at least one pair of differential output signals (Vout+, Vout-), using two resistors (two Rc resistors).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
2. Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zheng (US 20140254779 A1), in view of Gopinathan (US-6222418-B1).
In regard to Claim 4:
Zheng does not disclose wherein the second operational amplifier has a gain of 1.
In a similar field of endeavor, Gopinathan discloses wherein, in figure 3, the second operational amplifier (22; figure 3) has a gain of 1 (column 2, lines 34-35)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the unity-gain buffer (a type of opamp) taught by Gopinathan in combination with the teachings of Zheng. One would be motivated to do so because Gopinathan teaches that utilizing a unity-gain buffer allows for avoiding introducing a voltage differential at the input (column 2, lines 38-39).
3. Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zheng (US 20140254779 A1), in view of Perisetty (US-6222418-B1).
In regard to Claim 6:
Zheng discloses wherein the second feedback loop circuit (loop from Vout,CM to A1) provides the control signal (V_CMFB,CTL) to gate terminals of the two N-type transistors (V_CMFB,CTL biasing the gates of Gm2/P1, which are P-type but may be interchanged to be N-type).
Zheng does not disclose wherein the first current mirror circuit includes two N-type transistors, the second current mirror circuit includes two P-type transistors, and the second feedback.
In a similar field of endeavor, Perisetty teaches that pmos and nmos transistors may be interchangeable.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to utilize the teaching of pmos/nmos interchangeability of Perisetty in combination with the teachings of Zheng. One would be motivated to do so because Perisetty discloses in paragraph 55 lines 12-15 that pmos and nmos may be interchangeable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMAAN JAWAD KHAN whose telephone number is (571)270-7266. The examiner can normally be reached M-Th 9-4.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at (571)-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.J.K./Examiner, Art Unit 2843
/Jessica Han/Supervisory Patent Examiner, Art Unit 2843
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