DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 9/5/24 and 8/11/25 are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 10-13, 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seo et al. (US 2022/0165321).
With respect to claim 1,
Figure 8 of Seo discloses an apparatus for correcting output impedance of a memory interface driving circuit, the output impedance correction apparatus comprising:
a first pull-down (PD) driver (451) including a plurality of first sub PD drivers connected to each other in parallel (see Figure 5 and Paragraph 98);
a first control unit (460) configured to sequentially change a first control code (PDCD1), the first control code being a combination of control signals for turning the plurality of first sub PD drivers on or off in each pull-down sweep (Paragraph 103); and
a first comparator (461) configured to generate a first output pattern, the first output pattern being a sequence of 0 or 1 representing a result of comparing an output voltage of the first PD driver generated according to the first control code with a first reference voltage (Paragraph 103),
wherein the first control unit (460) is configured to determine a first impedance correction code (PDCD1) for the memory interface driving circuit from among the sequentially changing first control codes using the first output pattern (see Figure 2 – where PDCD1 is input to 320).
With respect to claim 2,
Seo further teaches wherein one terminal of a reference resistor (RZQ) is connected to an output terminal of the first PD driver (451 – see N12), and a first power supply (VDDQ) is connected to the other terminal of the external resistor (see Figure 8).
With respect to claim 10,
Seo further teaches a second PD driver (453) including a plurality of second sub PD drivers connected to each other in parallel (Paragraph 98), wherein outputs of the plurality of second sub PD drivers are configured to be controlled using the first impedance correction code (PDCD1).
With respect to claim 11,
Seo further teaches a pull-up (PU) driver (421) including a plurality of sub PU drivers connected to each other in parallel and having an output terminal connected to an output terminal of the second PD driver (Paragraph 98 and Figure 8);
a second control unit (430) configured to sequentially change a second control code (PUCD1), the second control code being a combination of control signals for turning the plurality of sub PU drivers on or off (Paragraph 99); and
a second comparator (431) configured to generate a second output pattern representing a result of comparing an output voltage of the first PU driver generated according to the second control code (VPU) with a second reference voltage (VTG1),
wherein the second control unit (430) is configured to determine a second impedance correction code (PUCD1) for the memory interface driving circuit from among the sequentially changing second control codes using the second output pattern (see Figure 2 – where PUCD1 is input to 320).
With respect to claim 12,
Seo further teaches wherein the memory interface driving circuit includes a pull-down driver including a plurality of sub pull-down drivers connected to each other in parallel, and a pull-up driver including a plurality of sub pull-down drivers connected to each other in parallel, wherein a connection structure of the plurality of sub pull-down drivers is the same as that of the plurality of first sub PD drivers, and wherein a connection structure of the plurality of sub pull-up drivers is the same as that of the plurality of sub PU drivers (see Figure 5 and Paragraph 98).
With respect to claim 13, this claim has substantially the same subject matter as that in claim 1 and differs only in that claim 1 is an apparatus claim whereas claim 13 is a method claim. Therefore, claim 13 is rejected under the same rationale as claim 1 above.
With respect to claim 19, this claim has substantially the same subject matter as that in claim 10 and differs only in that claim 10 is an apparatus claim whereas claim 19 is a method claim. Therefore, claim 19 is rejected under the same rationale as claim 10 above.
With respect to claim 20, this claim has substantially the same subject matter as that in claim 11 and differs only in that claim 11 is an apparatus claim whereas claim 20 is a method claim. Therefore, claim 20 is rejected under the same rationale as claim 11 above.
Allowable Subject Matter
Claims 3-9 and 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/JANY RICHARDSON/ Primary Examiner, Art Unit 2844