DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 20 is objected to because of the following informalities:
Claim 20 in line 3 recites “the a bit-line” which should be “the [[a]] bit line” instead.
Claim 20 recites “first metal” in line 4 and recites “second metal” in line 6, which should be “a first metal” and “a second metal” respectively.
Claim 20 (in line 10) recites “oxide of the second metal” which should be “an oxide of the second metal” instead.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Each of claim 1 (in l. 7), claim 2 (in l. 1), claim 3 (in l. 3), claim 4 (in l. 4), claim 5 (in l. 2), claim 6 (in ll. 3-4), claim 8 (in l. 3), claim 9 (in l. 3) , claim 10 (in l. 1), claim 12 (in l. 2 & 4), claim 13 (in l. 2) recites “the liner patterns”. It is not clear if they are referring to “a plurality of liner patterns” as recited in claim 1 in line 6 or different ones. Examiner is considering as such and interpreting the recitation in claim 1 in line 6 as “[[a plurality of]] liner patterns between the liner film and the channel structure, each of…” to make it consistent with later recitations of “the liner patterns” as mentioned.
Each of claim 14 (in l. 9), claim 15 (in l. 3), claim 16 (in l. 4), claim 19 (in l. 3) recites “the liner patterns”. It is not clear if they are referring to “a plurality of liner patterns” as recited in claim 1 in line 6 or different ones. Examiner is considering as such and interpreting the recitation in claim 14 in line 8 as “[[a plurality of]] liner patterns between the liner film and the channel structure, each of…” to make it consistent with later recitations of “the liner patterns” as mentioned.
Each of Claim 3 ( in l. 6) and claim 15 ( in line 6) recites “the upper surface” which has an antecedent base issue. Examiner is interpreting the limitation as “[[the]] an upper surface…” instead.
Claims 2-13 are also rejected being dependent on claim 1.
Claims 15-19 are also rejected being dependent on claim 14.
Allowable Subject Matter
Claims 1-19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
With respect to claim 1, the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation:
“[[a plurality of]] liner patterns between the liner film and the channel structure, each of the liner patterns overlapping the channel structure when viewed in a plan view”
Regarding claim 1, RYU (US 2022/0223732 A1) teaches,
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A semiconductor memory device (Fig. 10 as annotated above) comprising:
a bit-line (conductive line 120 which may function as bit line, para [0030]) on a substrate (100, para [0028]) and extending in a first direction (X);
a liner film (125, para [0093]) on the bit-line and extending along an upper surface of the bit-line;
a channel structure (130, para [0041]) on the liner film , the channel structure including a first channel pattern (including vertical portion of 130 on left) and a second channel pattern (including vertical portion of 130 on right) that are spaced apart from each other in the first direction (X) ;
……a first word-line (150A, para [0045]) between the first channel pattern and the second channel pattern, the first word-line extending in a second direction (Z) intersecting the first direction;
a second word-line (150B, para [0045]) between the first channel pattern and the second channel pattern, the second word-line extending in the second direction (Z) , the second word-line spaced apart from the first word-line in the first direction (X);
and a first capacitor (170A, para [0028]) and a second capacitor(170B, para [0028]) on the first channel pattern and the second channel pattern, respectively, the first capacitor and the second capacitor connected to the first channel pattern and the second channel pattern, respectively(via landing pads 160A and 160B respectively, para [0055]).
But RYU does not explicitly teach,
“[[a plurality of]] liner patterns between the liner film and the channel structure, each of the liner patterns overlapping the channel structure when viewed in a plan view”
The other cited arts, either alone or in combination, apear to cure deficiencies of RYU.
Claims 2-13 would be allowable, being dependent on Claim 1.
With respect to claim 14, the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation:
“[[a plurality of ]] liner patterns between the liner film and the channel structure, each of the liner patterns including oxide of the second metal”
Regarding claim 14, RYU (US 2022/0223732 A1) teaches,
A semiconductor memory device (Fig. 10 as annotated above) comprising:
a bit-line (conductive line 120 which may function as bit line, para [0030]) on a substrate (100, para [0028]and extending in a first direction, the bit-line including first metal (aluminum , para [0031]) ;
a liner film (125, para [0093]) on the bit-line and extending along an upper surface of the bit-line, the liner film including second metal (titanium, para [0093]) different from the first metal;
a channel structure (130, para [0041]) on the liner film, the channel structure including a first channel pattern (including vertical portion of 130 on left) and a second channel pattern (including vertical portion of 130 on right) that are spaced apart from each other in the first direction;
…….a first word-line(150A, para [0045]) between the first channel pattern and the second channel pattern, the first word-line extending in a second direction(Z) intersecting the first direction;
a second word-line (150B) between the first channel pattern and the second channel pattern, the second word-line extending in the second direction (Z) , the second word-line spaced apart from the first word-line in the first direction (X); and a
first capacitor (170A, para [0028]) and a second capacitor (170B, para [0028]) on the first channel pattern and the second channel pattern, respectively, the first capacitor and the second capacitor connected to the first channel pattern and the second channel pattern, respectively (via landing pads 160A/160B respectively, para [0055]).
But RYU does not explicitly teach,
[[a plurality of]] liner patterns between the liner film and the channel structure, each of the liner patterns including oxide of the second metal;
The other cited arts, either alone or in combination, apear to cure deficiencies of RYU.
Claims 15-19 would be allowable, being dependent on claim 14.
Claims 20 would be allowable if rewritten to overcome claim objection, set forth in this Office action.
With respect to claim 20, the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation:
“a liner pattern between the liner film and the channel structure, the liner pattern including oxide of the second metal doped with niobium”
Regarding claim 20, RYU (US 2022/0223732 A1) teaches,
A semiconductor memory device (Fig. 10 as annotated above) comprising:
…..substrate (100, para [0028]),
a bit-line (120, para [0030])…….., the [[a]] bit-line extending in a first
direction (X) , the bit-line including first metal (Al, para [0031]) ;
a liner film (125, para [0093]) on the bit-line, the liner film extending along an upper surface of the bit-line, the liner film including second metal (titanium, para [0093]) different from the first metal;
a channel structure (130, para [0041]) on the liner film, the channel structure including a first channel pattern (including vertical portion of 130 on left) and a second channel pattern (including vertical portion of 130 on right) that are spaced apart from each other in the first direction;
…..a first word-line (150A, para [0045]) between the first channel pattern and the second channel pattern, the first word-line extending in a second direction (Z) intersecting the first direction;
a second word-line (150B, para [0045]) between the first channel pattern and the second channel pattern, and the second word-line extending in the second direction (Z) , the second word-line spaced apart from the first word-line in the first direction (X);
a first capacitor (170A, para [0028]) and a second capacitor (170B, para [0028]) on the first channel pattern and the second channel pattern, respectively, the first capacitor and the second capacitor connected to the first channel pattern and the second channel pattern, respectively(via landing pads 160A/160B, para [0055]) and
a gate isolation pattern (114, para [0028]) on the liner pattern, the gate isolation pattern isolating the first word-line and the second word-line from each other(as seen).
But RYU does not explicitly teach,
a peripheral gate structure on the substrate (100);
a liner pattern between the liner film (125) and the channel structure (130) , the liner pattern including oxide of the second metal doped with niobium;
But RYU additionally teaches,
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a peri-gate structure (obvious gate structure of peripheral circuit element PT including 220 & 230 which may include transistor for sense amplifiers and/or row drivers and/or column and row decoders, para [0072], FIG. 6) on the substrate(100);
and a bit line (120, para [0030]) is on the peri-gate structure;
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to incorporate the teaching of RYU above into Ryu’s semiconductor memory device such that a peripheral circuit element PT including a transistor is formed on the substrate 100 such that a peri-gate structure (obvious gate structures of transistors formed as circuit element PT) on the substrate(100), according to teaching of RYU, in order to form a transistor for sense amplifiers and/or row drivers and/or column and row decoders to operate the memory device, as taught by RYU above
RYU still does not explicitly teach,
a liner pattern between the liner film and the channel structure, the liner pattern including oxide of the second metal doped with niobium;
The other cited arts, either alone or in combination, apear to cure deficiencies of RYU.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
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/K.A.R/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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