Prosecution Insights
Last updated: April 19, 2026
Application No. 18/825,615

METHOD AND SYSTEM

Final Rejection §102§103
Filed
Sep 05, 2024
Examiner
DANG, PHONG H
Art Unit
2184
Tech Center
2100 — Computer Architecture & Software
Assignee
Liebherr-Aerospace Lindenberg GmbH
OA Round
2 (Final)
80%
Grant Probability
Favorable
3-4
OA Rounds
2y 3m
To Grant
91%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allow Rate
283 granted / 353 resolved
+25.2% vs TC avg
Moderate +10% lift
Without
With
+10.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
24 currently pending
Career history
377
Total Applications
across all art units

Statute-Specific Performance

§101
2.7%
-37.3% vs TC avg
§103
44.5%
+4.5% vs TC avg
§102
25.6%
-14.4% vs TC avg
§112
18.0%
-22.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 353 resolved cases

Office Action

§102 §103
DETAILED ACTION Response to Amendment The Applicant’s Amendment, filed 02/20/2026 has been entered. Claims 1-16 are pending in the Application. Response to Arguments Applicant’s amendment has overcome the 112(a) rejection. Accordingly, the 112(a) rejection of claim 13 has been withdrawn. Applicant's arguments filed 02/20/2026 with respect to the prior art rejection have been fully considered but they are not persuasive. Regarding claim 1, the Applicant argues that the prior art Raja (US 20190188174) fails to teach the amended limitation “both a first data and a second data are transmitted to a first processing unit at a second transmission timepoint”. The Examiner respectfully disagrees. At the outset, the Examiner submits that the claim defines both the first transmission timepoint and a second transmission timepoint as receiving timepoint of the reception of the synchronization signal by the second and/or third processing unit. Thus, the first and the second timepoints can be construed as the same timepoint, different overlapping timepoints and/or separate timepoints of different periods, lengths and/or start times. Raja discloses that the select signal 118 defines a time during which data is transferred between the master 102 and the slaves 104-108. Thus, different timepoints defined by the select signal 118 can be construed as the transmission timepoints. Please refer to the annotated figure 2 below showing two different timepoints defined by the select signal 118. [AltContent: textbox (2nd timepoint)][AltContent: textbox (1st timepoint)][AltContent: textbox ()][AltContent: ] PNG media_image1.png 2676 1706 media_image1.png Greyscale As shown in figure 2 above, two different first data 220 and second data 218 are transmitted from the slave 108 (e.g. second processing unit) to the master 102 (e.g. first processing unit) via line 116 in the second timepoint. Therefore, the prior art discloses the argued limitation as claimed. The Examiner suggests amending the claim to clarify the first timepoint and the second timepoint to differentiate them from each other and from the prior art. Based on the reasoning above, the rejection should be maintained. Please see below for the detailed rejection. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-7, 9-11, 14 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Raja et al US 20190188174. Regarding claim 1, Raja teaches computer-implemented method for transmitting data (see figure 1 and figure 2), comprising the steps of: transmitting a synchronisation signal via a first processing unit (select signal 118 transmitted via master device 102); receiving the synchronisation signal by a second and/or a third processing unit, at a receiving timepoint in each case (select signal 118 is received by slave device 108 and slave device 106 and 108); transmitting first data from the third processing unit to the second processing unit (see para 0026, the slave device 106 is transmitting a status field 220 in the data signal 114 e.g. to slave device 108), wherein the transmission of the first data takes place at a first transmission timepoint which depends on the respective receiving timepoint of the reception of the synchronisation signal by the second and/or third processing unit (see figure 2 shows that the transmission of 220 is depends on a reception timepoint of signal 118); transmitting the first data and a second data from the second processing unit to the first processing unit (see para 0026 and figure 2, the slave device 108 is transmitting the status field 220 and a status field 218 in the data signal 116 e.g. to the master device 102), wherein the transmission of the first data and the second data takes place at a second transmission timepoint which depends on the respective receiving timepoint of the reception of the synchronisation signal by the second and/or third processing unit (see figure 2 shows that the transmission of 220 and 218 are depends on a reception timepoint of signal 118, also see para 0021, The select signal 118 defines a frame interval (a time during which data is transferred between the master device 102 and the slave devices 104-108)). Regarding claim 2, Raja further teaches the first transmission timepoint is a sum of the receiving timepoint of the receiving of the synchronisation signal by the second and/or third processing unit, a first time offset, and/or a time duration, and/or in that the second transmission timepoint is the sum of the receiving timepoint of the receiving of the synchronisation signal by the second and/or third processing unit, a second time offset, and/or a time duration (figure 2 shows that the transmission timepoints is a sum of receiving timepoint of select signal 118 and a time duration/offset before clock 120 start). Regarding claim 3, Raja further teaches before transmitting of first data from the third processing unit to the second processing unit, of: collecting the first data by means of the third processing unit (see para 0054, The slave device retrieves the reply value from the storage 608). Regarding claim 4, Raja further teaches before transmitting of the first data and the second data from the second processing unit to the first processing unit, of: collecting the second data by means of the second processing unit (see para 0054, The slave device retrieves the reply value from the storage 608). Regarding claim 5, Raja further teaches the collecting of the first data takes place at a first collection timepoint, which is a sum of the receiving timepoint of the receiving of the synchronisation signal by the second and/or third processing unit, and of the first time offset, and/or in that the collecting of the second data takes place at a second collection timepoint, which is a sum of the receiving timepoint of the receiving of the synchronisation signal by the second and/or third processing unit, and of the second time offset (see figure 2 shows that the transmission/collection of 220 is depends on a reception timepoint of signal 118, also see para 0021, The select signal 118 defines a frame interval (a time during which data is transferred between the master device 102 and the slave devices 104-108)). Regarding claim 6, Raja further teaches the transmission of the first data and/or of the second data from the second processing unit to the first processing unit takes place via exactly one data channel (see figure 1 shows that only one data channel is used). Regarding claim 7, Raja further teaches the steps of the method are carried out multiple times (see para 0017, in some implementations, two transactions (two communication frames) are required). Regarding claim 9, Raja further teaches system comprising a first, second and third processing unit, which are in each case configured so as to carry out a method according to claim 1 (see figure 1, communication system 100 comprising the master device 102, the slave device 108 and 106). Regarding claim 10, Raja further teaches the first, second and/or third processing unit in each case comprise or constitute a processor (see para 0002, master device, such as a microcontroller, also see para 0004, the slave device includes execution control circuitry). Regarding claim 11, Raja further teaches the first, second and/or third processing unit are connected directly or indirectly via a data channel (see figure 1, data channel of 110, 112, 114, and 116). Regarding claim 14, Raja further teaches the steps of the method are carried out periodically (see para 0021, a frame interval e.g. transmission is periodically during the time defined by the frame interval). Regarding claim 16, Raja further teaches the first, second and/or third processing unit are connected directly or indirectly via a high-speed data bus (see figure 1, the bus including 110, 112, 114, and 116). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 8 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Raja as applied to claims above, and further in view of Zielbauer US 20030014680. Regarding claim 8, Raja teaches all the features with respect to claim 1 as outlined above. But Raja fails to teach the first and/or the second transmission timepoint is adjusted. However, Zielbauer teaches adjusting device’s transmission timepoint (see figures 3B-3D and para 0079, each data source 3, 4, 5 sets a time delay ΔTi (i=1, 2, 3 . . .) for all its dispatched data to the value ΔTi=Tn−ti). Therefore, it would have been obvious to modify the method and system of Raja and further incorporate adjusting the transmission timepoint via a delay. The motivation for doing so is to prevent synchronization losses caused by propagation delays in communication between the devices. Regarding claim 15, Raja teaches all the features with respect to claim 1 as outlined above. But Raja fails to teach the first and/or the second transmission timepoint is adjusted to a latency of the third and/or second processing unit in each case. However, Zielbauer teaches adjusting device’s transmission timepoint to a latency of the third and/or second processing unit in each case (see figures 3B-3D and para 0079, each data source 3, 4, 5 sets a time delay ΔTi (i=1, 2, 3 . . .) for all its dispatched data to the value ΔTi=Tn−ti, also see para 0072, ti (i=1, 2, 3) is the measured signal propagation time between the control device 1 and the respective data source 3, 4, 5 e.g. latency of the device). Therefore, it would have been obvious to modify the method and system of Raja and further incorporate adjusting the transmission timepoint via a delay. The motivation for doing so is to prevent synchronization losses caused by propagation delays in communication between the devices. Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Raja as applied to claims above, and further in view of Esaki US 20180007408. Regarding claim 12, Raja teaches all the features with respect to claim 9 as outlined above. But Raja fails to teach the system is a component of a flight control of an aircraft. However, Esaki teaches a communication synchronization system as a component of a flight control of an aircraft (see para 0031, a process synchronization control system 10 according to the embodiment is incorporated in, for example, a flight control system that performs flight control of an aircraft). Therefore, it would have been obvious to modify the method and system of Raja and further incorporate them into a flight control system of an aircraft. The motivation for doing is to improve the communication reliability in the system. Regarding claim 13, Raja teaches all the features with respect to claim 3 as outlined above. But Raja fails to teach collecting the first data and collecting the second data includes reading out a sensor. However, Esaki teaches collecting data by reading out a sensor (see figure 1 and para 0033, the three channels A to C acquire the respective input signals from the sensor 15). Therefore, it would have been obvious to modify the method and system of Raja and further incorporate sensor data collection. The motivation for doing so is to obtain sensor data to further refining the control of the system. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kashiwagi et al US 20190258679 discloses a sensor data collection unit to collect data from a sensor THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHONG H DANG whose telephone number is (571)272-0470. The examiner can normally be reached Monday-Friday 9:30AM - 6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached at (571)272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PHONG H DANG/ Primary Examiner, Art Unit 2184
Read full office action

Prosecution Timeline

Sep 05, 2024
Application Filed
Nov 14, 2025
Non-Final Rejection — §102, §103
Feb 20, 2026
Response Filed
Mar 18, 2026
Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12596657
NETWORK INSTANTIATED PERIPHERAL DEVICES
2y 5m to grant Granted Apr 07, 2026
Patent 12596671
PRECISION TIMING ACROSS PCIe CEM NICS
2y 5m to grant Granted Apr 07, 2026
Patent 12591536
USER MODE DIRECT DATA ACCESS TO NON-VOLATILE MEMORY EXPRESS DEVICE VIA KERNEL-MANAGED QUEUE PAIR
2y 5m to grant Granted Mar 31, 2026
Patent 12580844
NETWORK MULTICASTING USING ALTERNATE SETS OF DIRECTIVES
2y 5m to grant Granted Mar 17, 2026
Patent 12579088
SEMI-POLLING INPUT/OUTPUT COMPLETION MODE FOR NON-VOLATILE MEMORY EXPRESS COMPLETION QUEUE
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
80%
Grant Probability
91%
With Interview (+10.4%)
2y 3m
Median Time to Grant
Moderate
PTA Risk
Based on 353 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month