DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 7-8, 10, 12-13, 18-19, and 21 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Pub. 2021/0063250 (“Park”).
Claim 1
Park discloses an ultra-low power (ULP) temperature sensing system, the system comprising: a proportional to absolute temperature (PTAT) current source (current source CS), wherein the PTAT current source is configured to generate a PTAT current that varies with an operating temperature (paragraph [0006]); a switched-capacitor converter electrically coupled to the PTAT current source, wherein the switched-capacitor converter is configured to generate an analog voltage signal based on the PTAT current (paragraph [0045]); and a ULP analog-to-digital converter (ADC) electrically coupled to the PTAT current source and the switched-capacitor converter (paragraph [0033]), wherein the ULP ADC is configured to output a digital voltage value corresponding to the analog voltage signal (output signal 67).
Claim 2
Park discloses the system of claim 1, wherein the analog voltage signal is proportional to the operating temperature (paragraph [0071]).
Claim 7
Park discloses the system of claim 1, wherein the switched-capacitor converter comprises at least one switched-capacitor based resistance, wherein the analog voltage signal is generated by the PTAT current flowing through the switched-capacitor based resistance (Park, paragraph [0072]).
Claim 8
Park discloses the system of claim 7, wherein the at least one switched-capacitor based resistance comprises a plurality of switched capacitors, wherein a switching frequency of the plurality of switched capacitors is a clock frequency of a crystal oscillator (XO) (paragraph [0077]).
Claim 10
Park discloses the system of claim 1, wherein the ULP ADC comprises a comparator (comparator 32), sample and hold circuit (delay circuit 34), and a digital-to-analog converter (DAC), wherein an output of the sample and hold circuit and an output of the DAC are electrically coupled to inputs of the comparator (paragraph [0041]), and wherein the sample and hold circuit is configured to receive the analog voltage signal as input (paragraph [0042]).
Claim 12
Park discloses a method for temperature sensing, the method comprising: generating, by a proportional to absolute temperature (PTAT) current source, a PTAT current that varies with an operating temperature (current source CS, paragraph [0006]); generating, by a switched-capacitor converter electrically coupled to the PTAT current source, an analog voltage signal based on the PTAT current (paragraph [0045]); and providing, by a ULP analog-to-digital converter (ADC) electrically coupled to the PTAT current source, a digital voltage value corresponding to the analog voltage signal (output signal 67).
Claim 13
Park discloses the method of claim 12, wherein the analog voltage signal is proportional to the operating temperature (paragraph [0071]).
Claim 18
Park discloses the method of claim 12, wherein the switched-capacitor converter comprises at least one switched-capacitor based resistance, and wherein the method further comprises: generating, by the PTAT current flowing through the switched-capacitor based resistance, an analog voltage signal (Park, paragraph [0072]).
Claim 19
Park discloses the method of claim 18, wherein the at least one switched-capacitor based resistance comprises a plurality of switched capacitors, and wherein a switching frequency of the plurality of switched capacitors is a clock frequency of a crystal oscillator (XO) (paragraph [0077]).
Claim 21
Park discloses the method of claim 12, wherein the ULP ADC comprises a comparator (comparator 32), sample and hold circuit (delay circuit 34), and a digital-to-analog converter (DAC), wherein an output of the sample and hold circuit and an output of the DAC are electrically coupled to inputs of the comparator (paragraph [0041]), and wherein the method further comprises: receiving, by the sample and hold circuit, the analog voltage signal (paragraph [0042]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. 2021/0063250 (“Park”) in view of U.S. Patent No. 7,075,360 (“Holloway”).
Claim 3
Park discloses the system of claim 1.
Park does not appear to explicitly disclose wherein the PTAT current source is biased sub-threshold.
Holloway discloses a similar PTAT current source including a sub threshold bias (col. 2, lns 47-67).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated wherein the PTAT current source is biased sub-threshold, as disclosed by Holloway, into the device of Park, for the purpose of generating a set of charging and discharging currents to a voltage generator (Holloway, col. 3, lns 18-24).
Claim 14
Park discloses the method of claim 12.
Park does not appear to explicitly disclose wherein the PTAT current source is biased sub-threshold.
Holloway discloses a similar PTAT current source including a sub threshold bias (col. 2, lns 47-67).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated wherein the PTAT current source is biased sub-threshold, as disclosed by Holloway, into the device of Park, for the purpose of generating a set of charging and discharging currents to a voltage generator (Holloway, col. 3, lns 18-24).
Claims 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. 2021/0063250 (“Park”) in view of U.S. Pub. 2010/0289564 (“Wang”).
Claim 4
Park discloses the system of claim 1.
Park does not appear to explicitly disclose wherein the PTAT current source comprises a constant transconductance.
Wang discloses a similar PTAT current source including a constant transconductance (paragraph [0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated the PTAT current source including a constant transconductance, as disclosed by Wang, into the device of Park, for the purpose of compensating for changes in the K parameter (Wang, paragraph [0040]).
Claim 15
Park discloses the method of claim 12.
Park does not appear to explicitly disclose wherein the PTAT current source comprises a constant transconductance.
Wang discloses a similar PTAT current source including a constant transconductance (paragraph [0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated wherein the PTAT current source comprises a constant transconductance, as disclosed by Wang, into the device of Park, for the purpose of compensating for changes in the K parameter (Wang, paragraph [0040]).
Claims 5,6, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. 2021/0063250 (“Park”) in view of U.S. Pub. 2013/0301680 (“Qiu”).
Claim 5
Park discloses the system of claim 1.
Park does not appear to explicitly disclose wherein the PTAT current source comprises at least one MOSFET transistor electrically coupled to a plurality of BJT transistors.
Qiu discloses a temperature detecting device including a plurality of selectable BJTs and mosfet as a switch (paragraph [0064, 0097]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated wherein the PTAT current source comprises at least one MOSFET transistor electrically coupled to a plurality of BJT transistors, as disclosed by Qiu, into the device of Park, for the purpose of reducing mismatch between bias currents (Qiu, paragraph [0097]).
Claim 6
Park in view of Qiu discloses the system of claim 5, wherein the at least one metal-oxide-semiconductor field-effect transistor (MOSFET) transistor comprises an NMOS transistor, and wherein the plurality of bipolar junction transistors (BJTs) comprises a plurality of PNP transistors (Qiu, paragraph [0074]).
Claim 16
Park discloses the method of claim 12.
Park does not appear to explicitly disclose wherein the PTAT current source comprises at least one MOSFET transistor electrically coupled to a plurality of BJT transistors.
Qiu discloses a temperature detecting device including a plurality of selectable BJTs and mosfet as a switch (paragraph [0064, 0097]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated wherein the PTAT current source comprises at least one MOSFET transistor electrically coupled to a plurality of BJT transistors, as disclosed by Qiu, into the device of Park, for the purpose of reducing mismatch between bias currents (Qiu, paragraph [0097]).
Claim 17
Park in view of Qiu discloses the method of claim 16, wherein the at least one metal-oxide-semiconductor field-effect transistor (MOSFET) transistor comprises an NMOS transistor, and wherein the plurality of bipolar junction transistors (BJTs) comprises a plurality of PNP transistors (Qiu, paragraph [0074]).
Claims 9, 11, 20, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. 2021/0063250 (“Park”) in view of U.S. Pub. 2020/0117147 (“Mercier”).
Claim 9
Park discloses the system of claim 1.
Park does not appear to explicitly disclose wherein the ULP ADC comprises a Successive Approximation Register (SAR) ULP ADC.
Mercier discloses including SAR logic with the ADC (paragraph [0029]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated wherein the ULP ADC comprises a Successive Approximation Register (SAR) ULP ADC, as disclosed by Mercier, into the device of Park, for the purpose of providing increased sensing accuracy (Mercier, paragraph [0029]).
Claim 11
Park discloses the system of claim 10.
Park does not appear to explicitly disclose wherein the ULP ADC further comprises Successive Approximation Register (SAR) logic coupled to an output of the comparator and to inputs of the DAC, and wherein the SAR logic is configured to output the digital voltage value.
Mercier discloses including SAR logic with the ADC (paragraph [0029]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated wherein the ULP ADC further comprises Successive Approximation Register (SAR) logic coupled to an output of the comparator and to inputs of the DAC, and wherein the SAR logic is configured to output the digital voltage value, as disclosed by Mercier, into the device of Park, for the purpose of providing increased sensing accuracy (Mercier, paragraph [0029]).
Claim 20
Park discloses the method of claim 12.
Park does not appear to explicitly disclose wherein the ULP ADC comprises a Successive Approximation Register (SAR) ULP ADC.
Mercier discloses including SAR logic with the ADC (paragraph [0029]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated wherein the ULP ADC comprises a Successive Approximation Register (SAR) ULP ADC, as disclosed by Mercier, into the device of Park, for the purpose of providing increased sensing accuracy (Mercier, paragraph [0029]).
Claim 22
Park discloses the method of claim 21.
Park does not appear to explicitly disclose wherein the ULP ADC further comprises Successive Approximation Register (SAR) logic coupled to an output of the comparator and to inputs of the DAC, and wherein the method further comprises: outputting, by the SAR logic, the digital voltage value.
Mercier discloses including SAR logic with the ADC (paragraph [0029]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have incorporated wherein the ULP ADC further comprises Successive Approximation Register (SAR) logic coupled to an output of the comparator and to inputs of the DAC, and wherein the method further comprises: outputting, by the SAR logic, the digital voltage value, into the device of Park, for the purpose of providing increased sensing accuracy (Mercier, paragraph [0029]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERICA S Y LIN whose telephone number is (571)270-7911. The examiner can normally be reached M-F 8-4, TW M,W.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Douglas X Rodriguez can be reached at (571) 431-0716. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERICA S LIN/Primary Examiner, Art Unit 2853
