Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claims 1-20 remain pending in the application under prosecution and have been re-examined.
Response to Arguments
Applicant's arguments filed 11/20/2025 have been fully considered but they are not deemed to be persuasive for at least the following remarks.
Applicant remarks regarding the double patenting rejection has been noted. The non-statutory double patenting is held until submission of a terminal disclaimer that would overcome the rejection.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,094,531. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 of US Patent 12,094,531 anticipate claims 1-20 of the instant application.
As an example:
Claim 1 (Application)
Claim 1 (US Patent 12,094,531)
A device, comprising: a processing circuitry configured to execute instructions of matrix computations;
a local memory coupled to the processing circuitry to store operands of the instructions; and
a circuit configured to: receive, during execution of the instructions of matrix computations, a request to fetch an item from a memory address into the local memory at a local address, the request configured with a hint; and
determine, in response to the request, whether to load the item through a buffer based at least in part on the hint and a data type of the item.
A device, comprising: a plurality of processing units configured to execute instructions and perform at least matrix computations of an artificial neural network via execution of the instructions;
a local memory coupled to the processing units and configured to store at least operands of the instructions during operations of the processing units in execution of the instructions; a memory configured as a buffer; a random access memory; and
a logic circuit coupled to the buffer, the local memory, and the random access memory; wherein the instructions include a first instruction to fetch an item from the random access memory to the local memory;
the first instruction includes a field related to caching the item in the buffer; and
during execution of the first instruction the logic circuit is configured to determine whether to load the item through the buffer based at least in part on the field specified in the first instruction.
Claim 11 (Application)
Claim 15 (US Patent 12,094,531)
A method, comprising:
executing, by a processing circuitry in a device, instructions of matrix computations;
storing, in a local memory coupled to the processing circuitry in the device, operands of the instructions;
receiving, in the device, a request to fetch an item from a memory address into the local memory at a local address, the request configured with a hint; and
determining, by the device in response to the request, whether to load the item through a buffer based at least in part on the hint and a data type of the item.
A method, comprising:
executing, by a plurality of processing units of a device, instructions to perform at least matrix computations of an artificial neural network;
storing, in a local memory coupled to the processing units in the device, at least operands of the instructions during operations of the processing units in execution of the instructions;
receiving a first instruction having a memory address and a local address to request an item at the memory address in a random access memory of the device to be fetched into the local memory at the local address, the first instruction having a field identifying a hint for caching the item in a system buffer of the device; and
determining, during execution of the first instruction, whether to load the item through the system buffer based at least in part on the hint specified in the first instruction and a data type of the item.
Claims 1, 11, and 15 of the patent recite elements that cover of the elements of corresponding claims 1, 11, and 19 of the application, as such anticipate claims 1, 11, and 19.
With respect to claims 2-10, 12-18 and 20 of the instant application and corresponding claims 2-10, 12-14, and 16-20 of U.S. Patent 12,094,531, the claims of the application recite all the elements of corresponding claims of the patent. Therefore, claims 2-10, 12-14, and 16-20 of U.S. Patent 12,094,531 anticipate corresponding claims of the instant application.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20130031298 A1 (TAN) et al teaching composite memory device that includes different types of non-volatile memory devices, which have different performance characteristics (different storage types defining desired characteristic or a targeted data configuration in the types of memory), the memory device may receive requests with includes a command, a logical address for at least a block of data associated with the command, and a hint associated with the command; the composite memory device executes the command on the block of data at the logical address identifying one of the types of non-volatile memory devices (defining desired characteristic or a targeted data configuration in the types of memory) and conditionally executes the hint based on one or more criteria, such as: response to an operating environmental change for data safety; an operational states of the types of memory devices (desired characteristic or a targeted data configuration in the types of memory).
US 20190384370 A1 (KIM et al) teaching microcode controller is to identify a global power and performance hint in an instruction stream that includes first and second instruction phases to be executed in parallel, identify a local hint based on synchronization dependence in the first instruction phase.
US 20220365782 A1 (WANG et al) teaching system including a memory to store an input data, an accelerator circuit comprising an input command execution circuit, a neuron matrix command execution circuit, and an output command execution circuit, and a processor, communicatively coupled to the memory and the accelerator circuit, to generate a stream of instructions from a source code targeted the accelerator circuit, each one of the stream of instructions comprising at least one of an input command, a neuron matrix command, or an output command, and issue the stream of instructions to the accelerator circuit for execution by the input command execution circuit, the neuron matrix command execution circuit, and the output command execution circuit.
US 11574100 B2 (KALE et al) teaching device, comprising: a substrate; random access memory configured to store first data representative of weights of an artificial neural network and store second data representative of instructions executable to implement matrix computations of the artificial neural network using the first data representative of the weights of the artificial neural network; an integrated circuit die of a field-programmable gate array (FPGA) or application specific integrated circuit (ASIC) implementing a deep learning accelerator (DLA); random access memory to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network.
All claims are identical to or patentably indistinct from, or have unity of invention with claims in the application prior to the entry of the submission under 37 CFR 1.114 (that is, restriction (including a lack of unity of invention) would not be proper) and all claims could have been finally rejected on the grounds and art of record in the next Office action if they had been entered in the application prior to entry under 37 CFR 1.114. Accordingly, THIS ACTION IS MADE FINAL even though it is a first action after the filing of a request for continued examination and the submission under 37 CFR 1.114. See MPEP § 706.07(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PIERRE MICHEL BATAILLE whose telephone number is (571)272-4178. The examiner can normally be reached Monday - Thursday 7-6 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIM VO can be reached on (571) 272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PIERRE MICHEL BATAILLE/Primary Examiner, Art Unit 2136
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