DETAILED ACTION
This application is responsive to the following: the application and information disclosure statement filed September 5, 2024.
Claims 1-16 are pending. Claims 1 and 11 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 5, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-8, 10-12, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 20240040762 A1) in view of Mathur et al (US 20230354571 A1).
Regarding Independent Claim 1, Liaw teaches a semiconductor storage device including a 2-port SRAM cell (Fig. 2A: Cell-1),
the 2-port SRAM cell (Fig. 2A: Cell-1) comprising:
a first transistor (Fig. 1: W-PU-2) having nodes, one of which is connected to a first power source (Fig. 2: CVdd) that supplies a first voltage and the other one of which is connected to a first node (Fig. 1: 110), and having a gate connected to a second node (Fig. 1: 112);
a second transistor (Fig. 1: W-PU-1) having nodes, one of which is connected to the first power source (Fig. 2: CVdd) and the other one of which is connected to the second node (Fig. 1: 112), and having a gate connected to the first node (Fig. 1: 110);
a third transistor (Fig. 1: W-PD2) having nodes, one of which is connected to the first node (Fig. 1: 110) and the other one of which is connected to a second power source (Fig. 2: CVss) that supplies a second voltage (Fig. 2: CVss) different from the first voltage (Fig. 2: CVdd), and having a gate connected to the second node (Fig. 1: 112);
a fourth transistor (Fig. 1: W-PD1) having nodes, one of which is connected to the second node (Fig. 1: 112) and the other one of which is connected to the second power source (Fig. 2: CVss), and having a gate connected to the first node (Fig. 1: 110);
a fifth transistor (Fig. 1: W-PG1) having nodes, one of which is connected to a first write-bit line (Fig. 1: W-BL) and the other one of which is connected to the first node (Fig. 1: 112), and having a gate connected to a write-word line (Fig. 1: WWL);
a sixth transistor (Fig. 1: W-PG2) having nodes, one of which is connected to a second write-bit line (Fig. 1: W-W-BL-BAR) forming a complementary bit line pair together with the first write-bit line (Fig. 1: W-BL) and the other one of which is connected to the second node (Fig. 1: 110), and having a gate connected to the write-word line (Fig. 1: WWL);
a seventh transistor (Fig. 1: R-PD) having one node connected to the second power source (Fig. 2: CVdd) and a gate connected to the second node (Fig. 1: 112); and
an eighth transistor (Fig. 1: R-PG) having nodes, one of which is connected to the other node of the seventh transistor (Fig. 1: R-PD) and the other one of which is connected to a read-bit line (Fig. 1: R-W-BL), and having a gate connected to a read-word line (Fig. 1: R-WL),
the write-word line (Fig. 2B: M2-W-WL) having a first interconnect formed in a first interconnect layer (Fig. 2B: M2) and extending in a second direction perpendicular to the first direction (Fig. 2B: x).
the read-word line (Fig. 2B: M2-R-WL) having a second interconnect (Fig. 2B: M2) formed in the first interconnect layer and extending in the second direction (Fig. 2B: x).
Liaw fails to teach buried bit line interconnect structures.
Mathur teaches the first write-bit line (Fig. 2: BL) having a first buried interconnect formed in a buried interconnect layer (Fig. 2: BM0) and extending in a first direction,
the second write-bit line (Fig. 2: NBL) having a second buried interconnect formed in the buried interconnect layer (Fig. 2: BM0) and extending in the first direction,
Mathur states in paragraphs 9-10 “the buried signal wires may be disposed within the substrate of an integrated circuit, wherein the buried signal wires may reduce congestion of metal routing layers. The buried signal wires may also provide lower resistance and/or lower capacitance memory signal routing when compared with traditional non-buried wires, thereby decreasing signal delay and energy consumption. Also, using buried signal wires in memory devices may have a significant impact on memory performance by simultaneously reducing memory access time, improving cycle time, reducing dynamic energy consumption and also increasing memory density. In addition, as the buried signal wire layer is less congested, the signals may be wider and/or disposed further apart to reduce resistance. In some instances, resistance of the wires may be further reduced by making the buried signal wire layer taller, and buried signal wires may be applied to unidirectional and non-unidirectional signals. In various implementations, buried signal wires may have lower capacitance and resistance, due to reduced signal coupling, when compared to similar non-buried signal wires of the same wire width. Also, various other critical signal wires for memory wordlines, bitlines and/or clock signals may be implemented as buried signal wires so as to provide improved memory performance and lower energy consumption when compared to implementing non-buried signal wires that use traditional above-substrate connectivity.” Given these numerous benefits to implementing buried wires and signal lines it would be obvious to apply these benefits to a two port SRAM cell.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Mathur to the teachings of Liaw to produce a two port SRAM cell with buried bit lines.
Regarding Claim 2, Liaw and Mathur teach the limitations of Claim 1. Liaw further teaches wherein
the 2-port SRAM cell (Fig 2A: Cell-1) further comprises:
a third interconnect (Fig. 2B: M1-Vdd) formed in a second interconnect layer (Fig. 2A: M1) below the first interconnect layer (Fig. 2B: M2), and connected to the first power source (Fig. 1: CVdd), and extending in the first direction (Fig. 1: y); and
a fourth interconnect (Fig. 2B: M1-Vss) formed in the second interconnect layer (Fig. 2A: M1), and connected to the second power source (Fig. 1: CVss), and extending in the first direction (Fig. 1: y).
Regarding Claim 4, Liaw and Mathur teach the limitations of Claim 2. Mathur further teaches wherein part of the fourth interconnect (Fig. 4: M_INT) overlaps with at least one of the first or second buried interconnects (Fig. 4: BUT BL Wire) in plan view.
Regarding Claim 5, , Liaw and Mathur teach the limitations of Claim 2. Liaw further teaches wherein the read-bit line (Fig. 1: R-BL) has a fifth interconnect formed (Fig. 2A: M1-R-BL) in the second interconnect layer (Fig. 2A: M1) and extending in the first direction (Fig. 2A: y).
Regarding Claim 6, Liaw and Mathur teach the limitations of Claim 2. Mathur further teaches wherein the read-bit line has a third buried interconnect formed in the buried interconnect layer and extending in the first direction. (para 41 “In some implementations, a memory device may include a single port that allows a single read-write access per cycle time, or the memory device may be multi-ported so as to allow multiple simultaneous read-write accesses, for example e.g., two-port SRAM allows for simultaneous read-write access, and dual-port SRAM allows for simultaneous read-write access (e.g., up to two simultaneous reads, two simultaneous writes, or a simultaneous read and write). For instance, SRAM with N-ports may support N-simultaneous accesses. Also, SRAM with multiple ports may have multiple groups of wordline wires and multiple groups of bitline wires. Therefore, in some instances, the memory device may have multiple groups of bitline wires and multiple groups of wordline wires, wherein one or more bitline wires and/or one or more wordline wires may be buried according to aspects of this disclosure.”)
Regarding Claim 7, Liaw and Mathur teach the limitations of Claim 1. Mathur further teaches wherein the 2-port SRAM cell (para 41) further includes:
a second buried power rail (Fig. 2: VSS (BM0)) formed in the buried interconnect layer (Fig. 2: M_BUR), and connected to the second power source (Fig. 2: VSS), and extending in the first direction; and
a third interconnect (Fig. 2: VDD) formed in a second interconnect layer (Fig. 2: M_INT) which is an interconnect layer between the buried interconnect layer (Fig. 2: M_BUR) and the first interconnect layer (Fig. 2: M2), and connected to the first power source (Fig. 2: VDD), and extending in the first direction.
Regarding Claim 8, Liaw and Mathur teach the limitations of Claim 7. Liaw further teaches wherein the read-bit line (Fig. 1: R-BL) has a fourth interconnect (Fig. 2A: M1-R-BL) formed in the second interconnect layer (Fig. 2A: M1) and extending in the first direction (Fig. 1: y).
Regarding Claim 10, Liaw and Mathur teach the limitations of Claim 7. Liaw teaches that power rails (Fig. 2B: M2-Vdd) are shared with a 2-port SRAM cell (Fig. 2B: Cell-1) arranged adjacent to the 2-port SRAM cell (Fig. 2B: Cell-2) in the second direction (Fig. 2B: x).
Regarding Independent Claim 11, Liaw teaches a semiconductor storage device including a 2-port SRAM cell (Fig. 2A: Cell-1),
the 2-port SRAM cell (Fig. 2A: Cell-1) comprising:
a first transistor (Fig. 1: W-PU-2) having nodes, one of which is connected to a first power source (Fig. 2: CVdd) that supplies a first voltage and the other one of which is connected to a first node (Fig. 1: 110), and having a gate connected to a second node (Fig. 1: 112);
a second transistor (Fig. 1: W-PU-1) having nodes, one of which is connected to the first power source (Fig. 2: CVdd) and the other one of which is connected to the second node (Fig. 1: 112), and having a gate connected to the first node (Fig. 1: 110);
a third transistor (Fig. 1: W-PD2) having nodes, one of which is connected to the first node (Fig. 1: 110) and the other one of which is connected to a second power source (Fig. 2: CVss) that supplies a second voltage (Fig. 2: CVss) different from the first voltage (Fig. 2: CVdd), and having a gate connected to the second node (Fig. 1: 112);
a fourth transistor (Fig. 1: W-PD1) having nodes, one of which is connected to the second node (Fig. 1: 112) and the other one of which is connected to the second power source (Fig. 2: CVss), and having a gate connected to the first node (Fig. 1: 110);
a fifth transistor (Fig. 1: W-PG1) having nodes, one of which is connected to a first write-bit line (Fig. 1: W-BL) and the other one of which is connected to the first node (Fig. 1: 112), and having a gate connected to a write-word line (Fig. 1: WWL);
a sixth transistor (Fig. 1: W-PG2) having nodes, one of which is connected to a second write-bit line (Fig. 1: W-W-BL-BAR) forming a complementary bit line pair together with the first write-bit line (Fig. 1: W-BL) and the other one of which is connected to the second node (Fig. 1: 110), and having a gate connected to the write-word line (Fig. 1: WWL);
a seventh transistor (Fig. 1: RW-PD) having one node connected to the second power source (Fig. 2: CVdd) and a gate connected to the second node (Fig. 1: 112); and
an eighth transistor (Fig. 1: RW-PG) having nodes, one of which is connected to the other node of the seventh transistor (Fig. 1: RW-PD) and the other one of which is connected to a read-bit line (Fig. 1: RW-BL), and having a gate connected to a read-word line (Fig. 1: RWL),
the write-word line (Fig. 2B: M2-W-WL) having a first interconnect formed in a first interconnect layer (Fig. 2B: M2) and extending in a second direction perpendicular to the first direction (Fig. 2B: x).
the read-word line (Fig. 2B: M2-R-WL) having a second interconnect (Fig. 2B: M2) formed in the first interconnect layer and extending in the second direction (Fig. 2B: x).
Liaw fails to teach buried bit line interconnect structures.
the 2-port SRAM cell (para 41) further including a second buried power rail (Fig. 2: VSS (BM0)) formed in a buried interconnect layer, connected to the second power source (Fig. 5: VSS), and extending in the first direction,
Mathur teaches the first write-bit line (Fig. 2: BL) having a first buried interconnect formed in a buried interconnect layer (Fig. 2: BM0) and extending in a first direction,
the second write-bit line (Fig. 2: NBL) having a second buried interconnect formed in the buried interconnect layer (Fig. 2: BM0) and extending in the first direction,
Mathur states in paragraphs 9-10 “the buried signal wires may be disposed within the substrate of an integrated circuit, wherein the buried signal wires may reduce congestion of metal routing layers. The buried signal wires may also provide lower resistance and/or lower capacitance memory signal routing when compared with traditional non-buried wires, thereby decreasing signal delay and energy consumption. Also, using buried signal wires in memory devices may have a significant impact on memory performance by simultaneously reducing memory access time, improving cycle time, reducing dynamic energy consumption and also increasing memory density. In addition, as the buried signal wire layer is less congested, the signals may be wider and/or disposed further apart to reduce resistance. In some instances, resistance of the wires may be further reduced by making the buried signal wire layer taller, and buried signal wires may be applied to unidirectional and non-unidirectional signals. In various implementations, buried signal wires may have lower capacitance and resistance, due to reduced signal coupling, when compared to similar non-buried signal wires of the same wire width. Also, various other critical signal wires for memory wordlines, bitlines and/or clock signals may be implemented as buried signal wires so as to provide improved memory performance and lower energy consumption when compared to implementing non-buried signal wires that use traditional above-substrate connectivity.” Given these numerous benefits to implementing buried wires and signal lines it would be obvious to apply these benefits to a two port SRAM cell.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Mathur to the teachings of Liaw to produce a two port SRAM cell with buried bit lines.
Regarding Claim 12, Liaw and Mathur teach the limitations of Claim 11. This claim is rejected for the same reasons as claim 5.
Regarding Claim 14, Liaw and Mathur teach the limitations of Claim 11. Mathur further teaches a first buried power rail formed in the buried interconnect layer, connected to the first power source, and extending in the first direction. (para 20 “Also, the multiple signal wires may include at least one power signal line (e.g., VSS, VDD) that is buried within the substrate 206 for transmitting power signals (e.g., VSS/VDD signals) to the memory cell structure (e.g., 210).”)
Regarding Claim 15, Liaw and Mathur teach the limitations of Claim 11. Liaw further teaches a sixth interconnect (Fig. 2A: M1-Vdd) formed in the second interconnect layer (Fig. 2A: M1) , connected to the first power source (Fig. 1: CVdd) , and extending in the first direction (Fig. 2A: y).
Regarding Claim 16, Liaw and Mathur teach the limitations of Claim 16. Liaw further teaches the sixth interconnect (Fig. 2A: M1-Vdd) is disposed between the first (Fig. 2A: M1-W-WL) and second interconnects (Fig. 2A: M1-R-WL; The figures are mislabeled with two M1-R-BL see para 28 “The gate electrode layer 220 is connected to an overlying level (e.g., the read word-line M1-R-WL) through a gate via 250”).
Allowable Subject Matter
Claims 3, 8, and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 3 requires the limitations that different interconnect structures in one layer are wider than the buried interconnects. Neither Liaw nor Mathur teach that relative widths of interconnects in different metal layers. Therefore, this claim would be allowable if written in independent form.
Claim 9 and Claim 13 would be allowable for the same reasons as claim 3. Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Paul et al. (US 20200035686 A1) teaches a two port SRAM cell that has a buried VSS power rail.
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825