DETAILED ACTION
This application is responsive to the following: Remarks made in amendment and English language translation of foreign priority documents filed on June 8, 2026.
Claims 1-16 are pending. Claims 1 and 11 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
The amendment to specification filed on June 8th, 2026 is entered. The amendment overcomes the objection set forth in the previous non-final office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-8, 10-12, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 20140153323 A1) in view of Mathur et al (US 20230354571 A1).
Regarding Independent Claim 1, Liaw teaches a semiconductor storage device including a 2-port SRAM cell (Fig. 9: 10’),
the 2-port SRAM cell (Fig. 9: 10’) comprising:
a first transistor (Fig. 10: PU-2) having nodes, one of which is connected to a first power source (Fig. 10: CVdd) that supplies a first voltage and the other one of which is connected to a first node (Fig. 10: Storage Node 110), and having a gate connected to a second node (Fig. 10: Storage Node 112);
a second transistor (Fig. 10: PU-1) having nodes, one of which is connected to the first power source (Fig. 10: CVdd) and the other one of which is connected to the second node (Fig. 10: Storage Node 112), and having a gate connected to the first node (Fig. 10: Storage Node 110);
a third transistor (Fig. 9: PD-2) having nodes, one of which is connected to the first node (Fig. 10: Storage Node 110) and the other one of which is connected to a second power source (Fig. 10: CVss) that supplies a second voltage (Fig. 10: CVss) different from the first voltage (Fig. 10: CVdd), and having a gate connected to the second node (Fig. 10: Storage Node 112);
a fourth transistor (Fig. 9: PD-1) having nodes, one of which is connected to the second node (Fig. 10: Storage Node 112) and the other one of which is connected to the second power source (Fig. 10: CVss), and having a gate connected to the first node (Fig. 10: Storage Node 110);
a fifth transistor (Fig. 9: W_PG-1) having nodes, one of which is connected to a first write-bit line (Fig. 9: W-BL) and the other one of which is connected to the first node (Fig. 10: Storage Node 112), and having a gate connected to a write-word line (Fig. 9: W-WL);
a sixth transistor (Fig. 9: W_PG-2) having nodes, one of which is connected to a second write-bit line (Fig. 9: W-BLB) forming a complementary bit line pair together with the first write-bit line (Fig. 9: W-BL) and the other one of which is connected to the second node (Fig. 10: Storage Node 110), and having a gate connected to the write-word line (Fig. 9: W-WL);
a seventh transistor (Fig. 9: R_PU) having one node connected to the second power source (Fig. 10: CVdd) and a gate connected to the second node (Fig. 10: Storage Node 112); and
an eighth transistor (Fig. 9: R_PG) having nodes, one of which is connected to the other node of the seventh transistor (Fig. 9: R_PU) and the other one of which is connected to a read-bit line (Fig. 9: R-BL), and having a gate connected to a read-word line (Fig. 9: RWL),
the write-word line (Fig. 18: W-WL; para 43 “The write word-line W-WL and the read word-line R-WL may be allocated in metal layer M2”) having a first interconnect formed in a first interconnect layer and extending in a second direction perpendicular to the first direction (Fig. 18: L3).
the read-word line (Fig. 18: R-WL; para 43 “The write word-line W-WL and the read word-line R-WL may be allocated in metal layer M2”) having a second interconnect formed in the first interconnect layer and extending in the second direction (Fig. 18: L3).
Liaw fails to teach buried bit line interconnect structures.
Mathur teaches the first write-bit line (Fig. 2: BL) having a first buried interconnect formed in a buried interconnect layer (Fig. 2: BM0) and extending in a first direction,
the second write-bit line (Fig. 2: NBL) having a second buried interconnect formed in the buried interconnect layer (Fig. 2: BM0) and extending in the first direction,
Mathur states in paragraphs 9-10 “the buried signal wires may be disposed within the substrate of an integrated circuit, wherein the buried signal wires may reduce congestion of metal routing layers. The buried signal wires may also provide lower resistance and/or lower capacitance memory signal routing when compared with traditional non-buried wires, thereby decreasing signal delay and energy consumption. Also, using buried signal wires in memory devices may have a significant impact on memory performance by simultaneously reducing memory access time, improving cycle time, reducing dynamic energy consumption and also increasing memory density. In addition, as the buried signal wire layer is less congested, the signals may be wider and/or disposed further apart to reduce resistance. In some instances, resistance of the wires may be further reduced by making the buried signal wire layer taller, and buried signal wires may be applied to unidirectional and non-unidirectional signals. In various implementations, buried signal wires may have lower capacitance and resistance, due to reduced signal coupling, when compared to similar non-buried signal wires of the same wire width. Also, various other critical signal wires for memory wordlines, bitlines and/or clock signals may be implemented as buried signal wires so as to provide improved memory performance and lower energy consumption when compared to implementing non-buried signal wires that use traditional above-substrate connectivity.” Given these numerous benefits to implementing buried wires and signal lines it would be obvious to apply these benefits to a two port SRAM cell.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Mathur to the teachings of Liaw to produce a two port SRAM cell with buried bit lines.
Regarding Claim 2, Liaw and Mathur teach the limitations of Claim 1. Liaw further teaches wherein
the 2-port SRAM cell (Fig. 18: 10’) further comprises:
a third interconnect (Para 43 “In accordance with some embodiments, lines CVss-line, W-BL, W-BLB, CVdd-line-1, and CVdd-line-2 are in metal layer M1”) formed in a second interconnect layer (Fig 4: M1)below the first interconnect layer (Fig. 4: M2), and connected to the first power source (Fig. 10: CVdd), and extending in the first direction (Fig. 18: W3); and
a fourth interconnect (Para 43 “In accordance with some embodiments, lines CVss-line, W-BL, W-BLB, CVdd-line-1, and CVdd-line-2 are in metal layer M1”) formed in the second interconnect layer (Fig. 4: M1), and connected to the second power source (Fig. 10: CVss), and extending in the first direction (Fig. 18: W3).
Regarding Claim 4, Liaw and Mathur teach the limitations of Claim 2. Mathur further teaches wherein part of the fourth interconnect (Fig. 4: M_INT) overlaps with at least one of the first or second buried interconnects (Fig. 4: BUT BL Wire) in plan view.
Regarding Claim 5, , Liaw and Mathur teach the limitations of Claim 2. Liaw further teaches wherein the read-bit line (Fig. 9: R-BL) has a fifth interconnect formed (Fig. Fig. 18: R-BL) in the second interconnect layer (Fig. 4: M1) and extending in the first direction (Fig. 18: W3).
Regarding Claim 6, Liaw and Mathur teach the limitations of Claim 2. Mathur further teaches wherein the read-bit line has a third buried interconnect formed in the buried interconnect layer and extending in the first direction. (para 41 “In some implementations, a memory device may include a single port that allows a single read-write access per cycle time, or the memory device may be multi-ported so as to allow multiple simultaneous read-write accesses, for example e.g., two-port SRAM allows for simultaneous read-write access, and dual-port SRAM allows for simultaneous read-write access (e.g., up to two simultaneous reads, two simultaneous writes, or a simultaneous read and write). For instance, SRAM with N-ports may support N-simultaneous accesses. Also, SRAM with multiple ports may have multiple groups of wordline wires and multiple groups of bitline wires. Therefore, in some instances, the memory device may have multiple groups of bitline wires and multiple groups of wordline wires, wherein one or more bitline wires and/or one or more wordline wires may be buried according to aspects of this disclosure.”)
Regarding Claim 7, Liaw and Mathur teach the limitations of Claim 1. Mathur further teaches wherein the 2-port SRAM cell (para 41) further includes:
a second buried power rail (Fig. 2: VSS (BM0)) formed in the buried interconnect layer (Fig. 2: M_BUR), and connected to the second power source (Fig. 2: VSS), and extending in the first direction; and
a third interconnect (Fig. 2: VDD) formed in a second interconnect layer (Fig. 2: M_INT) which is an interconnect layer between the buried interconnect layer (Fig. 2: M_BUR) and the first interconnect layer (Fig. 2: M2), and connected to the first power source (Fig. 2: VDD), and extending in the first direction.
Regarding Claim 8, Liaw and Mathur teach the limitations of Claim 7. Liaw further teaches wherein the read-bit line (Fig. 9: R-BL) has a fourth interconnect (Fig. 4: M1-R-BL) formed in the second interconnect layer (Fig 4: M1)and extending in the first direction (Fig. 18: W3).
Regarding Claim 10, Liaw and Mathur teach the limitations of Claim 7. Liaw teaches that power rails (Fig. 4: M2-Vdd) are shared with a 2-port SRAM cell (Fig. 18: 10’) arranged adjacent to the 2-port SRAM cell (Fig. 18: 10’) in the second direction (Fig. 18: L3).
Regarding Independent Claim 11, Liaw teaches a semiconductor storage device including a 2-port SRAM cell (Fig. 9: 10’),
the 2-port SRAM cell (Fig. 9: 10’) comprising:
a first transistor (Fig. 10: PU-2) having nodes, one of which is connected to a first power source (Fig. 10: CVdd) that supplies a first voltage and the other one of which is connected to a first node (Fig. 10: Storage Node 110), and having a gate connected to a second node (Fig. 10: Storage Node 112);
a second transistor (Fig. 10: PU-1) having nodes, one of which is connected to the first power source (Fig. 10: CVdd) and the other one of which is connected to the second node (Fig. 10: Storage Node 112), and having a gate connected to the first node (Fig. 10: Storage Node 110);
a third transistor (Fig. 9: PD-2) having nodes, one of which is connected to the first node (Fig. 10: Storage Node 110) and the other one of which is connected to a second power source (Fig. 10: CVss) that supplies a second voltage (Fig. 10: CVss) different from the first voltage (Fig. 10: CVdd), and having a gate connected to the second node (Fig. 10: Storage Node 112);
a fourth transistor (Fig. 9: PD-1) having nodes, one of which is connected to the second node (Fig. 10: Storage Node 112) and the other one of which is connected to the second power source (Fig. 10: CVss), and having a gate connected to the first node (Fig. 10: Storage Node 110);
a fifth transistor (Fig. 9: W_PG-1) having nodes, one of which is connected to a first write-bit line (Fig. 9: W-BL) and the other one of which is connected to the first node (Fig. 10: Storage Node 112), and having a gate connected to a write-word line (Fig. 9: W-WL);
a sixth transistor (Fig. 9: W_PG-2) having nodes, one of which is connected to a second write-bit line (Fig. 9: W-BLB) forming a complementary bit line pair together with the first write-bit line (Fig. 9: W-BL) and the other one of which is connected to the second node (Fig. 10: Storage Node 110), and having a gate connected to the write-word line (Fig. 9: W-WL);
a seventh transistor (Fig. 9: R_PU) having one node connected to the second power source (Fig. 10: CVdd) and a gate connected to the second node (Fig. 10: Storage Node 112); and
an eighth transistor (Fig. 9: R_PG) having nodes, one of which is connected to the other node of the seventh transistor (Fig. 9: R_PU) and the other one of which is connected to a read-bit line (Fig. 9: R-BL), and having a gate connected to a read-word line (Fig. 9: RWL),
the write-word line (Fig. 18: W-WL; para 43 “The write word-line W-WL and the read word-line R-WL may be allocated in metal layer M2”) having a first interconnect formed in a first interconnect layer and extending in a second direction perpendicular to the first direction (Fig. 18: L3).
the read-word line (Fig. 18: R-WL; para 43 “The write word-line W-WL and the read word-line R-WL may be allocated in metal layer M2”) having a second interconnect formed in the first interconnect layer and extending in the second direction (Fig. 18: L3).
Liaw fails to teach buried bit line interconnect structures.
the 2-port SRAM cell (para 41) further including a second buried power rail (Fig. 2: VSS (BM0)) formed in a buried interconnect layer, connected to the second power source (Fig. 5: VSS), and extending in the first direction,
Mathur teaches the first write-bit line (Fig. 2: BL) having a first buried interconnect formed in a buried interconnect layer (Fig. 2: BM0) and extending in a first direction,
the second write-bit line (Fig. 2: NBL) having a second buried interconnect formed in the buried interconnect layer (Fig. 2: BM0) and extending in the first direction,
Mathur states in paragraphs 9-10 “the buried signal wires may be disposed within the substrate of an integrated circuit, wherein the buried signal wires may reduce congestion of metal routing layers. The buried signal wires may also provide lower resistance and/or lower capacitance memory signal routing when compared with traditional non-buried wires, thereby decreasing signal delay and energy consumption. Also, using buried signal wires in memory devices may have a significant impact on memory performance by simultaneously reducing memory access time, improving cycle time, reducing dynamic energy consumption and also increasing memory density. In addition, as the buried signal wire layer is less congested, the signals may be wider and/or disposed further apart to reduce resistance. In some instances, resistance of the wires may be further reduced by making the buried signal wire layer taller, and buried signal wires may be applied to unidirectional and non-unidirectional signals. In various implementations, buried signal wires may have lower capacitance and resistance, due to reduced signal coupling, when compared to similar non-buried signal wires of the same wire width. Also, various other critical signal wires for memory wordlines, bitlines and/or clock signals may be implemented as buried signal wires so as to provide improved memory performance and lower energy consumption when compared to implementing non-buried signal wires that use traditional above-substrate connectivity.” Given these numerous benefits to implementing buried wires and signal lines it would be obvious to apply these benefits to a two port SRAM cell.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Mathur to the teachings of Liaw to produce a two port SRAM cell with buried bit lines.
Regarding Claim 12, Liaw and Mathur teach the limitations of Claim 11. This claim is rejected for the same reasons as claim 5.
Regarding Claim 14, Liaw and Mathur teach the limitations of Claim 11. Mathur further teaches a first buried power rail formed in the buried interconnect layer, connected to the first power source, and extending in the first direction. (para 20 “Also, the multiple signal wires may include at least one power signal line (e.g., VSS, VDD) that is buried within the substrate 206 for transmitting power signals (e.g., VSS/VDD signals) to the memory cell structure (e.g., 210).”)
Regarding Claim 15, Liaw and Mathur teach the limitations of Claim 11. Liaw further teaches a sixth interconnect (Fig. 4: M1-Vdd) formed in the second interconnect layer (Fig 4: M1), connected to the first power source (Fig. 10: CVdd) , and extending in the first direction (Fig. 18: W3).
Regarding Claim 16, Liaw and Mathur teach the limitations of Claim 16. Liaw further teaches the sixth interconnect (Fig. 4: M1-Vdd) is disposed between the first (Fig. 4: M1-W-WL) and second interconnects (Fig. 4: M1-R-WL; The figures are mislabeled with two M1-R-BL see para 28 “The gate electrode layer 220 is connected to an overlying level (e.g., the read word-line M1-R-WL) through a gate via 250”).
Allowable Subject Matter
Claims 3, 8, and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 3 requires the limitations that different interconnect structures in one layer are wider than the buried interconnects. Neither Liaw nor Mathur teach that relative widths of interconnects in different metal layers. Therefore, this claim would be allowable if written in independent form.
Claim 9 and Claim 13 would be allowable for the same reasons as claim 3.
Response to Arguments
Applicant’s arguments with respect to claims 1-2, 4-8, 10-12, and 14-16 have been considered but are moot because the new ground of rejection.
Applicant correctly perfected their foreign priority claim. However, a new rejection under 35 U.S.C. 103, using prior art with an older effective filing date, has been applied. Therefore, the rejection of these claims is maintained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/Donald HB Braswell/Primary Examiner, Art Unit 2825
Prosecution Insights