DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Claims 2-7 and 17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 25 November 2025.
Applicant’s election without traverse of Species II, corresponding to originally filed Figures 11 and 12 and originally filed Claims 1 and 8-16, in the reply filed on 25 November 2025 is acknowledged.
Upon further consideration of the claimed invention in view of the originally filed disclosure, it should be noted that dependent Claims 13 and 14 are not directed to the elected embodiment of Figures 11 and 12. Rather, Claims 13 and 14 are directed to the structural and/or functional embodiment of the “selection signal generator” of Figure 15, which is distinct from the structural and/or functional embodiment of the “selection signal generator” of elected Figure 12. Specifically, while Claims 11 through 14 all depend from Claim 10, Claims 13 and 14, directed to Figure 15, require claimed “transistors” and “control signals” that are structurally and functionally distinct from the claimed “transistors” and “control signals” of Claims 11 and 12, directed to Figure 12.
However, because the Requirement for Restriction / Election mailed 25 September 2025 noted Claims 1 and 8-16 as belonging to Species II, and Claims 13 and 14 do not present a serious search and/or examination burden, Species II is further interpreted as incorporating Figures 11, 12, and 15, and Claims 13 and 14 are examined as part of Species II.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8-9, and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shin et al. (hereinafter “Shin” US 2022 / 0399529).
As pertaining to Claim 1, Shin discloses (see Fig. 1, Fig. 3, and Fig. 12) a display device (100), comprising:
a display panel (10) including an active area (i.e., a display and driving area; see (20, 30, 40, 10)) and a non-active area (i.e., any non-display or non-driving area) adjacent to the active area (again, see (20, 30, 40, 10)), and including a plurality of pixels (110) and a plurality of selection signal generators (20, 30) disposed in the active area (again, see (20, 30, 40, 10); see Page 3 through Page 4, Para. [0055]-[0064], Para. [0065]-[0066], and Para. [0068]-[0069]); and
a timing controller (40) configured to control the display panel (10),
wherein each of the plurality of pixels (110) includes (see Fig. 12):
a first light emitting element (OLED1);
a first optical member (Lz1) configured to refract light from the first light emitting element (OLED1);
a second light emitting element (OLED2) configured to emit light of a same color as the first light emitting element (OLED1); and
a second optical member (Lz2) configured to refract the light from the second light emitting element (OLED2) and having a different shape from the first optical member (Lz1), and
wherein each of the plurality of selection signal generators (20, 30) controls any one of the first light emitting element (OLED1) and the second light emitting element (OLED2) included in at least one corresponding pixel (101) among the plurality of pixels (101) to emit light (see Page 7, Para. [0128]-[0130]; and Page 10 through Page 11, Para. [0201]-[0202], Para. [0204]-[0212], Para. [0216]-[0218], and Para. [0220]-[0226]).
As pertaining to Claim 8, Shin discloses (see Fig. 1, Fig. 3, and Fig. 12) that each of the plurality of pixels (110) includes:
a driving transistor (Tdr) configured to generate a first driving current that flows from a high-potential power line (ELVDD) configured to provide a high-potential power voltage (i.e., (ELVDD)) to a low-potential power line (VSS) configured to provide a low-potential power voltage (i.e., (VSS)) through the first light emitting element (OLED1), and a second driving current that flows from the high-potential power line (ELVDD) to the low-potential power line (VSS) through the second light emitting element (OLED2);
a third selection transistor (T4) connected between the driving transistor (Tdr) and the first light emitting element (OLED1), and configured to be turn on in response to a selection signal (VGL, VGH) supplied to a selection signal line (EM2); and
a fourth selection transistor (T6) connected between the driving transistor (Tdr) and the second light emitting element (OLED2), and configured to be turn on in response to the selection signal (i.e., (VGL, VGH); see Page 10 Para. [0204]-[0212], Para. [0216]-[0218]; and Page 11, Para. [0220]-[0226] and [0230]).
As pertaining to Claim 9, Shin discloses (see Fig. 1, Fig. 3, and Fig. 12) that the third selection transistor (T4) is an n-type transistor and the fourth selection transistor (T6) is a p-type transistor (see Page 10, Para. [0203] and note that any one of (T1) through (T7) can be an n-type transistor while each of the remaining (T1) through (T7) is a p-type).
As pertaining to Claim 15, Shin discloses (see Fig. 1, Fig. 3, and Fig. 12) that each of the plurality of selection signal generators (20, 30) controls any one of the first light emitting element (OLED1) and the second light emitting element (OLED2) included in one pixel (110) of the plurality of pixels (110) to emit light (see Page 10, Para. [0204]-[0212] and Page 11, Para. [0220]-[0226]).
As pertaining to Claim 16, Shin discloses (see Fig. 1, Fig. 3, and Fig. 12) that each of the plurality of selection signal generators (20, 30) controls any one of the first light emitting element (OLED1) and the second light emitting element (OLED2) included in each of at least two pixels (110) of the plurality of pixels (110) to emit light (see Page 10, Para. [0204]-[0212] and Page 11, Para. [0220]-[0226]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Eom (US 2016 / 0086549).
As pertaining to Claim 10, Shin discloses (see Fig. 1, Fig. 3, and Fig. 12) that each of the plurality of selection signal generators (20, 30) outputs the selection signal (VGL, VGH) having a high level (VGH) or low level (VGL; see Page 10 Para. [0204]-[0212], Para. [0216]-[0218]; and Page 11, Para. [0220]-[0226] and [0230]).
Shin does not explicitly provide a detailed description of the structural and/or functional features of the selection signal generators. That is, Shin does not explicitly disclose that the output of the selection signal is based on a first control signal, a second control signal, a third control signal, a fourth control signal, a first power voltage, and a second power voltage.
However, in the same field of endeavor, Eom discloses (see Fig. 2A and Fig. 3A) that it was well-known in the art before the effective filing date of the claimed invention to implement a selection signal generator (200) that provides a selection signal (VGL, VGH), having a high level (VGH) or low level (VGL), to a selection signal line (EMIT1) to turn on a selection transistor (TE) based on a first control signal (i.e., (CS3)), a second control signal (i.e., (CLK2)), a third control signal (i.e., (CS4)), a fourth control signal (i.e., (CLK1)), a first power voltage (VGL), and a second power voltage (VGH; see Page 4, Para. [0063]-[0064]; and Page 5, Para. [0075]). Eom discloses a means for controlling the output to a selection signal line to turn on a selection transistor that is analogous to that of Shin. Furthermore, it is a goal of Eom to provide an effective means for initiating selective light-emission in a display panel comprising individually addressable light emitting elements that prevents image defects from occurring (see Page 1, Para. [0006]-[0009]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Shin with the teachings of Eom, such that the structural and/or functional features of the selection signal generators of Shin include the output of the selection signal based on a first control signal, a second control signal, a third control signal, a fourth control signal, a first power voltage, and a second power voltage, as suggested by Eom, in order to provide an effective means for initiating selective light-emission in a display panel comprising individually addressable light emitting elements that prevents image defects from occurring.
As pertaining to Claim 11, Eom discloses (see Fig. 3A) that each of the plurality of selection signal generators (200) includes:
a ninth transistor (i.e., see the transistor between (VGH) and (EMIT1)) connected between a second power voltage line (VGH) that provides the second power voltage (VGH) and a third output node (EMIT1), and configured to be turn on in response to the first control signal (i.e., the gate voltage (CS3));
a tenth transistor (i.e., see the transistor connected at (CS3) having a gate connected to (CLK2)) connected between the second power voltage line (VGH) and the third output node (EMIT1), and configured to be turn on in response to the second control signal (CLK2);
an eleventh transistor (i.e., see the transistor between (VGL) and (EMIT1)) connected between the third output node (EMIT1) and a first power voltage line (VGL) that provides the first power voltage (VGL), and configured to be turn on in response to the third control signal (i.e., the gate voltage (CS4)); and
a twelfth transistor (i.e., see the transistor connected at (VGL) having a gate connected to (CLK1)) connected between the eleventh transistor (i.e., see the transistor between (VGL) and (EMIT1)) and the first power voltage line (VGL), and configured to be turn on in response to the fourth control signal (i.e., the gate voltage (CLK1); again, see Page 4, Para. [0063]-[0064]; and Page 5, Para. [0075]).
As pertaining to Claim 12, Eom discloses (see Fig. 3A) that each of the plurality of selection signal generators (200) includes:
wherein the ninth transistor (i.e., see the transistor between (VGH) and (EMIT1)) and the tenth transistor (i.e., see the transistor connected at (CS3) having a gate connected to (CLK2)) are connected in parallel between the second power voltage line (VGH) and the third output node (EMIT1; see Fig. 3A and note that the ninth and tenth transistors each have a source/drain terminal electrically connected at (VGH) and a source/drain terminal electrically connected at (EMIT1)), and
the eleventh transistor (i.e., see the transistor between (VGL) and (EMIT1)) and the twelfth transistor (i.e., see the transistor connected at (VGL) having a gate connected to (CLK1)) are connected in series between the first power voltage line (VGL) and the third output node (EMIT1; see Fig. 3A and note that the eleventh and twelfth transistors each have a source/drain terminal electrically connected at (VGL) and are connected in series to (EMIT1); again, see Page 4, Para. [0063]-[0064]; and Page 5, Para. [0075]).
Claim 10 is additionally rejected and Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Shin in view of Eom.
As pertaining to Claim 10, Shin discloses (see Fig. 1, Fig. 3, and Fig. 12) that each of the plurality of selection signal generators (20, 30) outputs the selection signal (VGL, VGH) having a high level (VGH) or low level (VGL; see Page 10 Para. [0204]-[0212], Para. [0216]-[0218]; and Page 11, Para. [0220]-[0226] and [0230]).
Shin does not explicitly provide a detailed description of the structural and/or functional features of the selection signal generators. That is, Shin does not explicitly disclose that the output of the selection signal is based on a first control signal, a second control signal, a third control signal, a fourth control signal, a first power voltage, and a second power voltage.
However, in the same field of endeavor, Eom discloses (see Fig. 2A and Fig. 3A) that it was well-known in the art before the effective filing date of the claimed invention to implement a selection signal generator (200) that provides a selection signal (VGL, VGH), having a high level (VGH) or low level (VGL), to a selection signal line (EMIT1) to turn on a selection transistor (TE) based on a first control signal (i.e., (CS3)), a second control signal (i.e., (CLK2)), a third control signal (i.e., (CLK1)), a fourth control signal (i.e., (CS4)), a first power voltage (VGH), and a second power voltage (VGL; see Page 4, Para. [0063]-[0064]; and Page 5, Para. [0075]). Eom discloses a means for controlling the output to a selection signal line to turn on a selection transistor that is analogous to that of Shin. Furthermore, it is a goal of Eom to provide an effective means for initiating selective light-emission in a display panel comprising individually addressable light emitting elements that prevents image defects from occurring (see Page 1, Para. [0006]-[0009]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Shin with the teachings of Eom, such that the structural and/or functional features of the selection signal generators of Shin include the output of the selection signal based on a first control signal, a second control signal, a third control signal, a fourth control signal, a first power voltage, and a second power voltage, as suggested by Eom, in order to provide an effective means for initiating selective light-emission in a display panel comprising individually addressable light emitting elements that prevents image defects from occurring.
As pertaining to Claim 13, Eom discloses (see Fig. 3A) that each of the plurality of selection signal generators (200) includes:
a thirteenth transistor (i.e., see the transistor between (VGL) and (EMIT1)) connected between a second power voltage line (VGL) that provides the second power voltage (VGL) and a fourth output node (EMIT1), and configured to be turn on in response to the fourth control signal (i.e., the gate voltage (CS4));
a fourteenth transistor (i.e., see the transistor connected at (VGL) having a gate connected to (CLK1)) connected between the thirteenth transistor (i.e., see the transistor between (VGL) and (EMIT1)) and the fourth output node (EMIT1), and configured to be turn on in response to the third control signal (CLK1);
a fifteenth transistor (i.e., see the transistor between (VGH) and (EMIT1)) connected between the fourth output node (EMIT1) and a first power voltage line (VGH) configured to provide the first power voltage (VGH), and configured to be turn on in response to the first control signal (i.e., the gate voltage (CS3)); and
a sixteenth transistor (i.e., see the transistor connected at (CS3) having a gate connected to (CLK2)) connected between the fourth output node (EMIT1) and the first power voltage line (VGH), and configured to be turn on in response to the second control signal (CLK2; again, see Page 4, Para. [0063]-[0064]; and Page 5, Para. [0075]).
As pertaining to Claim 14, Eom discloses (see Fig. 3A) that each of the plurality of selection signal generators (200) includes:
wherein the thirteenth transistor (i.e., see the transistor between (VGL) and (EMIT1)) and the fourteenth transistor (i.e., see the transistor connected at (VGL) having a gate connected to (CLK1)) are connected in series between the second power voltage line (VGL) and the fourth output node (EMIT1; see Fig. 3A and note that the thirteenth and fourteenth transistors each have a source/drain terminal electrically connected at (VGL) and are connected in series to (EMIT1)), and
the fifteenth transistor (i.e., see the transistor between (VGH) and (EMIT1)) and the sixteenth transistor (i.e., see the transistor connected at (CS3) having a gate connected to (CLK2)) are connected in parallel between the first power voltage line (VGH) and the fourth output node (EMIT1; see Fig. 3A and note that the fifteenth and sixteenth transistors each have a source/drain terminal electrically connected at (VGH) and a source/drain terminal electrically connected at (EMIT1); again, see Page 4, Para. [0063]-[0064]; and Page 5, Para. [0075]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shikina et al. (US 2011 / 0284881) discloses a display panel having pixels comprising a first light emitting and a second light emitting element having a same color but different viewing angle characteristics.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON M MANDEVILLE whose telephone number is (571)270-3136. The examiner can normally be reached Mon - Fri 7:30AM-4:00PM.
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/JASON M MANDEVILLE/Primary Examiner, Art Unit 2623