DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/18/26 and 9/5/24 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 46, 48 are objected to because of the following informalities:
Applicant is advised that should claim 46 be found allowable, claim 48 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Appropriate correction is required.
Claim Rejections - 35 USC § 112 (Part I)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 57 and 58 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 57, the claim limitation of “a secondary power source” is unclear. It is not clear whether or not this is referring to the power source of claim 4 from which claim 57 depends.
Claim 58 is dependent on claim 58 and therefore inherits its deficiencies.
Claim Rejections - 35 USC § 112 (Part II)
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 14 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claim 13, from which claim 14 depends, discloses that the charging indicator is illuminated while AVT is charging. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-6, 27-30, 49-52, 54-56, 57, 58 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balid et al., US 2022/0120790 in view of Agarwal et al., US 20220037877
Regarding claim 4, Balid teaches an absence of voltage tester (AVT) for detecting absence of voltage (Title; absence of voltage detection) comprising: a housing assembly (¶[0025]; “indicate the presence of voltage via an indicator module that is mounted on the safe and isolated side of the equipment/panel”); analog circuitry electrically connected to a power source (Fig. 3, 9 -10; ¶[0028]; absence of voltage connected to power line); the analog circuitry configured to detect the absence of voltage (Figs. 9-11; function of absence of voltage detector ); the analog circuitry configured to detect connections to the power source (Fig. 15; “connectivity detection”); means for a user to initiate a test for the absence of voltage (¶[0025]; absence of voltage initiated by button); a supervisory test circuit within the analog circuitry (Fig. 3; test circuit and controller); a visual indicator within the analog circuitry to confirm the absence of voltage after an absence of voltage test has been performed (Fig. 2b; Yellow, green LEDs indicating voltage levels); a secondary power source operatively connected to the supervisory test circuit for powering the supervisory test circuit (¶[0026], “ a secondary power source (battery)”; claim 1; battery of absence of voltage detection device is checked and connected to the test circuit); and a circuit assembly for each phase connection that enables both a redundant continuity test and provide a reduced voltage power supply front end (¶[0060]; AVD checks voltage on each phase).
Balid is silent in a current limited power supply front end. Agarwal teaches a current limited power supply front end (Fig. 1; current limiter 10). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Agarwal into Balid for the benefit of reducing in-rush current to the components.
Regarding claim 1, Balid teaches wherein in a first mode of operation phase indication is provided using the plurality of phase indication lighting elements to show voltage present on each of the plurality of phase connections and continuity to each of the plurality of phase connections (Figs. 2a-2b; yellow and green leds used to show an absence or presence of voltage on each phase, See ¶[0060]); and wherein in a second mode of operation in response to initiation of the test sequence for the absence of voltage testing, the test sequence tests each of the plurality of phase connections and the supervisory test circuit activates the visual indicator if continuity testing of the AVT is successful while the secondary power source is used to energize the AVT (¶[0060], [0066], [0067]; Fig. 2a-2b; AVD circuit connectivity for installation failure or disconnection checked).
Regarding claim 2 and 3, Balid teaches wherein the circuitry assembly for each of the plurality of phase connections provides for voltage reduction. current limiting and wherein the current limiting is active current limiting. Agarwal teaches a circuitry assembly that provides for current limiting, wherein the current limiting is active current limiting (Fig. 1; current limiter 10) and wherein the active current limiting occurs prior to conversion to DC (¶[0049]; limiter 10 is between AC source and electrical equipment). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Agarwal into Balid for the benefit of reducing in-rush current to the components.
Regarding claim 5, Balid teaches wherein the visual indicator comprises a green lighting element and wherein the analog circuitry is configured to confirm the absence of voltage after the absence of voltage test has been performed by illuminating the green lighting element (Fig. 2b; if voltage is absent, green LED is on).
Regarding claim 6, Balid teaches wherein the analog circuitry is configured such that any voltage over a first threshold voltage is associated with voltage present and any voltage under the first threshold voltage is associated with the absence of voltage (¶[0060]-[0063]; Fig. 14; voltage above 2.95 considered hazardous/ unsafe).
Regarding claim 27, Balid teaches wherein the housing assembly comprises a face and wherein the visual indicator is visible at the face (¶[0025]; “indicate the presence of voltage via an indicator module that is mounted on the safe and isolated side of the equipment/panel”).
Regarding claim 28, Balid teaches wherein the power source comprises a single phase, two phase three phase AC power source ( ¶[0025]; ‘Single Phase or Multi-Phase”).
Regarding claim 29, Blaid teaches wherein the power source comprises of a DC power source ([0026]; battery).
Regarding claim 30, Balid teaches wherein the analog circuitry comprises a pair of voltage sense lead and continuity termination for each phase of the power source (Fig. 1; 2 leads connected to voltage detector).
Regarding claim 49, Balid is silent in wherein the analog circuitry is configured to perform the test and illuminate the visual indicator in under 1.5 seconds from the user initiating the test using the means for the user to initiate the test.
Regarding claim 50, Balid teaches the visual indicator is illuminated by providing a pulsing signal to an LED (Fig. 2a-2b; flashing leds).
Regarding claim 51, Balid teaches wherein in a first mode of operation phase indication is provided using a plurality of phase indication lighting elements to show voltage present on each of a plurality of phase connections and continuity to each of the plurality of phase connections (Fig. 1-2b).
Regarding claim 52, Balid teaches wherein in a second mode of operation in response to initiation of the test for the absence of voltage a continuity test is performed for each of the plurality of phase connections and the supervisory test circuit is configured to activate the visual indicator if the absence of voltage is determined for all of the phase connections (Fig. 1-2b).
Regarding claim 54, 55 and 56, Balid teaches a voltage reduction circuitry but is silent in wherein a circuitry assembly for each of the plurality of phase connections provides for current limiting, wherein the current limiting is active current limiting and wherein the active current limiting occurs prior to conversion to DC. Agarwal teaches a circuitry assembly that provides for current limiting and voltage reduction, wherein the current limiting is active current limiting (Fig. 1; current limiter 10) and wherein the active current limiting occurs prior to conversion to DC (¶[0049]; limiter 10 is between AC source and electrical equipment). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Agarwal into Balid for the benefit of reducing in-rush current to the components.
Regarding claim 57, Balid teaches a supervisory test circuit within the analog circuitry; a visual indicator within the analog circuitry to confirm the absence of voltage after an absence of voltage test has been performed with the supervisory test circuit; a visual indicator within the analog circuitry to confirm the absence of voltage after the absence of voltage test has been performed with the redundant supervisory circuit; a secondary power source operatively connected to the supervisory test circuit for powering the supervisory test circuit; and a circuit assembly for each phase connection that enables both a continuity test and provide reduced voltage power supply front end (same reasoning as that of claim 4 as the limitations are similar).. Balid is silent in a current limited power supply front end. Agarwal teaches a current limited power supply front end (Fig. 1; current limiter 10). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Agarwal into Balid for the benefit of reducing in-rush current to the components. Balid is silent in a redundant supervisory test circuit and visual indicator It would have been obvious to one having ordinary skill in the art at the time the invention was made to provide duplicate circuits, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. It would be within the level of ordinary skill in the art to provide redundancy so as to improve reliability of the system.
Regarding claim 58, Balid teaches wherein the visual indicator comprises a first green lighting element and wherein the analog circuitry is configured to confirm the absence of voltage after the absence of voltage test has been performed by illuminating the first green lighting element (Fig. 2b, after testing for absent voltage, green LED is on).
Claim(s) 7-12, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balid et al., US 2022/0120790 in view of Agarwal et al., US 20220037877 in view of Bugaris et al., US 20160313386
Regarding claim 7, Balid teaches wherein the analog circuitry configured to illuminate a first lighting element when a voltage of a phase is greater than a second threshold voltage (¶[0026]; one or more red LEDs illuminated when voltage is about 40V). Balid does not explicitly disclose at least two lighting elements per phase of the power source and wherein the analog circuitry is configured to illuminate a second of the at least two lighting elements when a magnitude of the voltage is less than a magnitude of the second threshold voltage, the magnitude of the second threshold voltage greater than a magnitude of the first threshold voltage. Bugaris teaches at least two lighting elements per phase of the power source (Fig. 5-6; LEDs 508) and wherein the analog circuitry is configured to illuminate a second of the at least two lighting elements when a magnitude of the voltage is less than a magnitude of the second threshold voltage ( ¶[0028]; red and green LEDs lights to indicate absence and presence of voltage), the magnitude of the second threshold voltage greater than a magnitude of the first threshold voltage (¶[0028]; voltage being present would indicate a first voltage which is the voltage of the power line, if no voltage is present, then the voltage is less than the power line voltage). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Bugaris into Balid for the benefit of verifying that the power line is not energized.
Regarding claim 8, Bugaris teaches wherein each of the at least two lighting elements per phase of the power sources is a red lighting element (¶[0028]; red LEDs lights to indicate presence of voltage). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Bugaris into Balid for the benefit of verifying that the power line is not energized.
Regarding claim 9, Balid teaches a third visual indicator and wherein the analog circuitry is configured to illuminate the third visual indicator when the voltage present on any single phase or GRD is above the first threshold voltage and below a third voltage threshold (¶[0052]; illumination of indicators between 30-50V).
Regarding claim 10, Balid teaches wherein the first voltage threshold is 3 volts (¶[0059]; boundary outside 2.95 V).
Regarding claim 11, Balid teaches wherein the third voltage threshold is greater than a magnitude of the second threshold voltage (¶[0044], [0052]; voltage greater than 30V).
Regarding claim 12, Balid teaches wherein the third voltage threshold is less than 50 volts (¶[0044], [0052]; voltage between 30-50V).
Regarding claim 17, Balid is silent in wherein the means for a user to initiate a test for the absence of voltage comprises a push button. Bugaris teaches wherein the means for a user to initiate a test for voltage comprises a push button (¶[0035]; user activates push button). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Bugaris into Balid since the substitution of the push button would produce predictable result of activating the device for a test.
Claim(s) 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balid et al., US 2022/0120790 in view of Agarwal et al., US 20220037877 in view of Gribbin, AU 2019264668
Regarding claim 13-15, Balid is silent in further comprising a charging visual indicator within the analog circuitry and wherein the charging visual indicator is illuminated while the AVT is charging and further comprising a charge low visual indicator within the analog circuitry. Gribbin teaches a charging visual indicator within a voltage detection circuitry and wherein the charging visual indicator is illuminated while the voltage detector is charging and further comprising a charge low visual indicator within the circuitry (¶[0037], [0080]; battery level indication, low battery state indicator to indicate that charging is needed). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Gribbin into Balid for the benefit of alerting a user to charge the device.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balid et al., US 2022/0120790 in view of Agarwal et al., US 20220037877 in view of Gribbin, AU 2019264668 in view of Bugaris et al., US 20160313386
Regarding claim 16, Balid is silent in a super capacitor and wherein the analog circuitry is configured such that the charge low visual indicator indicates state of the super capacitor. Gribbin teaches the circuitry is configured to indicate a charge low level (¶[0080]; low battery state indicator to indicate that charging is needed). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Gribbin into Balid for the benefit of alerting a user to charge the device. Bugaris teaches a super capacitor (¶[0063]; “ultracap”). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Bugaris into Balid since the substitution of the super capacitor would produce predictable result of providing a non-hazardous power source.
Claim(s) 18, 46,48 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balid et al., US 2022/0120790 in view of Agarwal et al., US 20220037877 in view of Clarke, US 20130214922
Regarding claim 18, Balid is silent in wherein the supervisory circuit is configured to flash one or more visual indicators to indicate presence of stored energy if voltage present is over a stored energy threshold. Clarke teaches wherein a circuit is configured to flash one or more visual indicators to indicate presence of stored energy if voltage present is over a stored energy threshold (¶[0029]; C10, F2). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Clarke into Balid for the benefit of indicating that a capacitor or storage unit has reached its charge potential.
Regarding claim 46 and 48, Balid is silent in wherein the AVT is configured to reduce or eliminate leakage of current to ground by the analog circuitry. Clarke taches a voltage tester configured to reduce or eliminate leakage of current to ground ([0020]). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Clarke into Balid for the benefit of reducing damage from leakage current.
Claim(s) 19, 20, 21, 23, 24, 34 and 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balid et al., US 2022/0120790 in view of Agarwal et al., US 20220037877 in view of Bugaris et al., US 20170269128
Regarding claim 19, Balid is silent wherein the secondary power source is a super capacitor. Bugaris teaches wherein the secondary power source is a super capacitor (¶[0063]; “ultracap”). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Bugaris into Balid since the substitution of the super capacitor would produce predictable result of providing a non-hazardous power source.
Regarding claim 20, 21, 23, and 24, Balid is silent in wherein the analog circuitry is configured to charge the secondary power source, wherein the analog circuitry is configured to charge the secondary power source using line voltage from the power source and wherein the analog circuitry is configured to charge the secondary power source using RF power and wherein the analog circuitry is configured to charge the secondary power source using a solar interface (¶[0046]-[0047]; rechargeable secondary power source, using RF, solar as well as recharging when power is returned, i.e. power line). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Bugaris into Balid since the substitution of the temporary power source would provide a non hazardous power source.
Regarding claim 34 and 35, Balid is silent in wherein the housing assembly comprises a door mount assembly, and wherein the AVT is connector less other than source connections. Bugaris teaches housing assembly comprises a door mount assembly, and wherein the AVT is connector less other than source connections (Fig. 5; system 10 with door mount assembly 12 and connection to power source. claim also does not define what is considered source connections and therefore can be any desired connection). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Bugaris into Balid for the benefit of quickly assessing the state of the power system.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balid et al., US 2022/0120790 in view of Agarwal et al., US 20220037877 in view of Bugaris
et al., US 20170269128 in view of Urden, US 4475209
Regarding claim 22, Balid is silent in wherein the analog circuitry is configured to charge the secondary power source using inductive charging coils. Urden teaches charging a power source using inductive charging coils (Fig. 1; coil 66 to power supply 68). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Urden into Balid for the benefit of operating the second power supply.
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balid et al., US 2022/0120790 in view of Agarwal et al., US 20220037877 in view of Malakhovskiy et al., US 20240019466
Regarding claim 25, Balid is silent in wherein the analog circuitry provides for temperature compensation. Malakhovskiy teaches a circuitry of a voltage sensor providing temperature compensation (¶[0034]). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Malakhovskiy into Balid for the benefit of improving accuracy of the measurement by the voltage sensor.
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balid et al., US 2022/0120790 in view of Agarwal et al., US 20220037877 in view of Cuny et al., US 20040257741
Regarding claim 26, Balid is silent in wherein the analog circuitry comprises an application specific integrated circuitry (ASIC). Cuny teaches wherein a voltage sensing circuitry comprises an ASIC (¶0025], [0028]). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Cuny into Balid for the benefit of providing a circuitry which is designed for the application of processing continuous signals of the power line.
Claim(s) 31, 32, 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balid et al., US 2022/0120790 in view of Agarwal et al., US 20220037877 in view of Belady et al., JP 2004004039
Regarding claim 31, 32, and 33, Balid is silent in wherein each pair of voltage lead terminations is coupled to a VSLT printed circuit board (PCB), wherein the VSLT PCB is mounted directly on conductors of the power source and further comprising a heat sink mounted directly on the conductors of the power source. Belady teaches voltage lead terminations coupled to a printed circuit board (PCB), wherein the PCB is mounted directly on conductors of a power source and further comprising a heat sink mounted on the conductors of the power source (Fig. 1-2; PCB 14, vias 16, power supply 18 with conductors connected to PCB and heat sink 32). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Belady into Balid for the benefit of ensuring heat dissipation.
Claim(s) 36, 40, 41, 42, 45 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balid et al., US 2022/0120790 in view of Agarwal et al., US 20220037877 in view of Eriksen et al., CA 3172287
Regarding claim 36, Balid teaches a method of operating an absence of voltage tester (AVT) for detecting the absence of voltage associated with a power source having at least one phase, the AVT having leads for ground and each of the at least one phase (Fig. 1; phase and ground of power line), the AVT comprising analog circuitry electrically connected to a power source (Fig. 3, 9 -10; ¶[0028]; absence of voltage connected to power line); the analog circuitry configured to detect the absence of voltage (Figs. 9-11; absence of voltage detector function ); and detect connections to the power source (Fig. 15; “connectivity detection”); a means for a user to initiate a test for the absence of voltage (¶[0025]; absence of voltage initiated by button); a supervisory test circuit within the analog circuitry (Fig. 3; test circuit and controller); a visual indicator within the analog circuitry to confirm the absence of voltage (Fig. 2b; Yellow, green LEDs indicating voltage levels); a secondary power source operatively connected to the supervisory test circuit for powering the supervisory test circuit (¶[0026], “ a secondary power source (battery)”; claim 1; battery of absence of voltage detection device is checked and connected to the test circuit); and a circuit assembly for each phase connection that enables both a redundant continuity test and provide a reduced voltage power supply front end (¶[0060]; AVD checks voltage on each phase), the method comprising: monitoring of each of the at least one phase of the power source to visually indicate presence or absence of voltage on each of the at least one phase of the power source using analog circuitry (Fig. 1; connection to the power line with the tester is a monitoring of each phase); receiving input from a user to initiate a test (¶[0025]; absence of voltage initiated by button); initiating the test to determine absence of voltage for the power source after receiving input from the user to initiate the test (¶[0025]; test initiated after input); during the test detecting connectivity of the AVT to the power source using an analog supervisory test circuit powered by a secondary power source to confirm the phase and ground leads of the AVT are in direct contact with conductors being tested (¶[0025], [0026]; connectivity of the secondary power source confirmed to detect absence of power which is an indication that no current is flowing in the phase and ground); visually displaying a green indicator to confirm the absence of voltage above a first threshold after the test has been performed and the secondary power source is operative (Fig. 2b; if voltage is absent, green LED is on); and wherein the phase and ground leads are connected to conductors of the power source (Fig. 1; all elements of tester are connected to the phase and ground).
Balid is silent in a current limited power supply front end and using voltage sense lead and continuity termination (VSLT) printed circuit boards. Balid is silent in a current limited power supply front end.
Agarwal teaches a current limited power supply front end (Fig. 1; current limiter 10). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Agarwal into Balid for the benefit of reducing in-rush current to the components.
Eriksen teaches a monitoring sensor using voltage sense lead and continuity termination (VSLT) printed circuit boards (Fig. 65a-b; ground wire monitoring; ground wire 6530, PCB 6520). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Eriksen into Balid for the benefit of monitoring electrical characteristics while reducing the space needed for additional circuitry.
Regarding claim 40, Balid teaches wherein the analog circuitry comprises power conversion circuitry but is silent in the conversion is at the voltage sense lead and continuity termination printed circuit boards. Eriksen teaches a monitoring sensor using voltage sense lead and continuity termination (VSLT) printed circuit boards (Fig. 65a-b; ground wire monitoring; ground wire 6530, PCB 6520). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Eriksen into Balid for the benefit of monitoring electrical characteristics while reducing the space needed for additional circuitry.
Regarding claim 41, Balid teaches visually displaying at least one indicator for each of the at least one phase to indicate voltage is above a second threshold, the at least one indicator not being green in color (Fig. 2b, yellow led when voltage detected by threshold circuits).
Regarding claim 42, Balid teaches further comprising visually displaying at least one indicator indicative that voltage is below a third threshold, the third threshold greater than the second threshold, and the at least one indicator indicative that the voltage is below a third threshold not being green in color (¶[0025], [0026]; yellow flashing led is on after detecting no hazardous voltage).
Regarding claim 45, Balid teaches conducting heat from the circuitry to the conductors (electrical components inherently generate heat). Balid is silent in voltage sense lead and continuity termination printed circuit boards. Eriksen teaches a monitoring sensor using voltage sense lead and continuity termination (VSLT) printed circuit boards (Fig. 65a-b; ground wire monitoring; ground wire 6530, PCB 6520). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Eriksen into Balid for the benefit of monitoring electrical characteristics while reducing the space needed for additional circuitry.
Claim(s) 37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balid et al., US 2022/0120790 in view of Agarwal et al., US 20220037877 in view of Eriksen et al., CA 3172287 in view of Raatikainen et al., EP 2746784
Regarding claim 37, Balid is silent in wherein the method is performed without software and/or microcontrollers. Raatikainen teaches a voltage detecting method is performed without software and/or microcontrollers (page 11 lines 5-10). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Raatikainen into Balid for the benefit of providing a more reliable system.
Claim(s) 38 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balid et al., US 2022/0120790 in view of Agarwal et al., US 20220037877 in view of Eriksen et al., CA 3172287 in view of Cuny et al., US 20040257741
Regarding claim 38, Balid is silent in wherein the analog supervisory test circuit comprises an application specific integrated circuit (ASIC). Cuny teaches wherein a voltage sensing circuitry comprises an ASIC (¶0025], [0028]). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Cuny into Balid for the benefit of providing a circuitry which is designed for the application of processing continuous signals of the power line.
Claim(s) 39, 43 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balid et al., US 2022/0120790 in view of Agarwal et al., US 20220037877 in view of Eriksen et al., CA 3172287 in view of Bugaris, US 20170269128
Regarding claim 39, Balid is silent in wherein the green indicator is mounted at a door mount assembly. Bugaris teaches wherein an indicator is mounted at a door mount assembly (Fig. 5; system 10 with door mount assembly 12). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Bugaris into Balid for the benefit of quickly assessing the state of the power system.
Regarding claim 43, Balid is silent wherein the secondary power source comprises a super capacitor. Bugaris teaches wherein the secondary power source is a super capacitor (¶[0063]; “ultracap”). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Bugaris into Balid since the substitution of the super capacitor would produce predictable result of providing a non-hazardous power source.
Claim(s) 44 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balid et al., US 2022/0120790 in view of Agarwal et al., US 20220037877 in view of Eriksen et al., CA 3172287 in view of Gribbin, AU 2019264668
Regarding claim 44, Balid is silent in further comprising visually indicating that the secondary power source is charging. Gribbin teaches visually indicating that a power source is charging. (¶[0037], [0080]; battery level indication, low battery state indicator to indicate that charging is needed). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Gribbin into Balid for the benefit of alerting a user to charge the device.
Claim(s) 47 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balid et al., US 2022/0120790 in view of Agarwal et al., US 20220037877 in view of Heo, KR 100775340
Regarding claim 47, Balid is silent in wherein the analog circuitry comprises a sample and hold circuit. Heo teaches wherein an analog circuitry comprises a sample and hold circuit (Fig. 3; sample/hold 131-137). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Heo into Balid for the benefit of sampling and processing the signals from multiple phases of the power system.
Claim(s) 53 is/are rejected under 35 U.S.C. 103 as being unpatentable over Balid et al., US 2022/0120790 in view of Agarwal et al., US 20220037877 in view of Blenman, US 4233560
Regarding claim 53, Balid is silent in wherein the continuity test is a bi-directional continuity test. Blenman teaches wherein the continuity test is a bi-directional continuity test (Col. 5 lines 20-35). It would have been obvious to one of ordinary skill in the art before the filing date of the invention to incorporate the teaching of Blenman into Balid for the benefit of testing faults in the wiring and connection systems.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEBA POTHEN whose telephone number is (571)272-9219. The examiner can normally be reached 8:30-5:00 PM.
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/FEBA POTHEN/Examiner, Art Unit 2858
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