Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
The following are the Applicant’s arguments and Examiner’s response:
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Examiner does not agree with Applicant’s arguments Fleming, JR. et al. discloses performing operations on files stored on a storage device based at least in part on a pre-ordered file name or a key value (i.e., “a configurable spatial accelerator
includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value,”(abstract), “Accelerator tile 100 may include one or more of integer arithmetic PEs, floating point arithmetic PEs, communication circuitry (e.g., network dataflow endpoint circuits), and in-fabric storage, e.g., as part of spatial array of processing elements 101”(0201) and Examiner asserts the register or integer arithmetic Pes, in-fabric storage are storage as claimed invention, configuration value is key value of the file and the file can be data such as input with key value, output queue with confirmation value are file as claimed invention and is stored in fabric storage, register or PE and values is key value is claimed invention). Further, In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies “associated with file name associated with a file system” are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The claims recites files stored on a storage device based at least in part on a pre-ordered file name or a key value. Further, the claims does not define what is the storage device, so FE or in in-fabric storage are storage device as claimed invention. Therefore, the Applicant’s arguments are not persuasive.
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Examiner does not agree with Applicant’s argument since Fleming, JR et al. discloses the in-fabric storage, register, PE are storage device as claimed invention.
(i.e., “Accelerator tile 100 may include one or more of integer arithmetic PEs, floating point arithmetic PEs, communication circuitry (e.g., network dataflow endpoint circuits), and in-fabric storage, e.g., as part of spatial array of processing elements 101”(0201) and Examiner asserts the register or integer arithmetic Pes, in-fabric storage are storage as claimed invention, configuration value is key value of the file and the file can be data such as input with key value, output queue with confirmation value are file claimed invention and is stored in fabric storage, register or PE and values is key value is claimed invention). Therefore, the Applicant’s arguments are not persuasive.
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Examiner does not agree with Applicant’s argument since Fleming teaches storage device (i.e., “Accelerator tile 100 may include one or more of integer arithmetic PEs, floating point arithmetic PEs, communication circuitry (e.g., network dataflow endpoint circuits), and in-fabric storage, e.g., as part of spatial array of processing elements 101”(0201) and Examiner asserts the register or integer arithmetic Pes, in-fabric storage are storage as claimed invention, configuration value is file as claimed invention and is stored in fabric storage, register or PE and values is key value is claimed invention) and further having the controller (“a configurable spatial
Accelerator includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value,”(abstract)(it is inherent one element like processer or PE configures to store configuration value (write function as claimed invention) and store or write are action to control and it is controller as claimed invention and further “causes the processing element to perform an operation according to the configuration value” mean read configuration value in the storge (PE, in fabric storage) to execute the configuration based on the configuration value). Therefore, the Applicant’s arguments are not persuasive.
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Examiner does not agree with Applicant’s argument since Fleming discloses a controller to write the data to the storage and to read the data from the storage based on temporary tables (i.e., “a configurable spatial accelerator includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value, a plurality of input queues, an input controller to control enqueue and dequeue of values into the plurality of input queues according to the configuration value, a plurality of output queues, and an output controller to control enqueue and dequeue of values into the plurality of output queues according to the configuration value”(abstract) and Examiner asserts perform function to store or write configuration value in PE or register or so controller (configuration) to read the value that is stored in in-fabric storage and stored in storage, mean write the data to the storage). Furthermore, Fleming discloses to read the data from the storage based on temporary tables (i.e., “FIG. 108 illustrates a buffer box element 10800 according to embodiments of the disclosure. In one embodiment, operation configuration register 10819 (e.g., having a control state machine for each buffer) is loaded during configuration (e.g., mapping) and specifies the particular mode (or modes) this buffer box (e.g., storage) element is to perform, e.g., any of the storage operations discussed herein”(0992) so after read from storage based on the buffer to configurate the operation ). Therefore, the Applicant’s arguments are not persuasive.
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Examiner does not agree with Applicant’s argument Fleming teaches a file or a file name ((i.e., “a configurable spatial accelerator includes a first processing element that includes
a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value,”(abstract), and Examiner assert “store a configuration value” is file as claimed invention.). Further, google defines file is a collection of data stored in a computer system. Store a configuration value is collection of configuration data stored in the computer system such as PE. Further, the Applicant’s argument about a storage device used in a windows-compatible personal computer might include either the FAT32 or NTFS file system. However, In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies “FAT32 or NTFS file system” are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Therefore, the Applicant’s arguments are not persuasive.
Applicant argues Fleming does not disclose operation is drawn from the set including a merge operation and other operation such slip, or a histogram operation . Examiner does not agree since Fleming disclose operation is executed based on the configuration value (key value of the file ) (i.e., “a configurable spatial accelerator includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value, a plurality of input queues, an input controller to control enqueue and dequeue of values into the plurality of input queues according to the configuration value, a plurality of output queues, and an output controller to control enqueue and dequeue of values into the plurality of output queues according to the configuration value”(abstract) and the file can be stream is stored then perform operation merge (i.e., “FIG. 60 illustrates use of streaming compare operator 6002 in a dataflow graph of a merge sort according to embodiments of the disclosure. In one embodiment, this subgraph is repeated to form a sort tree to implement a merge sort. Because the merged lists may not have uniform size, and because the arrangement of the lists into sorted order may occur in any order, it is useful to have an operator that captures this dynamic control behavior. Thus, including a stream compare operation (e.g., in a CSA operation set) allows since multiple control paths are required.”(0467)). Therefore, the Applicant’s argument is not persuasive.
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Examiner does not agree with Applicant’s argument since Fleming teaches operation on data and file. (), “Accelerator tile 100 may include one or more of integer arithmetic PEs, floating point arithmetic PEs, communication circuitry (e.g., network dataflow endpoint circuits), and in-fabric storage, e.g., as part of spatial array of processing elements 101”(0201) and Examiner asserts the register or integer arithmetic Pes, in-fabric storage are storage as claimed invention, configuration value is key value of the file and the file can be data such as input with key value, output queue with confirmation value are file as claimed invention and is stored in fabric storage, register or PE and values is key value is claimed invention). Therefore, the Applicant’s argument is not persuasive.
In response to Applicant’s argument to claim 6, see response on claim 2 above.
In response the Applicant’s argument to claim 8, Examiner does not agree Applicant’s argument since Fleming discloses wherein the accelerator includes at least one of a FPGA (i.e., “embodiments herein may include a FPGA in addition to a CSA according to this disclosure”(0235)), ASIC, CPU (i.e., “Relative to a processor core, CSA embodiments herein may provide for more computational density and energy efficiency. For example, when PEs are very small (e.g., compared to a core), the CSA may perform many more operations and have much more computational parallelism than a core, e.g., perhaps as many as 16 times the number of FMAs as a vector processing unit (VPU). To utilize all of these computational elements, the energy per operation is very low in certain embodiments.”(0237)), GPU.
In response to Applicant’s argument to claim 9 and 19. (See Examiner’s response above like claim 1 above).
In response to the Applicant’s argument about 103, Examiner does not agree since Examiner indicate Fleming teaches all features except for database query. Further, Dorre teaches the data query (see rejection below). Further, Applicant’s argument about that Fleming discloses temporary data and not temporary table. Examiner does not agree with Applicant’s argument since Fleming discloses temporary table (i.e., “FIG. 108 illustrates a buffer box element 10800 according to embodiments of the disclosure. In one embodiment, operation configuration register 10819 (e.g., having a control state machine for each buffer) is loaded during configuration (e.g., mapping) and specifies the particular mode (or modes) this buffer box (e.g., storage) element is to perform, e.g., any of the storage operations discussed herein”(0992) so after read from storage based on the buffer to configurate the operation and “he following discusses examples of certain CSA operations, including certain streaming operations, Boolean control operations, dataflow operations, storage (buffer) operations, and fountain operations, and then includes a table of other CSA operations.”(0452) ). Furthermore, Applicant argued that combination might be archived without significant experimentation, Examiner does not agree since hardware architecture is easy to modify with software with person of ordinary skill in the art, before the effective filing date of the claimed invention. The “KSR” supreme court ruling emphasizing predictability and common sense to make combination both reference. Furthermore, Applicant argued that deleting rows from a table would not to be the result of a query. Examiner does not agree since Dorre discloses deleting is the result of a query (i.e., “an AOT can be modified by a query's data-manipulation (DML) statements (such as a Structured Query Language (SQL) INSERT, UPDATE, and DELETE statement) executed by the dedicated accelerator component. Accelerators cannot, however, directly perform DML statements on rows of regular accelerated tables because doing so would desynchronize the manipulated rows with analogous rows in the client database.’(0020)). The last argument, the Applicant argued that Dorre does not appear mention a temporary table. However, Examiner does not agree with Applicant’s argument since Dorre discloses the temporary location (i.e., “Deleting all qualifying rows from the target table would necessitate additional steps to store the deleted content in a cache or other temporary location. ”(0144)) and further, Fleming discloses temporary table ((i.e., “FIG. 108 illustrates a buffer box element 10800 according to embodiments of the disclosure. In one embodiment, operation configuration register 10819 (e.g., having a control state machine for each buffer) is loaded during configuration (e.g., mapping) and specifies the particular mode (or modes) this buffer box (e.g., storage) element is to perform, e.g., any of the storage operations discussed herein”(0992) so after read from storage based on the buffer to configurate the operation and “he following discusses examples of certain CSA operations, including certain streaming operations, Boolean control operations, dataflow operations, storage (buffer) operations, and fountain operations, and then includes a table of other CSA operations.”(0452)), Therefore, the applicant’s arguments are not persuasive.
In response to the obvious double patenting, the Applicant filed TD on 11/19/2025, therefore, the previous the obvious double patent are withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-14 and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fleming, JR. et al. (U.S. Pub. 2019/0042513 A1)
With respect to claim 1, Fleming, JR. et al. discloses a system, comprising:
a storage device (i.e., “accelerator tile 100 embodiment of a spatial array of processing elements according to embodiments of the disclosure”(0200) and fig. 1 shows memory interface 102), including:
storage for data (i.e., “Accelerator tile 100 may include one or more of integer arithmetic PEs, floating point arithmetic PEs, communication circuitry (e.g., network dataflow endpoint circuits), and in-fabric storage, e.g., as part of spatial array of processing elements 101. Dataflow graphs (e.g., compiled dataflow graphs) may be overlaid on the accelerator tile 100 for execution. In one embodiment, for a particular dataflow graph, each PE handles only one or two (e.g., dataflow) operations of the graph.”(0201)); and
a controller to write the data to the storage and to read the data from the storage based on temporary tables (i.e., “a configurable spatial accelerator includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value, a plurality of input queues, an input controller to control enqueue and dequeue of values into the plurality of input queues according to the configuration value, a plurality of output queues, and an output controller to control enqueue and dequeue of values into the plurality of output queues according to the configuration value”(abstract), “ The input data that is queued may be sent from another component of a CSA, e.g., from a plurality of other PEs as discussed herein. In certain embodiments, the data is read from the first slot of a queue, and when consumed (e.g., removed), any data from other slots of the queue are advanced such that data from the second slot is moved into the first slot, etc. For all of the embodiments herein, the data value from the output queues may be consumed from the output queues”(0899) (and queue is stored in buffer from memory) or “the RAF circuit may be provisioned with completion buffers, e.g., queue-like structures that re-order memory responses and return them to the fabric in the request order.”(0267) “”(the RAM mode (number 4 above) of a buffer box element uses two wide inputs (addr and data_in) (e.g., two wide input queues) and one wide output (data_out) (e.g., one wide output queue). As one embodiment, the Streaming-unload RAM mode being selected for a buffer box element allows a buffer (e.g., buffers 10840 and 10850 in FIG. 108) to use another wide output (e.g., wide output queue) of the buffer box element as a streaming unload port and operating as follows”(1006) and ”(As one embodiment, the random access memory (RAM) mode being selected for a buffer box element uses a buffer (e.g., buffers 10840 and 10850 in FIG. 108) that is small enough for a separate occupancy bit to exist to for each location implemented to be cleared in an energy and cycle-efficient way, for example, as an array of registers. In this mode: (i) on writes, the bit corresponding to the written memory location of the buffer is set, and (ii) on reads, the bit for the read location of the buffer is returned on the control output (e.g., a narrow output queue) (ctl_out) channel along with the output data”. (1003)); and
an accelerator implementing an operation on a file stored on the storage device based at least in part on a pre-ordered file name or a key value (i.e., “ a configurable spatial accelerator includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value, a plurality of input queues, an input controller to control enqueue and dequeue of values into the plurality of input queues according to the configuration value, a plurality of output queues, and an output controller to control enqueue and dequeue of values into the plurality of output queues according to the configuration value”(abstract) and Examiner assert the key value is value as reference).
With respect to claims 2 and 20, Fleming, JR. et al. discloses wherein the operation is drawn from the set including a merge operation (i.e., “the (e.g., inbound) operation is one of a Pick, PickSingleLeg, PickAny, or Merge dataflow operation, e.g., corresponding to a (e.g., same) dataflow operator of a dataflow graph. In one embodiment, a merge dataflow operation is a pick that requires and dequeues all operands (e.g., with the egress endpoint receiving control).”(0313) or “The section below describes several dataflow operations (e.g., and their dataflow operators in embodiments of a CSA) which facilitate the manipulation of streams. In one embodiment, Stream Compare (“stcmp”) allows the comparison of two streams of values (e.g., data values). This operation permits the merging of partially ordered lists, e.g., in merge sort and also in sparse matrix multiplication (e.g., where it is used to calculate the unions and intersections of sparse matrix rows and columns). Stream Pick (“stpick”) and Stream Switch (“stswitch”) allow for the steering of stream-based data. Is Null (“snull”) assists in controlling stream operations by checking the length of a stream object. In one embodiment, one or more (e.g., all) of these operations are sufficient to implement a large number of streaming algorithms.”(0464)), a split operation (i.e., “a CSA architecture includes a configuration value that, when stored into the configuration storage (e.g., register), causes the CSA (e.g., a PE thereof) to perform a Stream Split operation according to the following (e.g., semantics and/or description).”(0527)) , or a histogram operation (i.e., “Accelerator tile 100 may include one or more of integer arithmetic PEs, floating point arithmetic PEs, communication circuitry (e.g., network dataflow endpoint circuits), and in-fabric storage, e.g., as part of spatial array of processing elements 101. Dataflow graphs (e.g., compiled dataflow graphs) may be overlaid on the accelerator tile 100 for execution. In one embodiment, for a particular dataflow graph, each PE handles only one or two (e.g., dataflow) operations of the graph.”(0201) and “This mode may be useful when the RAM is being used as a scratchpad, e.g., when serving as a bank of accumulators for a histogram. Being able to shift the contents out of the buffer with no other address machinery or connections to the inputs saves the need to instantiate this functionality using other compute boxes in the CSA fabric and reduces simplifies the routing interconnectivity required.”(1006)( a configurable spatial accelerator (CSA)));
With respect to claim 3, Fleming, JR. et al. discloses the system according to claim 2, wherein the accelerator implements at least two of the merge operation (i.e., “the (e.g., inbound) operation is one of a Pick, PickSingleLeg, PickAny, or Merge dataflow operation, e.g., corresponding to a (e.g., same) dataflow operator of a dataflow graph. In one embodiment, a merge dataflow operation is a pick that requires and dequeues all operands (e.g., with the egress endpoint receiving control).”(0313) or “The section below describes several dataflow operations (e.g., and their dataflow operators in embodiments of a CSA) which facilitate the manipulation of streams. In one embodiment, Stream Compare (“stcmp”) allows the comparison of two streams of values (e.g., data values). This operation permits the merging of partially ordered lists, e.g., in merge sort and also in sparse matrix multiplication (e.g., where it is used to calculate the unions and intersections of sparse matrix rows and columns). Stream Pick (“stpick”) and Stream Switch (“stswitch”) allow for the steering of stream-based data. Is Null (“snull”) assists in controlling stream operations by checking the length of a stream object. In one embodiment, one or more (e.g., all) of these operations are sufficient to implement a large number of streaming algorithms.”(0464)), the split operation (i.e., “a CSA architecture includes a configuration value that, when stored into the configuration storage (e.g., register), causes the CSA (e.g., a PE thereof) to perform a Stream Split operation according to the following (e.g., semantics and/or description).”(0527)) , or the histogram operation (i.e., “Accelerator tile 100 may include one or more of integer arithmetic PEs, floating point arithmetic PEs, communication circuitry (e.g., network dataflow endpoint circuits), and in-fabric storage, e.g., as part of spatial array of processing elements 101. Dataflow graphs (e.g., compiled dataflow graphs) may be overlaid on the accelerator tile 100 for execution. In one embodiment, for a particular dataflow graph, each PE handles only one or two (e.g., dataflow) operations of the graph.”(0201) and “This mode may be useful when the RAM is being used as a scratchpad, e.g., when serving as a bank of accumulators for a histogram. Being able to shift the contents out of the buffer with no other address machinery or connections to the inputs saves the need to instantiate this functionality using other compute boxes in the CSA fabric and reduces simplifies the routing interconnectivity required.”(1006)( a configurable spatial accelerator (CSA)));
. With respect to claim 5, Fleming, JR. et al. discloses wherein the operation operates on the input file name (configure a circuit element (0312), fig. 17) and generates an output file (1704C (e.g., indicating which of a plurality of operations are to be performed (0313). For example, merge dataflow operation) associated with file system (high-radix dataflow configuration, fig. 17) )(i.e., “a PE and/or network dataflow endpoint circuit is (e.g., each a single) dataflow operator, for example, a dataflow operator that only operates on input data when both (i) the input data has arrived at the dataflow operator and (ii) there is space available for storing the output data,”(0202) and “Depicted receive operation configuration data format 1704 includes an output field 1704A (e.g., indicating which component(s) in a network the (resultant) data is to be sent to), an input field 1704B (e.g., an identifier of the component(s) that is to send the input data), and an operation field 1704C (e.g., indicating which of a plurality of operations are to be performed). In one embodiment, the (e.g., inbound) operation is one of a Pick, PickSingleLeg, PickAny, or Merge dataflow operation, e.g., corresponding to a (e.g., same) dataflow operator of a dataflow graph. In one embodiment, a merge dataflow operation is a pick that requires and dequeues all operands (e.g., with the egress endpoint receiving control)”(0313) (Examiner asserts the file input is fig. 17 configure a circuit element (e.g., network data flow endpoint circuit) data formats to configure a circuit element for sent operation and a recive (e.g.pick) operation (0024) ) and component is an identifier of an input file associated with a file name such 1702 or 1704 fig. 18 shows input filed 1802c (ie.g. an identifier of the component that is to sent the input data (0315)))
With respect to claim 6, Fleming, JR. et al discloses et al. discloses the system according to claim 5, wherein the operation is based at least in part on the key value and a second key value ((i.e., “ a configurable spatial accelerator includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value, a plurality of input queues, an input controller to control enqueue and dequeue of values into the plurality of input queues according to the configuration value, a plurality of output queues, and an output controller to control enqueue and dequeue of values into the plurality of output queues according to the configuration value”(abstract) and Examiner assert the key value is value as reference).
With respect to claim 7, Fleming, JR. et al discloses the system according to claim 5, wherein the operation further generates a second output file (i.e., “Depicted receive operation configuration data format 1704 includes an output field 1704A (e.g., indicating which component(s) in a network the (resultant) data is to be sent to), an input field 1704B (e.g., an identifier of the component(s) that is to send the input data), and an operation field 1704C (e.g., indicating which of a plurality of operations are to be performed). In one embodiment, the (e.g., inbound) operation is one of a Pick, PickSingleLeg, PickAny, or Merge dataflow operation, e.g., corresponding to a (e.g., same) dataflow operator of a dataflow graph. In one embodiment, a merge dataflow operation is a pick that requires and dequeues all operands (e.g., with the egress endpoint receiving control).”(0313) and second output file is can be pick or picksignleleg etc. and still under high-radix dataflow configuration).
With respect to claim 8, Fleming, JR. et al discloses wherein the accelerator includes at least one of a Field Programmable Gate Array (FPGA), an Application-Specific Integrated Circuit (ASIC), a central processing unit (CPU), a Graphics Processing Unit (GPU), or a General Purpose GPU (GPGPU). i.e., “Certain embodiments herein provide a CSA that allows for easy compilation, e.g., in contrast to an existing FPGA compilers that handle a small subset of a programming language (e.g., C or C++) and require many hours to compile even small programs.”(0229)).
With respect to claims 9 and 19, Fleming, JR. et al discloses a method, comprising:
receiving, at a storage device (i.e., “accelerator tile 100 embodiment of a spatial array of processing elements according to embodiments of the disclosure”(0200) and fig. 1 shows memory interface 102),
an instruction from a host to execute an operation (i.e., “ the CSA configuration protocol is for the PEs and the local, circuit switched network. In certain embodiments, a request for CSA configuration (e.g., the configuration code) arrives from a host (e.g., core of a processor that is coupled to the CSA).”(0428)), on a temporary table stored on the storage device, the operation based at least in part on a pre-ordered file name or a key value (i.e., “the configuration (e.g., configuration values) are sent into the PEs and circuit switched network by configuration controllers, e.g., as discussed below.”(0428) and configuration values is key value of claimed invention and “ The input data that is queued may be sent from another component of a CSA, e.g., from a plurality of other PEs as discussed herein. In certain embodiments, the data is read from the first slot of a queue, and when consumed (e.g., removed), any data from other slots of the queue are advanced such that data from the second slot is moved into the first slot, etc. For all of the embodiments herein, the data value from the output queues may be consumed from the output queues”(0899) and queue is stored in buffer from memory) or “the RAF circuit may be provisioned with completion buffers, e.g., queue-like structures that re-order memory responses and return them to the fabric in the request order.”(0267) “”(the RAM mode (number 4 above) of a buffer box element uses two wide inputs (addr and data_in) (e.g., two wide input queues) and one wide output (data_out) (e.g., one wide output queue). As one embodiment, the Streaming-unload RAM mode being selected for a buffer box element allows a buffer (e.g., buffers 10840 and 10850 in FIG. 108) to use another wide output (e.g., wide output queue) of the buffer box element as a streaming unload port and operating as follows”(1006) and ”(As one embodiment, the random access memory (RAM) mode being selected for a buffer box element uses a buffer (e.g., buffers 10840 and 10850 in FIG. 108) that is small enough for a separate occupancy bit to exist to for each location implemented to be cleared in an energy and cycle-efficient way, for example, as an array of registers. In this mode: (i) on writes, the bit corresponding to the written memory location of the buffer is set, and (ii) on reads, the bit for the read location of the buffer is returned on the control output (e.g., a narrow output queue) (ctl_out) channel along with the output data”. (1003);
accessing the file stored on the storage device for the operation (i.e., “executing the operation on the input file that transmitted on a packed switched communication network, for example, to product output file configuration includes a destination filed 1702A, a channel field 1702 B and input filed 1702c (fig. 17) and an operation filed 1702D indicating which of a plurality of operations are to be performed such Switch (second file name associated with High-Radix system file) (0312) using accelerator (“Certain CSAs include many PEs, each of which holds live program values, giving the aggregate effect of a huge register file in a traditional architecture, which dramatically reduces memory accesses“ (0238) )( a configurable spatial accelerator (CSA) “Certain CSAs include many PEs, each of which holds live program values, giving the aggregate effect of a huge register file in a traditional architecture, which dramatically reduces memory accesses“ (0238) )( a configurable spatial accelerator (CSA)) “”(the RAM mode (number 4 above) of a buffer box element uses two wide inputs (addr and data_in) (e.g., two wide input queues) and one wide output (data_out) (e.g., one wide output queue). As one embodiment, the Streaming-unload RAM mode being selected for a buffer box element allows a buffer (e.g., buffers 10840 and 10850 in FIG. 108) to use another wide output (e.g., wide output queue) of the buffer box element as a streaming unload port and operating as follows”(1006) and ”(As one embodiment, the random access memory (RAM) mode being selected for a buffer box element uses a buffer (e.g., buffers 10840 and 10850 in FIG. 108) that is small enough for a separate occupancy bit to exist to for each location implemented to be cleared in an energy and cycle-efficient way, for example, as an array of registers. In this mode: (i) on writes, the bit corresponding to the written memory location of the buffer is set, and (ii) on reads, the bit for the read location of the buffer is returned on the control output (e.g., a narrow output queue) (ctl_out) channel along with the output data”. (1003));
executing the operation on the temporary table to generate an output file using an accelerator (i.e., “ a configurable spatial accelerator includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value, a plurality of input queues, an input controller to control enqueue and dequeue of values into the plurality of input queues according to the configuration value, a plurality of output queues, and an output controller to control enqueue and dequeue of values into the plurality of output queues according to the configuration value”(abstract) and Examiner assert the key value is value as reference and “ The input data that is queued may be sent from another component of a CSA, e.g., from a plurality of other PEs as discussed herein. In certain embodiments, the data is read from the first slot of a queue, and when consumed (e.g., removed), any data from other slots of the queue are advanced such that data from the second slot is moved into the first slot, etc. For all of the embodiments herein, the data value from the output queues may be consumed from the output queues”(0899) (and queue is stored in buffer from memory) or “the RAF circuit may be provisioned with completion buffers, e.g., queue-like structures that re-order memory responses and return them to the fabric in the request order.”(0267) “”(the RAM mode (number 4 above) of a buffer box element uses two wide inputs (addr and data_in) (e.g., two wide input queues) and one wide output (data_out) (e.g., one wide output queue). As one embodiment, the Streaming-unload RAM mode being selected for a buffer box element allows a buffer (e.g., buffers 10840 and 10850 in FIG. 108) to use another wide output (e.g., wide output queue) of the buffer box element as a streaming unload port and operating as follows”(1006) and ”(As one embodiment, the random access memory (RAM) mode being selected for a buffer box element uses a buffer (e.g., buffers 10840 and 10850 in FIG. 108) that is small enough for a separate occupancy bit to exist to for each location implemented to be cleared in an energy and cycle-efficient way, for example, as an array of registers. In this mode: (i) on writes, the bit corresponding to the written memory location of the buffer is set, and (ii) on reads, the bit for the read location of the buffer is returned on the control output (e.g., a narrow output queue) (ctl_out) channel along with the output data”. (1003), and
writing the output file on the storage device (i.e., output file configuration includes a destination filed 1702A, a channel field 1702 B and input filed 1702c (fig. 17) and an operation filed 1702D indicating which of a plurality of operations are to be performed such Switch (second file name associated with High-Radix system file) (0312) and “there is a control state machine in the scheduler which controls the reading and writing to the buffers based on the mode they are programmed to achieve”(0995)).
With respect to claim 10, Fleming, JR. et al discloses 10. The method according to claim 9, further comprising returning a result from the storage device to the host (i.e., “the CSA configuration protocol is for the PEs and the local, circuit switched network. In certain embodiments, a request for CSA configuration (e.g., the configuration code) arrives from a host “ (0428)).
With respect to claim 11, Fleming, JR. et al discloses the method according to claim 10, wherein the result includes a second pre-ordered file name associated with the output file (i.e., “composite operations are named for the order of processing (e.g. fused multiply add=>fma, sll+add=>sladd). In certain embodiments, conversions (cvt) are named cvt{dsttype}{srctype} (e.g., “convert to xxx from yyy”, and the output size is the first type size)”(0439)).
With respect to claim 12, Fleming, JR. et al discloses wherein: the input file is associated with the pre-ordered file name; and the operation includes a merge operation to combine the input file and a second input file associated with a second pre-ordered file name into the output file. (i.e., “a PE and/or network dataflow endpoint circuit is (e.g., each a single) dataflow operator, for example, a dataflow operator that only operates on input data when both (i) the input data has arrived at the dataflow operator and (ii) there is space available for storing the output data,”(0202) and “Depicted receive operation configuration data format 1704 includes an output field 1704A (e.g., indicating which component(s) in a network the (resultant) data is to be sent to), an input field 1704B (e.g., an identifier of the component(s) that is to send the input data), and an operation field 1704C (e.g., indicating which of a plurality of operations are to be performed). In one embodiment, the (e.g., inbound) operation is one of a Pick, PickSingleLeg, PickAny, or Merge dataflow operation, e.g., corresponding to a (e.g., same) dataflow operator of a dataflow graph. In one embodiment, a merge dataflow operation is a pick that requires and dequeues all operands (e.g., with the egress endpoint receiving control)”(0313) (Examiner asserts the file input is fig. 17 configure a circuit element (e.g., network data flow endpoint circuit) data formats to configure a circuit element for sent operation and a receive (e.g. pick) operation (0024) ) and component is an identifier of an input file associated with a file name such 1702 or 1704 fig. 18 shows input filed 1802c (e.g. an identifier of the component that is to send the input data (0315)))
With respect to claim 13, Fleming, JR. et al discloses wherein the operation includes a split operation to separate the input file into the output file and a second output file based at least in part on the key value (i.e., “a CSA architecture includes a configuration value that, when stored into the configuration storage (e.g., register), causes the CSA (e.g., a PE thereof) to perform a Stream Split operation according to the following (e.g., semantics and/or description).”(0527)).
With respect to claim 18, Fleming, JR. et al discloses wherein the accelerator implements the operation and a second operation, the operation a first of a merge operation, a split operation, or a histogram operation, the second operation a second of the merge operation, the split operation, and the histogram operation, and the operation is different from the second operation (i.e., “ Certain embodiments herein allow a first (e.g., type of) dataflow operation to be performed by one or more processing elements (PEs) of the spatial array and, additionally or alternatively, a second (e.g., different, type of) dataflow operation to be performed by one or more of the network communication circuits (e.g., endpoints) of the spatial array.”(0200)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C 103(a) as being unpatentable over Fleming, JR. et al in view of Dorre et al. (U.S. Pub. 2022/0012217 A1).
With respect to claim 4, Fleming, JR. et al. discloses wherein the temporary table processing is based at least in part on in a database query. (i.e., In certain embodiments of a CSA architecture, local storage mechanisms are used to store temporary data, implement read-only-memory (ROM), and/or add buffering to certain portions (e.g., legs) of a dataflow graph executing on the CSA”(0990) and “Another mode of operation for in-fabric storage (e.g., buffer box element) is as a completion buffer, e.g., where values are inserted in a sliding window, and values can be retrieved in order.”(01118) and “More specifically, the load address queue may buffer an incoming address of the memory 18 from which to retrieve data. ”(1325) and “a configurable spatial accelerator includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value, a plurality of input queues, an input controller to control enqueue and dequeue of values into the plurality of input queues according to the configuration value, a plurality of output queues,”(abstract)) but Flemming, JR et al. does not explicit say database query. However Dorre et al. discloses wherein the temporary table processing is based at least in part on in a database query (i.e., “ Deleting all qualifying rows from the target table would necessitate additional steps to store the deleted content in a cache or other temporary location.”(0104)) or “performing the INSERT before the DELETE would temporarily add duplicate rows to the updated table, potentially violating uniqueness constraints and requiring additional code to select which rows to delete and which to retain during the DELETE operation. These issues become even more complex if the columns to be updated are also used by query predicates to determine whether updating a row changes that row's qualifications for archiving.”(0145)). It would have been obvious for a person of ordinary skill in the art, before the effective filing date of the claimed invention, to include database in order to easy and quicky retrieve the query, further, Flemming, JR et al. discloses retrieve the data but do not say retrieving from database and it is not new for the stated purpose has been well known in the art as evidenced by teaching of Dorre.
Allowable Subject Matter
Claim14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed wherein: a first entry a second temporary table stored in in the output file is no larger than the key value; and a second entry a third temporary table stored in in the second output file is larger than the key value.
Claims 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed wherein the operation includes a histogram operation ; and executing the operation on the temporary table to generate the output file using the accelerator includes executing the operation on the temporary table to generate the output file, a second output file accelerator); and a third output file using the accelerator based at least in part on the key value and a second key value; wherein the histogram operation includes separating the input file into the output file, the second output file, and the third output file based at least in part on the key value and the second key value; further comprising sorting the key value and the second key value.
Citation of Pertinent References
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The patent to Buyuktosunoglu et al. discloses Instruction sequence Merging and splitting for optimized accelerator implementing U.S. Pub. 2021/0303306 A1
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/HUNG T VY/Primary Examiner, Art Unit 2163 January 19, 2026