DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Field et al. (2021/0290169) and further in view of Fujimoto (US 2020/0174427).
Regarding claim 1, Field et al discloses a measurement system architecture in figure 7 that teaches: plurality TDC (704, para. 0070) and VCO (1106, para. 0087). Field fails to further teaches: each TDC comprises a voltage-controlled oscillator configured to generate a multiphase clock, each voltage-controlled oscillator comprises a control transistor which is arranged between a first power supply line and a second power supply line and includes a gate to which a control voltage is input, and each voltage-controlled oscillator further comprises a supply circuit configured to supply a current to the gate.
While, Fujimoto discloses an architecture in figure 5 that teaches a TDC comprising: a voltage-controlled oscillator (21) configured to generate a multiphase clock (PH2(0), PH2(1), PH2(2)), each voltage-controlled oscillator comprises a control transistor (T1, T2, T3, T4) which is arranged between a first power supply line (VCTL) and a second power supply line (Ground) and includes a gate to which a control voltage is input, and each voltage-controlled oscillator further comprises a supply circuit (IN) configured to supply a current to the gate (see figure 5(b) and descriptions).
Therefore, it would be obvious to an ordinary skill in the art at the time of the effective filing of the invention in integrate Fujimoto’s teaching into Field’s disclosure to meet the invention requirements.
Regarding claim 6, Fujimoto also teaches wherein the voltage-controlled oscillator arranged in each of the plurality of time-to-digital converters individually comprises a terminal to which a signal for starting an operation is input (see figure 5 and descriptions).
Regarding claim 15, claim 15 is similar to claim 1 in device format. Therefore, claim 15 is rejected as well as rejected in claim 1 such as: plurality of pixel (702), generation circuit (710) and Field et al discloses a measurement system architecture in figure 7 that teaches: plurality TDC (704, para. 0070) and VCO (1106, para. 0087). Field fails to further teaches: each TDC comprises a voltage-controlled oscillator configured to generate a multiphase clock, each voltage-controlled oscillator comprises a control transistor which is arranged between a first power supply line and a second power supply line and includes a gate to which a control voltage is input, and each voltage-controlled oscillator further comprises a supply circuit configured to supply a current to the gate.
While, Fujimoto discloses an architecture in figure 5 that teaches a TDC comprising: a voltage-controlled oscillator (21) configured to generate a multiphase clock (PH2(0), PH2(1), PH2(2)), each voltage-controlled oscillator comprises a control transistor (T1, T2, T3, T4) which is arranged between a first power supply line (VCTL) and a second power supply line (Ground) and includes a gate to which a control voltage is input, and each voltage-controlled oscillator further comprises a supply circuit (IN) configured to supply a current to the gate (see figure 5(b) and descriptions).
Therefore, it would be obvious to an ordinary skill in the art at the time of the effective filing of the invention in integrate Fujimoto’s teaching into Field’s disclosure to meet the invention requirements.
Regarding claim 16, Field et al, also teaches: each of the plurality of pixels (702) comprise an avalanche photodiode (see figure 7 and descriptions).
Regarding claim 17, claim 17 is similar to claim 15 in equipment format. Therefore claim 17 is rejected as well as claim 15, such as: plurality of pixel (702), generation circuit (710) and Field et al discloses a measurement system architecture in figure 7 that teaches: plurality TDC (704, para. 0070) and VCO (1106, para. 0087). Field fails to further teaches: each TDC comprises a voltage-controlled oscillator configured to generate a multiphase clock, each voltage-controlled oscillator comprises a control transistor which is arranged between a first power supply line and a second power supply line and includes a gate to which a control voltage is input, and each voltage-controlled oscillator further comprises a supply circuit configured to supply a current to the gate.
While, Fujimoto discloses an architecture in figure 5 that teaches a TDC comprising: a voltage-controlled oscillator (21) configured to generate a multiphase clock (PH2(0), PH2(1), PH2(2)), each voltage-controlled oscillator comprises a control transistor (T1, T2, T3, T4) which is arranged between a first power supply line (VCTL) and a second power supply line (Ground) and includes a gate to which a control voltage is input, and each voltage-controlled oscillator further comprises a supply circuit (IN) configured to supply a current to the gate (see figure 5(b) and descriptions).
Therefore, it would be obvious to an ordinary skill in the art at the time of the effective filing of the invention in integrate Fujimoto’s teaching into Field’s disclosure to meet the invention requirements.
Allowable Subject Matter
Claims 2-3 are objected to as being dependent upon a rejected base claim, but it would be considered for allowable if they are rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the supply circuit comprises a capacitive element arranged between the first power supply line and the gate, a first switch element configured to charge the capacitive element, and a second switch element configured to supply a current to the gate.
Claims 4-5 objected to as being dependent upon a rejected base claim, but it would be considered for allowable if they are rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the supply circuit reduces variation in potential of the gate by charge injection via a capacitance of the gate at a startup time of the voltage-controlled oscillator.
Claims 7-14 are objected to as being dependent upon a rejected base claim, but it would be considered for allowable if they are rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior art of record, considered individually or in combination, fails to fairly teach or suggest objected features, which is: wherein the voltage-controlled oscillator further includes a ring oscillator arranged between the control transistor and the second power supply line.
Cited References
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cited references are related to instant application subject matters.
Conclusion
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/LAM T MAI/Primary Examiner, Art Unit 2845
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