DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for the examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 6, 7, 18, 19 are rejected under 35 U.S.C. 103 as being unpatentable over DITTY( US 20190258251 A1) in view of Chen( US 20220114014 A1)
As to claim 1, DITTY teaches A system-on-chip (SoC), comprising: a processor; an artificial intelligence (AI) accelerator coupled to the processor to and comprising N acceleration units, wherein N is a positive integer greater than or equal to 2 ( Preferably, platform (100) is implemented with the components (200-500) being implemented on a single die, in a small, powerful, efficient SoC…..At a high-level, CPU (200) can be one or more general purpose central processing units (CPUs), each comprising one or more CPU cores. GPU (300) can be one or more graphics processing units (GPUs), each comprising thousands of GPU cores. Each GPU can be used for any advanced processing task, especially complex tasks that benefit from massively parallel processing. Each GPU typically exhibits better performance per watt for such computer graphics and parallel processing than each CPU, Platform (100) includes an Acceleration Cluster (400) that can consist of a variety of different hardware accelerators, each optimized for a different function or category of functions, para[0183] to para[0185]/Fig. 7)
wherein a security level of the first-type task is higher than a security level of the second-type task ( ISO 26262 addresses possible hazards caused by the malfunctioning of electronic and electrical systems in passenger vehicles, determined by the Automotive Safety Integrity Level (“ASIL”). ASIL addresses four different risk levels, “A”, “B”, “C” and “D”, determined by three factors: (1) Exposure (hazard probability), (2) Controllability (by the driver), and (3) Severity (in terms of injuries). The ASIL risk level is roughly defined as the combination of Severity, Exposure, and Controllability. As FIG. 2 illustrates, ISO 26262 “Road vehicles—Functional safety—Part 9: Automotive Safety Integrity Level (ASIL)-oriented and safety-oriented analyses” (ISO 26262-9:2011(en)) defines the ASIL “D” risk as a combination of the highest probability of exposure (E4), the highest possible controllability (C3), and the highest severity (S3). An automotive equipment rated as ASIL “D” means that the equipment can safely address hazards that pose the most severe risks. A reduction in any one of the Severity, Exposure, and Controllability classifications from its maximum corresponds to a single level reduction in ASIL “A”, “B”, “C” and “D” ratings, para[0013], ln 8-31/The tasks/functions performed by accelerators (401) and (402) may, standing alone, be rated at a lower safety standard (ASIL B) whereas the processes performed by the GPU complex (300) would meet with a higher level of functional safety (e.g., ASIL C), para[0166], ln 4-9).
Chen teaches AI controller coupled to the processor and the AI accelerator and configured to: configure the N acceleration units as a first-type acceleration unit and a second-type acceleration unit, wherein a security level of the first-type acceleration unit is higher than a security level of the second-type acceleration unit( The TEE 202 could also include other components, such as an attestation processor for performing TEE attestation, a configuration manager for managing AI model configurations, a model manager for managing different stored AI models, or a model processor for facilitating execution of a model in conjunction with the computation processor 212, para[0055], ln 6-20/ After performing attestation, retrieving the AI model 414 and any precomputed obfuscated model parameters, and configuring how the AI model 414 is to be executed using the configuration manager 420, the model manager 416 provides the AI model data to the model processor 411. The model processor 411 facilitates the execution of the AI model 414 using the input data 417, The model processor 411 can also partition the computation workload 432 of the inference result between TEE 402 and the non-TEE 404, such as between the computation processor 412 and the accelerator 410. For example, the model processor 411 can partition a calculation of an inference result 434 between an internal calculation 436 performed by processor resources within the TEE 402, such as the computation processor 412, and an external calculation 438 performed by processor resources outside the TEE 402, such as the accelerator 410, In some embodiments, when the model processor 411 partitions the computation workload 432 for the calculation of the inference result 434, the model processor 411 assigns a computation-heavy portion 440 of the computation workload 432, such as a matrix multiplication or convolution portion of the calculation, as at least a portion of the external calculation 438 performed by the processor resources, such as the accelerator 410, in the non-TEE 404, para[0069], ln 1-30/ The model processor 411 allocates computations between the accelerator 410 in the non-TEE 404 and a computation processor 412, such as an application processor[Accelerator], operating within the TEE 402, which can be the processor 120 in some embodiments, para[0064], ln 12-17/ The processor 120[Accelerator] includes one or more of a central processing unit (CPU), a graphics processor unit (GPU)[ Accelerator], an application processor (AP), or a communication processor (CP). , para[0038]/ A TEE is an environment in a secure area of a processor that protects code and data loaded inside the TEE with respect to confidentiality and integrity. The TEE is isolated and runs in parallel with the operating system in a non-TEE and is more secure than a user-facing operating system, para[0034], ln 8-15)
receive a first-type task from the processor in a first execution environment; distribute the first-type task to the first-type acceleration unit; receive a second-type task from the processor in a second execution environment; and distribute the second-type task to the second-type acceleration unit( the model manager 416 provides the AI model data to the model processor 411. The model processor 411 facilitates the execution of the AI model 414 using the input data 417. The model processor 411 can also partition the computation workload 432 of the inference result between TEE 402 and the non-TEE 404, such as between the computation processor 412 and the accelerator 410. For example, the model processor 411 can partition a calculation of an inference result 434 between an internal calculation 436 performed by processor resources within the TEE 402, such as the computation processor 412, and an external calculation 438 performed by processor resources outside the TEE 402, such as the accelerator 410. In some embodiments, when the model processor 411 partitions the computation workload 432 for the calculation of the inference result 434, the model processor 411 assigns a computation-heavy portion 440 of the computation workload 432, such as a matrix multiplication or convolution portion of the calculation, as at least a portion of the external calculation 438 performed by the processor resources, such as the accelerator 410, in the non-TEE 404. The model processor 411 can also assign a computationally-lighter portion 442 of the computation workload 432, such as data obfuscation and obfuscated parameter recovery, activation, and/or pooling, as at least a portion of the internal calculation 436 performed by the processor resources, such as the computation processor 412, in the non-TEE 404. In some embodiments, the assigning of which portions of the computations to partition between the computation processor 412 and the accelerator 410 can be provided to the model processor 411, such as in part of the configuration data provided by the configuration manager 420, para[0069]/ The model processor 411 allocates computations between the accelerator 410 in the non-TEE 404 and a computation processor 412, such as an application processor[Accelerator], operating within the TEE 402, which can be the processor 120 in some embodiments, para[0064], ln 12-17/ The processor 120[Accelerator] includes one or more of a central processing unit (CPU), a graphics processor unit (GPU)[ Accelerator], an application processor (AP), or a communication processor (CP). , para[0038]/ A TEE is an environment in a secure area of a processor that protects code and data loaded inside the TEE with respect to confidentiality and integrity. The TEE is isolated and runs in parallel with the operating system in a non-TEE and is more secure than a user-facing operating system, para[0034], ln 8-15/ processor can assign internal calculation tasks such as data obfuscation, like splitting or perturbing weights of the AI model or layer outputs to be provided to a next layer. The processor can also assign tasks such as performing activation functions or pooling to the computation processor in the TEE. The processor can assign heavier workload tasks, such as matrix multiplications or convolutions, as external calculations performed by the non-TEE accelerator., para[0075], ln 20-32/ the two matrices are provided to the accelerator 410 in the non-TEE 404, and the accelerator 410 returns external results 446 to the model processor 411 in the TEE 402. The computation processor 412 can use the external results 446 to transform or recover the external results 446 into a non-obfuscated result and produce internal results 448. The non-TEE 404 is thus not provided the original weight matrix of the AI model 414. In some embodiments, the computation processor 412 can perturb one or more parameters, such as a weight matrix or intermediary layer inputs, and pass the perturbed parameters to the accelerator 410. Upon receiving external results 446 from the accelerator 410 using the perturbed parameters, the computation processor 412 transforms or recovers the external results 446 into unperturbed results, para[0070, ln 12-27).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this is increasingly common for service providers to run artificial intelligence (AI) models locally on user devices to avoid user data collection and communication costs.
As to claim 2, Chen teaches the AI controller is further configured to: receive a configuration instruction from the processor, wherein the configuration instruction comprises a security identifier and configuration information; and configure the N acceleration units as the first-type acceleration unit and the second-type acceleration unit based on the configuration information when the security identifier indicates that the configuration instruction is from the processor in the first execution environment( para[0067] to para[0068]) for the same reason as to claim 1 above.
As to claims 6, 7, 18, 19, they are rejected for the same reasons as to claims 1, 2 above.
Claim(s) 3, 20 are rejected under 35 U.S.C. 103 as being unpatentable over DITTY( US 20190258251 A1) in view of Chen( US 20220114014 A1) and further in view of Bequet( US 20190370288 A1).
As to claim 3, Bequet teaches a first storage area configured to store computing data corresponding to the first-type task; and a second storage area configured to store computing data corresponding to the second-type task, wherein the AI controller is further configured to configure the first storage area and the second storage area( For example, some of these processors can include a graphical processing unit (GPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), an artificial intelligence (AI) accelerator, para[0278], ln 6-15/ the processor is also caused to, in response to having identified at least one dependency in which the first task routine outputs a mid-flow data set that the second task routine accepts as an input, and in which the first task routine and the second task routine include executable instructions written in different programming languages, perform operations including, for each identified dependency of the at least one identified dependency, para[0010], ln 37-42/ In response to having identified at least one dependency in which the first task routine outputs a mid-flow data set that the second task routine accepts as an input, and in which the first task routine and the second task routine include executable instructions written in different programming languages, the processor may be caused to perform operations including: instantiate a shared memory space to store at least one mid-flow data set during the job flow performance; and for each identified dependency of the at least one identified dependency: store the one of the first form and the second form of the mid-flow data set within the at least one federated area as one of the multiple data sets based on which of the first form and the second form is supported by the primary programming language; and store another of the first form and the second form of the mid-flow data set that is supported by the secondary programming language within the shared memory space as the mid-flow data set is converted., para[0014]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this enables oversight and error checking has also become desirable.
As to claim 20, it is rejected for the same reason as to claim 3 above.
Claim(s) 4, 5 are rejected under 35 U.S.C. 103 as being unpatentable over DITTY( US 20190258251 A1) in view of Chen( US 20220114014 A1) and further in view of Rogers( US 20060267990 A1).
As to claim 4, Rogers teaches the first-type task comprises a first task corresponding to a first virtual address, wherein the second-type task comprises a second task corresponding to a second virtual address, wherein the first-type acceleration unit is configured to perform data access to the first storage area based on the first virtual address and a first page table, and wherein the second-type acceleration unit is configured to perform data access to the second storage area based on the second virtual address and a second page table( Embodiments include a video processing system with at least one graphics processing unit (GPU) or video processing unit (VPU). As used herein, GPU and VPU are interchangeable terms. In various embodiments, rendering tasks are shared among multiple VPUs in parallel to provide improved performance and capability with minimal increased cost. In various embodiments, multiple VPUs in a system access each other's local memories to facilitate cooperative video processing. In one embodiment, each VPU in the system has the local memories of each other VPU mapped to its own graphics address remapping table (GART) table to facilitate access via a virtual addressing scheme. Each VPU uses the same virtual addresses for this mapping to other VPU local memories. This allows the driver to send exactly the same write commands to each VPU, including the numeric value of the destination address for operations such as writing rendered data. This obviates the necessity of generating unique addressing for each VPU according to known virtual addressing schemes. Respective VPUs in the system cooperate to produce a frame to be displayed. In various embodiments, data output by different VPUs in the system is combined, or merged, or composited to produce image data displayed. In one embodiment, the system is programmable such that various modes of operation are selectable, including various compositing modes, and various modes of task sharing or load balancing between multiple VPUs, para[0034]/ In various other embodiments, VPU A 108 and VPU B 110 are not identical. The various embodiments, which include different configurations of a video processing system, will be described in greater detail below, para[0037], ln 5-10).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this provides improved performance and capability with minimal increased cost.
As to claim 5, Rogers teaches the first-type task comprises a first task corresponding to a first physical address, wherein the second-type task comprises a second task corresponding to a second physical address, wherein the first-type acceleration unit is permitted access to the first storage area when the first physical address is located in the first storage area, and wherein the second-type acceleration unit is permitted to access the second storage area when the second physical address is located in the second storage area( para[0051]/ para[0065], ln 1-8/ para[0066], ln 1-8) for the same reason as to claim 1 above.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over DITTY( US 20190258251 A1) in view of Chen( US 20220114014 A1) and further in view of Tatarinov(US 20200257811 A1)
As to claim 8, Chen teaches wherein distributing the first-type task to the first-type acceleration unit comprises: reading, by the AI controller, a first identifier carried in the first-type task; and delivering, by the AI controller, the first-type task to the first-type acceleration unit based on the first identifier, wherein distributing the second-type task to the second-type acceleration unit comprises: reading, by the AI controller, a second identifier carried in the second-type task; and delivering, by the AI controller, the second-type task to the second-type acceleration unit based on the second identifier( para[0069], ln 9-36) for the same reason as to claim 1 above.
Tatarinov teaches wherein the first identifier indicates the security level of the first-type task, and wherein the second identifier indicates the security level of the second-type task( performing a task on a computing device based on access rights determined from a danger level of the task is implemented in a computer comprising a hardware processor, the method comprising: gathering data characterizing the task for control of the computing device, determining a task danger level using a model for determining the task danger level based on the gathered data, para[0010], ln 1-8/ In the first instance, the first task, constituting a great security threat to the computing device, will have a higher task danger level (for example, 0.80). In contrast, the second task may constitute a lower security threat and may be assigned a lower task danger level (for example, 0.30), para[0087], ln 14-21/ performing a task on a computing device based on access rights determined from a danger level of the task in accordance with the teachings of the present disclosure includes real-world devices, systems, components, and groups of components realized with the use of hardware such as integrated microcircuits (application-specific integrated circuit, ASIC) or field-programmable gate arrays (FPGA), or, for example, in the form of a combination of software and hardware such as a microprocessor system and set of program instructions, and also on neurosynaptic chips, para[0036], ln 1-11).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this provides authorized access to computer resources and performing critical action for information security on computing devices.
Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over DITTY( US 20190258251 A1) in view of Chen( US 20220114014 A1) and further in view of Parikh( US 20210132769 A1).
As to claim 9, Parikh teaches integrating the AI controller, the processor, and the AI accelerator into a system-on-chip (SoC); connecting the AI controller and the processor through a bus; and connecting the AI controller and the AI accelerator through the bus( FIG. 54. In one example, an SoC can comprise multiple processor cores, cache memory, a display driver, a GPU, multiple I/O controllers, an AI accelerator, an image processing unit driver, I/O controllers, an AI accelerator, an image processor unit. Further, a computing device can connect elements via bus or point-to-point configurations different from that shown in FIG. 54, para[0740], ln 8-15).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this provides Enhanced and improved experiences are enabled by the lid controller hub's computing resources.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over DITTY( US 20190258251 A1) in view of Chen( US 20220114014 A1) and further in view of Chen( US 20210312271 A1).
As to claim 10, Chen teaches receiving, by the AI controller through the bus, the first-type task and the second-type task that are from the processor; distributing, by the AI controller, the first-type task to the first-type acceleration unit through the bus; and distributing, by the AI controller, the second-type task to the second-type acceleration unit through the bus( AI client 139 can provide access to the AI accelerator 131 by enabling a bus redirect from the local device 256 to the networked device 253. The AI client 139 can intercept and redirect bus traffic intended for the AI accelerator 131 across the network 112. The redirected AI accelerator 131 can appear and be accessed as a USB device or PCI-e device of the networked device 253, rather than the local device 256 to which the AI accelerator 131 is actually connected. The bus redirect can cause the AI accelerator 131 to be accessible to the networked device 253 and inaccessible to the local device 256. The AI agent 137 or other instructions executed on the networked device 253 can control the AI workload through the bus redirect of the AI accelerator 131. The AI accelerator 131 connected to the local device 265 can perform the AI workload, para[0052]/
In step 515, the AI agent 137 can access the AI accelerator 131 using the bus redirect. The AI client 139 can enable access to the AI accelerator 131 by enabling the bus redirect from the local device 256 to the networked device 253. The AI agent 137 can redirect instructions and other traffic for the AI accelerator 131 to the AI client 139 or otherwise to the local device 256. The redirected AI accelerator 131 can be accessed as a USB device or PCI-e device of the networked device 253, rather than the local device 256 to which the AI accelerator 131 is actually connected. An AI workload can be performed by the redirected AI accelerator 131, as controlled from the networked device 253, para[0069]/ Fig.1).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this provides utilizes a management service capable of protecting IoT device data, as well as email, corporate documents, and other enterprise data from theft, data loss, and unauthorized access.
Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over DITTY( US 20190258251 A1) in view of Chen( US 20220114014 A1) and further in view of Bequet( US 20190370288 A1).
As to claim 11, Bequet teaches configuring, by the AI controller, a first storage area in a memory, wherein the first storage area is for storing computing data corresponding to the first-type task; and configuring, by the AI controller, a second storage area in the memory, wherein the second storage area is for storing computing data corresponding to the second-type task( For example, some of these processors can include a graphical processing unit (GPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), an artificial intelligence (AI) accelerator, para[0278], ln 6-15/ he processor is also caused to, in response to having identified at least one dependency in which the first task routine outputs a mid-flow data set that the second task routine accepts as an input, and in which the first task routine and the second task routine include executable instructions written in different programming languages, perform operations including, for each identified dependency of the at least one identified dependency, para[0010], ln 37-42/ In response to having identified at least one dependency in which the first task routine outputs a mid-flow data set that the second task routine accepts as an input, and in which the first task routine and the second task routine include executable instructions written in different programming languages, the processor may be caused to perform operations including: instantiate a shared memory space to store at least one mid-flow data set during the job flow performance; and for each identified dependency of the at least one identified dependency: store the one of the first form and the second form of the mid-flow data set within the at least one federated area as one of the multiple data sets based on which of the first form and the second form is supported by the primary programming language; and store another of the first form and the second form of the mid-flow data set that is supported by the secondary programming language within the shared memory space as the mid-flow data set is converted., para[0014]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this enable oversight and error checking has also become desirable.
Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over DITTY( US 20190258251 A1) in view of Chen( US 20220114014 A1) and further in view of Parikh( US 20210132769 A1).
As to claim 12, Parikh teaches integrating the AI controller, the memory, the AI accelerator, and the processor into a system-on-chip (SoC); and either connecting the memory, the AI controller, the processor, and the AI accelerator through a same bus; connecting the memory, the AI controller, and the processor through a first bus; or connecting the memory, the AI controller, and the AI accelerator through a second bus ( FIG. 54. In one example, an SoC can comprise multiple processor cores, cache memory, a display driver, a GPU, multiple I/O controllers, an AI accelerator, an image processing unit driver, I/O controllers, an AI accelerator, an image processor unit. Further, a computing device can connect elements via bus or point-to-point configurations different from that shown in FIG. 54, para[0740], ln 8-15).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this provides Enhanced and improved experiences are enabled by the lid controller hub's computing resources.
Claim(s) 14, 15 are rejected under 35 U.S.C. 103 as being unpatentable over DITTY( US 20190258251 A1) in view of Chen( US 20220114014 A1) and further in view of Rogers( US 20060267990 A1).
As to claim 14, Rogers teaches wherein the first-type task comprises a first task corresponding to a first virtual address, wherein the second-type task comprises a second task corresponding to a second virtual address, and wherein the AI acceleration method further comprises: performing, by the first-type acceleration unit, data access to the first storage area based on the first virtual address and a first page table; and performing, by the second-type acceleration unit, data access to the second storage area based on the second virtual address and a second page table ( Embodiments include a video processing system with at least one graphics processing unit (GPU) or video processing unit (VPU). As used herein, GPU and VPU are interchangeable terms. In various embodiments, rendering tasks are shared among multiple VPUs in parallel to provide improved performance and capability with minimal increased cost. In various embodiments, multiple VPUs in a system access each other's local memories to facilitate cooperative video processing. In one embodiment, each VPU in the system has the local memories of each other VPU mapped to its own graphics address remapping table (GART) table to facilitate access via a virtual addressing scheme. Each VPU uses the same virtual addresses for this mapping to other VPU local memories. This allows the driver to send exactly the same write commands to each VPU, including the numeric value of the destination address for operations such as writing rendered data. This obviates the necessity of generating unique addressing for each VPU according to known virtual addressing schemes. Respective VPUs in the system cooperate to produce a frame to be displayed. In various embodiments, data output by different VPUs in the system is combined, or merged, or composited to produce image data displayed. In one embodiment, the system is programmable such that various modes of operation are selectable, including various compositing modes, and various modes of task sharing or load balancing between multiple VPUs, para[0034]/ In various other embodiments, VPU A 108 and VPU B 110 are not identical. The various embodiments, which include different configurations of a video processing system, will be described in greater detail below, para[0037], ln 5-10).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this provides improved performance and capability with minimal increased cost.
As to claim 15, Rogers teaches the first-type task comprises a first task corresponding to a first physical address, wherein the second-type task comprises a second task corresponding to a second physical address, wherein the first-type acceleration unit is permitted access to the first storage area when the first physical address is located in the first storage area, and wherein the second-type acceleration unit is permitted to access the second storage area when the second physical address is located in the second storage area ( para[0051]/ para[0065], ln 1-8/ para[0066], ln 1-8) for the same reason as to claim 14 above.
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over DITTY( US 20190258251 A1) in view of Chen( US 20220114014 A1) and further in view of Kaxiras( US 20130254488 A1).
As to claim 16, Kaxiras teaches the N acceleration units comprise a third acceleration unit, and wherein the acceleration method further comprises clearing data cached in the third acceleration unit when the third acceleration unit is configured as the second-type acceleration unit from the first-type acceleration unit, or the third acceleration unit is configured as the first-type acceleration unit from the second-type acceleration unit( The methods and systems according to the invention relate to general-purpose multi-cores (few fat cores), many-cores (many thin cores) or GP-GPUs with coherent caches, accelerator multi-cores, and shared-address space heterogeneous architectures with a multi-core coupled to a many-core., para[0030], ln 5-12/ e computer system includes multiple processor cores, a main memory operatively coupled to the multiple processor cores, and at least one local cache memory associated with and operatively coupled to each of the processor cores for storing cache lines accessible only by the associated core. Each of the cache lines being classified as either a shared cache line or a private cache line, para[0013], ln 3-14/ In the dynamic write policies of the present invention, cache lines that change from private to shared in turn change the write policy for the cache line from write-back to write-through. Consequently, those cache lines marked as Dirty in the L1 cache are cleared by means of a write-through (of the modified cache line) or a delayed write-through transaction, para[0068]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this maintains cache coherence which eliminates the need for directories, invalidations, broadcasts and snoops while maintaining or improving performance and the need improvements to fully take advantage of the multi-core architecture and the number of unnecessary operations needs to be significantly reduced.
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over DITTY( US 20190258251 A1) in view of Chen( US 20220114014 A1) and further in view of YI(US 20220245515 A1).
As to claim 17, YI teaches the first execution environment is a trusted execution environment (TEE), and wherein the second execution environment is a rich execution environment (REE)( The computation associated with the artificial intelligence model may include computation (e.g., matrix computation, bias computation, and activation function computation) based on the artificial intelligence models 231 including layers trained in advance. Although described below, each of the plurality of computation devices 220 may be configured to perform computation in a specific execution environment (e.g., a rich execution environment (REE) 310 or a trusted execution environment (TEE) 320) (or an execution mode or a processor 250). For example, the rich execution environment (REE) may refer to a general execution environment having a low security level, and the trusted execution environment (TEE) may refer to a security execution environment having a high security level, para[0071], ln 18-36/ FIGS. 3A and 3B, the electronic device 101 may be implemented to perform an operation (or function) based on a plurality of execution environments that are separate (or independent) from each other in terms of software. The plurality of execution environments may include, but are not limited to, a rich execution environment (REE) 310 and a trusted execution environment (TEE) 320, and may further include various types of execution environments which may be implemented to be separated (or independent) from each other, para[0082], ln 1-12).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the above teaching to incorporate the above feature because this manages artificial intelligence models increases, a demand for technology of optimizing a computation process of artificial intelligence models increases to manage the artificial intelligence models in portable digital communication devices.
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
US 20100058036 A1 teaches scheduler to process a security level red virtual acceleration task then that same acceleration device, when finished, may not be able to be reassigned to process a security level green virtual acceleration task until a suitable scrubbing process is successfully completed.
US 10366378 B1 teaches cached risk data is modified for each request of offline transaction that is handled regardless of whether the risk data was cached for a previous request or not. In an example, the cached risk data for any given request is only stored in cache memory for a defined period of time and deleted at the lapse of the request. In other implementations.
US 20200133805 A1 teaches Each individual FGPA card 220 may be optimized to perform specific processing tasks, such as specific signal processing, security, data mining, and artificial intelligence functions, and/or to support specific hardware coupled to IHS .
US 20190258251 A1 teaches he context of the example discussed above, if the neural network executing on the SoC's GPU is rated ASIL B, and the same function performed on the PVA (402) is also rated ASIL B, the redundancy provides ASIL D safety for that function.
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/LECHI TRUONG/Primary Examiner, Art Unit 2194
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