DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on 01/23/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of Patent No. 12,088,301 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 8, 11, 12 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xin (US Pub. No. 2004/0064770).
a) regarding claim 8:
Xin discloses a method (Figures 6, 7 and 10), comprising:
electrically connecting a plurality of flip-flops (30) in a predefined series by electrically connecting in series each flip-flop of a portion of the plurality of flip-flops to an adjacent flip-flop in the portion of the plurality of flip-flops between a first output (Q) and a scan input (SD and Figure 6), and
feeding a bit string (scan instruction) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops (Figure 10 and paragraph [0044]).
b) regarding claim 11:
Xin discloses an apparatus (Figure 6), comprising:
a plurality of flip-flops (30) electrically connected in a predefined series, wherein a first output (Q) of one flip-flop of a portion of the plurality of flip-flops is electrically connected to a scan input (SD) of an adjacent flip-flop of the portion of the plurality of flip-flops (Figure 6); and
circuitry configured to provide a bit string of identical bits (scan instruction) to a first flip-flop of the plurality of flip-flops for the resetting of the apparatus (Figure 10 and paragraph [0044]).
c) regarding claim 12:
Xin discloses the apparatus of claim 11, wherein the plurality of flip-flops further comprises a first series of flip-flops and the portion of the plurality of flip-flops is a second series of flip- flops (Figure 7 and paragraph [0036]).
d) regarding claim 15:
Xin discloses the apparatus of claim 12, wherein the circuitry is further configured to feed the bit string of identical bits (scan instruction) through the scan input of the first flip-flop of the first series to reset the plurality of flip-flops in the absence of signaling indicative of performance of a reset operation (Figure 10 and paragraph [0044]).
e) regarding claim 16:
Xin discloses the apparatus of claim 12, wherein a quantity of flip-flops of the first series is different than a quantity of flip-flops of the second series (Figure 7 and paragraph [0036]).
f) regarding claim 17:
Xin discloses the apparatus of claim 11, wherein:
the first flip-flop is configured to output a first predefined bit for each of the identical bits in the bit string, wherein the first predefined bit is further input to a second flip-flop in the predefined series of flip-flops to eliminate receipt of signaling indicative of a reset operation to reset inputs in the plurality of flip-flops (Figures 6 and 10 and paragraph [0044]).
g) regarding claim 18:
Xin discloses the apparatus of claim 17, wherein:
the second flip-flop is configured to output a second predefined bit for each of the first predefined bit, wherein the second predefined bit is further input to a third flip-flop in the predefined series of flip-flops (Figures 6 and 10 and paragraph [0044]).
h) regarding claim 19:
Xin discloses the apparatus of claim 18, wherein the first predefined bit is identical to the second predefined bit (Figure 10 and paragraph [0044]).
i) regarding claim 20:
Xin discloses the apparatus of claim 11, wherein a quantity of the identical bits is greater than a quantity of flip-flops of the plurality of flip-flops (paragraphs [0037] and [0040]).
Allowable Subject Matter
Claims 1-7 are allowed.
Claims 9, 10, 13 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to disclose or make obvious an apparatus, comprising: a final flip-flop configured to produce a scan out chain of bits from either a first output or a second output of the final flip-flop, wherein the scan out chain of bits is different than the identical bits of the bit string, along with all the other limitations as required by claim 1.
The prior art of record fails to disclose or make obvious a method, comprising: producing a scan out chain of bits from a final flip-flop of the plurality of flip-flops in the predefined series, wherein the scan out chain of bits is different from the bits of the bit string, along with all the other limitations as required by claim 9.
The prior art of record fails to disclose or make obvious a method, comprising: electrically connecting another portion of the plurality of flip-flops in series each of the another portion of the plurality of flip-flops to an adjacent flip-flop of the another portion of the plurality of flip-flops between a second output and a scan input, along with all the other limitations as required by claim 10.
The prior art of record fails to disclose or make obvious an apparatus, comprising: wherein a second output of each flip-flop of the first series of flip-flops is electrically connected to a scan input of an adjacent flip-flop in the first series, along with all the other limitations as required by claim 13.
The prior art of record fails to disclose or make obvious an apparatus, comprising: wherein a first output of a final flip-flop of the first series is electrically connected to a scan input of a first flip-flop of the second series, along with all the other limitations as required by claim 14.
Conclusion
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/PATRICK O NEILL/ Primary Examiner, Art Unit 2842
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