Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The applicant’s claim of the benefit of and priority to U.S. Provisional Application No. 63/598,136, filed November 12, 2023 is granted.
Information Disclosure Statement
Acknowledgment is made of the information disclosure statement filed on September 6, 2024. The information disclosure statement has been considered and accepted by the examiner.
Drawings
The drawings submitted on September 6, 2024 have been considered and accepted.
Specification
The specification submitted on September 6, 2024 has been considered and accepted.
Claim Objections
Claims 1, 8, 9, and 11 are objected to because of the following informalities:
In claim 1, line 13, “to allow the first register and the second register share” should read “to allow the first register and the second register to share”.
In claim 8, line 18 of the page, “wherein the memory controller comprising:” should read “wherein the memory controller comprises:”
In claim 9, lines 1-2 of the claim, “wherein the memory controller further comprising:” should read “wherein the memory controller further comprises:”
In claim 11, line 16 of the page, “to allow the first register and the second register share” should read “to allow the first register and the second register to share”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 5-6 and 15-16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 5 recites “the memory controller is further configured to execute a second instruction to declare the first register and the second register in the memory storage”, however the specification of the instant application does not provide support for an instruction declaring two registers in the memory storage. Paragraph 24 of the specification recites “The compiler 110 provides an instruction named “Register_rid”, which is used to set required information for a corresponding one of the registers r1 to rn”. As the “Register_rid” instruction is only disclosed to declare a single register, and no other disclosed instructions appear to be able to declare two registers, claim 5 fails to comply with the written description requirement.
Claim 6 depends on claim 5, and therefore would also fail to comply with the written description requirement. In addition, claim 6 also recites a claim limitation that fails to comply with the written description requirement: “wherein the second instruction is a “Register_rid” instruction which sets the base address, the bound address and the delete size of each of the first register and the second register”. As explained in claim 5 above, the “Register_rid” instruction is not described as being able to set two registers.
Claims 15 and 16 are rejected under the same rationale as claims 5 and 6, respectively, above.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 4 and 14 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "wherein the one of the memory spaces between the base address and the bound address of the first register is sharable". There is insufficient antecedent basis for this limitation in the claim. While claim 1 recites “the first register and the second register share one of the memory spaces in the memory storage” and “a plurality of registers to manage a plurality of memory spaces in the memory storage”, there is no prior recitation in the claims of a (one of the) memory space between the base address and the bound address. For the purpose of examination, the claim limitation has been interpreted to read “wherein one of the memory spaces is between the base address and the bound address of the first register and is sharable”.
Claim 14 is rejected under the same rationale as claim 4 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 10-12, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nation et al. (U.S. patent application publication 20100161908 A1), hereinafter referred to as Nation, in view of Shinyama (GitHub repository entitled "Convolutional Neural Network in C" 12 pages, posted April 2, 2020 by Yusuke Shinyama. Retrieved from Internet:<https://github.com/euske/nn1/blob/3937838ad83adf26cdb69395f41790a70fbddea4/cnn.c>.), hereinafter referred to as Shinyama.
Regarding claim 1, Nation teaches A memory device, for cooperating with at least one computing engine, the memory device comprising: (Nation shared memory resource 250; and processing systems 210 (any of which comprise the at least one computing engine), see Nation Fig. 2) a memory storage, configured to store data for the at least one computing engine; and (any of the memory appliances 252-258 of the shared memory resource 250 of Nation. See also “Shared memory resource 250 … is utilized as the system main memory for one or more of processing systems 210.” [Nation par. 47]) a memory controller, configured to utilize a plurality of registers to manage a plurality of memory spaces in the memory storage, (“memory appliance 400 includes a number of memory banks 410 each accessible via a memory controller 420. To manage the mapping of global virtualized addresses to physical addresses in memory banks 410, memory controller 420 includes an MMU or equivalent page table (e.g., configuration registers)” [Nation par. 54]. Wherein memory addresses are memory spaces, and it would have been obvious to a person having ordinary skill in the art that memory appliance 400 is an example implementation of or substitute equivalent implementation for the memory appliances 252-258 cited above).
Although Nation does disclose data de-duplication including copying configuration entries (which are part of the configuration registers) that point to common/shared data (see Nation pars. 57 and 92), Nation does not appear to explicitly disclose to perform a plurality of neural network computations, execute a first instruction to control at least two data paths in the neural network computations, and wherein the first instruction is utilized to duplicate a first register to a second register, to allow the first register and the second register share one of the memory spaces in the memory storage, wherein the first register and the second register are among the plurality of registers.
However, Shinyama teaches to perform a plurality of neural network computations (the for loop depicted in the screen capture of Shinyama’s code below contains instructions for a computing engine to perform a plurality of neural network computations), execute a first instruction to control at least two data paths in the neural network computations (based on paragraph 5 of the specification of the instant application reciting “a first instruction to control at least two data paths in the computations. The first instruction is utilized to duplicate a first register to a second register of the registers”, the broadest reasonable interpretation of this claim limitation is met by duplicating registers involved in neural network computations. Line 210 of Shinyama’s code below duplicates a pointer to a C code data structure representing a neural network layer. The pointer to a data structure is a memory register. Additionally, a person having ordinary skill in the art would recognize that line 210 of Shinyama’s code makes a memory read followed by a memory write, and that those would require execution on the part of a memory controller (such as Nation’s memory controller 420) to perform. Therefore the duplication of neural network layer on line 210 comprises the first instruction, and the claimed limitation would have been obvious.), and wherein the first instruction is utilized to duplicate a first register to a second register, to allow the first register and the second register to share one of the memory spaces in the memory storage, wherein the first register and the second register are among the plurality of registers (copying the pointer to variable lprev (“previous layer”) as depicted on line 210 of Shinyama’s C code below achieves this claimed limitation (see above). A person having ordinary skill in the art would recognize that both variables would share the same memory address (space), and a first and second register (as in Shinyama) are inherently among a plurality of registers as they themselves are a plurality of registers. See also the de-deduplication process of Nation (Nation Fig. 11 and par. 92), which could be applied in combination with Shinyama).
PNG
media_image1.png
455
635
media_image1.png
Greyscale
Nation and Shinyama are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Nation and Shinyama before him or her, to modify the apparatus of Nation to include the attributes of to perform a plurality of neural network computations, execute a first instruction to control at least two data paths in the neural network computations, and wherein the first instruction is utilized to duplicate a first register to a second register, to allow the first register and the second register share one of the memory spaces in the memory storage, wherein the first register and the second register are among the plurality of registers of Shinyama because it will enhance apparatus efficiency.
The motivation for doing so would be that the pointer manipulation of Shinyama enables efficient memory allocation and memory access for neural network computations.
Therefore, it would have been obvious to combine Nation and Shinyama to obtain the invention as specified in the instant claim.
Regarding claim 11, it is rejected under the same rationale as claim 1 above.
Regarding claim 2, the combination of Nation/Shinyama teaches The memory device of claim 1, wherein the first instruction is a “Duplicate” instruction with a first data field identifying the first register as a source and a second data field identifying the second register as a destination (Line 210 of Shinyama duplicates the lprev (the name of the layer pointer functioning as a register) of the function’s input parameter (source) Layer pointer to a newly instantiated Layer pointer (destination), also named lprev).
Regarding claim 12, it is rejected under the same rationale as claim 2 above.
Regarding claim 10, the combination of Nation/Shinyama teaches The memory device of claim 1, wherein the memory storage comprises any type of volatile storage or non-volatile storage (“In some instances of the aforementioned embodiments, the memory appliance includes a network interface and a flash memory. In some such instances, the memory appliance further includes a DRAM. In other instances of the aforementioned embodiments, the memory appliance includes a network interface and a DRAM.” [Nation par. 8]. Wherein flash memory is a type of non-volatile storage and DRAM is a type of volatile storage).
Regarding claim 20, it is rejected under the same rationale as claim 10 above.
Claims 3-7 and 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Nation, in view of Shinyama, further in view of Narad et al (U.S. patent application publication 20060236011 A1), hereinafter referred to as Narad.
Regarding claim 3, the combination of Nation/Shinyama teaches The memory device of claim 1, wherein each of the plurality of registers has a plurality of parameters including a base address, (Nation teaches “Configuration registers 440 include a number of configuration entries 450 that identify individual regions of memory supported by memory appliance 400. Each of configuration entries 450 includes a virtual machine identification (VMID) 451, a virtual machine base address 452, a memory range 453, a set of access attributes 454, and a page size 455” (Nation par. 57; fig. 4)) a bound address, (Nation teaches “Memory range 453 indicates the amount of memory starting at virtual machine base address 452 that is identified by the particular configuration entry 450” (Nation par. 57; fig. 4). Wherein the range represents a bound or last address identified by the configuration entry) a delete size, (Paragraph 35 and table 4-5 of the specification of the instant application provide description that the delete size is the amount of memory within the register that gets deallocated during a delete operation. Nation teaches “Page size 455 identifies a memory page granularity that allows the physical memory in memory banks 410 to be fragmented across the set of virtual machines. By doing this, large contiguous ranges of the physical memory do not have to be available for mapping to the virtual machine memory spaces. Rather, the mapped physical memory may consist of a number of smaller, non-contiguous regions that are combined to provide the range designed by the particular configuration entry 450.” (par. 0057; fig. 4). As the page size is the smallest quanta of data management of the registers in Nation, deallocations would also share the granularity of the page size (i.e. the size of deletions would correspond to the page size) and the base address and the bound address of the first register are the same as the second register (both registers of Shinyama point to the same memory space, so they would share the same base address and bound address).
Nation/Shinyama do not appear to explicitly disclose a head pointer and a tail pointer.
However, Narad teaches a head pointer and a tail pointer (“A particular ring number will thus be used to access a head descriptor 52, a tail descriptor 50, a public descriptor 54 and a credit descriptor 56 one within each of those four arrays and each related to that particular ring. The head descriptor provides a pointer to the next entry or location to be read from the corresponding ring, while the tail descriptor provides a pointer the next entry or location to be written” [Narad par. 34]. Wherein the rings of Narad are a shared memory data structure analogous to a register of the instant claim.
Nation/Shinyama and Narad are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Nation/Shinyama and Narad before him or her, to modify the apparatus of Nation/Shinyama to include the attributes of a head pointer and a tail pointer of Narad because it will enhance apparatus efficiency.
The motivation for doing so would be the pointer system of Narad improves data sharing between computing agents (see Narad par. 67 “agents may share memory without contention”). Reducing contention would improve memory access efficiency.
Therefore, it would have been obvious to combine Nation/Shinyama and Narad to obtain the invention as specified in the instant claim.
Regarding claim 13, it is rejected under the same rationale as claim 3 above.
Regarding claim 4, the combination of Nation/Shinyama/Narad teaches The memory device of claim 3, wherein the one of the memory spaces is between the base address and the bound address of the first register and is sharable by the second register, and (Narad teaches memory portions organized as rings (Narad figs. 1-3) where [Narad par. 0035] “Each ring can be independently configured for size and can be independently located in memory (i.e., the different rings may not reside in a contiguous region of memory). Several techniques are applicable to ring size configuration. For example, a ring or group of rings could be configured by a control register indicating the ring size. Alternately, the ring size may be stored as data in a ring's descriptor. The size and the alignment of each memory array representing a ring may be restricted to a power of 2 to allow the full pointer to be stored in one location in the ring descriptor. By using the ring-size to determine which high-order bits to hold constant and which to include in the incrementing pointer, a ring base and an incrementing index for each ring can be stored efficiently in the ring's descriptor. Alternatively, one could support arbitrary alignment and/or arbitrary size of independently located rings by storing the ring upper_bound address and the ring size (or equivalently the ring_base and the ring size) and when the boundary is reached, the pointer is reset to the bound minus the size (or equivalently is set to the base value).” Wherein the ring comprises a memory space continuing from the base (which would be the base address) to the ring upper_bound address (which would be the bound address)) an available data between the head pointer and the tail pointer of the first register is accessible through the second register (Narad par. 41 teaches “Referring now to FIGS. 4-6, the head descriptor 50 contains data private to the consumer, the tail descriptor 52 contains data private to the producer and the public descriptor 54 contains a public version of the produce pointer communicated to the consumer. The head (consume) pointer stored in the head pointer field 70 provides the address of the next item (entry) to be read from the ring by a consume access operation (e.g., based on a ME generated `get` command). The tail pointer stored in the Tail_Ptr field 80 contains the address of the next item to be written to the ring by a produce access operation (e.g., as generated by a ME `put` command). In a preferred embodiment the head and tail pointers are initialized with the physical address (location in the shared memory) of the base of the ring data storage region 41. The Prev_Tail field 72 stores the most recently cached value of the public tail pointer. The C_Count 74 contains the amount of data (number of entries) on the ring available for a consume access operation.” Where the head and tail are within each memory ring (see figs. 1-3) which includes address bounds (see Narad par. 0035)). As Shinyama teaches accessing the same data through data structures pointing to the same data (as cited above), it would have been obvious to, in combination with Narad and Nation, have the addresses and data sharable/accessible through both the first and second register).
Regarding claim 14, it is rejected under the same rationale as claim 4 above.
Regarding claim 5, the combination of Nation/Shinyama/Narad teaches, as best understood and interpreted by the examiner in light of the 112(a) rejection described above, the memory device of claim 3, wherein the memory controller is further configured to execute a second instruction to declare the first register and the second register in the memory storage before the first instruction is executed (“Before a given ring can be used it must be initialized” [Narad par. 61]. See Narad Fig. 15 for the initialization process, which includes allocating space in memory for the ring. Therefore it would have been obvious to initialize (which is synonymous with declare) a register before using it in further operations, such as the first instruction).
Regarding claim 15, it is rejected under the same rationale as claim 5 above.
Regarding claim 6, the combination of Nation/Shinyama/Narad teaches, as best understood and interpreted by the examiner in light of the 112(a) rejection described above, The memory device of claim 5, wherein the second instruction is a “Register_rid” instruction which sets the base address, the bound address and the delete size of each of the first register and the second register (“Network controller 430 includes a set of configuration registers 440 that are programmable and used to identify memory regions that are supported by memory appliance 400. By programming configuration registers 440, memory appliance 400 can be programmed to operate as the main memory for a number of different virtual machines, with provisioned physical memory spaces assigned to respective virtual machines. Configuration registers 440 include a number of configuration entries 450 that identify individual regions of memory supported by memory appliance 400. Each of configuration entries 450 includes a virtual machine identification (VMID) 451, a virtual machine base address 452, a memory range 453, a set of access attributes 454, and a page size 455” [Nation par. 57 and fig. 4]. As the registers of Nation are programmable, it would have been obvious to a person having ordinary skill in the art that a computer instruction could be used to program (set) the base address, the bound address and the delete size of registers).
Regarding claim 16, it is rejected under the same rationale as claim 6 above.
Regarding claim 7, the combination of Nation/Shinyama/Narad teaches The memory device of claim 3, wherein each of the plurality of registers further includes an identifier (Nation virtual machine identification (VMID) 451 as well as “Configuration registers 440 include a number of configuration entries 450 that identify individual regions of memory” (see Nation par. 57 and fig. 4). Both VMID 451 and configuration entries 450 would be identifiers) and two indicators, (“the different producers and consumers may independently access the ring data structures of a given ring. In such an implementation, mechanisms (e.g., a mutual-exclusion lock ("mutex")) may be used to resolve contention issues between the agents. For example, the head and tail descriptors may be protected by mutual-exclusion (mutex) locks that restrict access to the descriptors to one respective consumer or producer agent at a time. Alternately, mutexes may be used at finer granularity. For instance, one mutex may lock the private consumer pointer while another locks the private consumer credit count. Additionally, the multiple agents may maintain their own credit pools that they contribute to/take from the private producer/consumer credit pools.” [Narad par. 67]. Wherein the plurality of mutexes indicate whether pointers are accessible, making them indicators) and the memory controller utilizes a managing table to record the base address, the bound address, the delete size, the head pointer, the tail pointer, the identifier and the indicators (The examiner notes that the phrasing “table to record” does not require the table perform the listed functionality but merely controllers where the functionality is not expressly precluded See MPEP 2111.04 and MPEP 2114. Additionally, a table recording different types of information may be interpreted as nonfunctional descriptive material since the material is not functionally related to the controller. "Nonfunctional descriptive material" includes but is not limited to music, literary works and a compilation or mere arrangement of data (MPEP section 2106.IV.B.1). Note that "Nonfunctional descriptive material cannot render nonobvious an invention that would have otherwise been obvious." Ex parte Curry, See MPEP 2111.05. Furthermore, it would have been obvious to record the base address, the bound address, the delete size, the head pointer, the tail pointer, the identifier and the indicators in a table utilized by a memory controller. See the tables utilized in Nation to record information descriptive of registers by the network controller 430 and memory controller 420 in Nation fig. 4))
Regarding claim 17, it is rejected under the same rationale as claim 7 above.
Claims 8-9 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Nation/Shinyama/Narad, further in view of Frazier et al. (US 9,547,484 B1), hereinafter referred to as Frazier.
Regarding claim 8, the combination of Nation/Shinyama/Narad teaches the memory device of claim 7, wherein the memory controller comprises: the base address, the bound address and the delete size (see the rejections to claims 3 and 7 above).
Nation/Shinyama/Narad do not appear to explicitly disclose wherein the memory controller comprises: a compiler, configured to maintain the base address, the bound address and the delete size in a software level.
However, Frazier, teaches wherein the memory controller comprises: a compiler, configured to maintain the base address, the bound address and the delete size in a software level (“compiler 120 that compiles software (e.g., application 107, source code 108, hypervisor 106, etc.), and the compiler 120 is configured to execute on the processor 101 of the computer system 100” (col. 10, lines 56-60). It would have been obvious to a person having ordinary skill in the art to have the compiler 120 of Frazier to, in combination with Nation/Shinyama/Narad, execute on the memory controller to perform these memory management functions as doing so would offload work from the main processor, improving the efficiency of the processor. Furthermore, Frazier discloses compiling for a hypervisor, and Nation uses a hypervisor. Therefore in combination it would have been obvious to apply a compiler to the register configurations taught by Nation).
Nation/Shinyama/Narad and Frazier are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Nation/Shinyama/Narad and Frazier before him or her, to modify the apparatus of Nation/Shinyama/Narad to include the attributes of wherein the memory controller comprises: a compiler, configured to maintain the base address, the bound address and the delete size in a software level of Frazier because it will enhance apparatus efficiency.
The motivation for doing so would be that it would have been obvious to a person having ordinary skill in the art that a compiler, such as the one taught by Frazier, enables the optimization of software for a target platform, such as the software taught by Nation/Shinyama/Narad and the hardware platforms they teach (additionally see Frazier col. 10 lines 56-60 for compiler optimization).
Therefore, it would have been obvious to combine Nation/Shinyama/Narad and Frazier to obtain the invention as specified in the instant claim.
Regarding claim 18, it is rejected under the same rationale as claim 8 above.
Regarding claim 9, the combination of Nation/Shinyama/Narad/Frazier teaches The memory device of claim 8, wherein the memory controller further comprises: a memory managing unit, configured to control the head pointer, the tail pointer and the indicators in a hardware level (Nation par. 54 “memory controller 420 includes an MMU” and Narad teaches a memory managing unit configured to control the head pointer and tail pointer in a hardware level (Narad Fig. 1 “ring manager (hardware)” 30 (the word “hardware” in paratheses is present in Narad Fig. 1) and Fig. 2 depicting ring manager 30 which manages a plurality of head and tail descriptors (the descriptors are pointers, see Narad par. 34). Furthermore, “The ring manager sets 210 the cache line lock status bit for the cache line holding the head descriptor” [Narad par. 60] and “The ring manager sets the lock status bit associated with the cache line holding the tail descriptor” [Narad par. 51]. Wherein the lock statuses are indicators.
Regarding claim 19, it is rejected under the same rationale as claim 9 above.
Pertinent Prior art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220237487 A1 – Kim et al.
Relevant excerpt: “If there is a weight sharing group of the first group, the scheduler 411 may cause the two groups (in other words, the first group and the weight sharing group) to be performed in parallel, in operation 630. For example, the scheduler 411 may assign the first group to half of the PE arrays 416 (for example, the PE arrays 1 to 8), and assign the weight sharing group to the other half the PE arrays 416 (for example, the PE arrays 9 to 16). The weight fetcher 415 may fetch the weights of the first group stored in the on-chip memory 413 and transfer the weights of the first group to the PE arrays 1 to 16. The input fetcher 414 may fetch the input data of the first group stored in the on-chip memory 413 and transfer the input data of the first group to the PE arrays 1 to 8. The input fetcher 414 may fetch the input data of the weight sharing group stored in the on-chip memory 413 and transfer the input data of the weight sharing group to the PE arrays 9 to 16.” [Par. 106]
US 20220108209 A1 – PUDIPEDDI et al.
Relevant excerpt: “Techniques for shared memory spaces in data and model parallelism are provided to improve memory efficiency and memory access speed. A shared memory space may be established at a host system or in a hardware memory agent. The shared memory may store training data or model parameters for an artificial intelligence model at a memory address in one or more memory circuits. Data for the artificial intelligence model may be processed across a plurality of artificial intelligence accelerators using the training data or the model parameters of the shared memory space. That is, multiple accelerators access one copy of the data from the shared memory space instead of accessing their own separate memory space.” [abstract]
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTIAN O’CONNELL whose telephone number is (571)270-7784. The examiner can normally be reached on Monday-Friday 9:30 AM - 6:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Vo can be reached on (571)272-3642. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857
To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http:/www.uspto.gov/interviewpractice.
Information regarding the status of published or unpublished applications may be
obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and ttps://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.J.O./
Examiner, Art Unit 2138
/Kaushikkumar M Patel/Primary Examiner, Art Unit 2138