DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-28 are presented for examination.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-28 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of the parent U.S. Patent No. 12,113,360 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because the instant independent claims 1, 9, 19 recite similar steps such as: determining observed additional latencies; determining circuit load; binning the observed additional latencies; determining and observed additional latency average; determining an average of the observed additional latency averages of a subset of the load bins; determining an average of expected additional latencies of the subset of the load bins; and scoring health of the network path. The instant independent claims recites a narrower limitation of circuit load in part on both ingress and egress loads.
Instant Application
Parent 12,113,360 B2
1. A method comprising:
determining observed additional latencies with respect to a base latency of a network path based on time-series latency data of the network path;
determining circuit load of each of a plurality of time intervals of the time-series latency data based, at least in part, on both ingress and egress loads;
binning the observed additional latencies into corresponding ones of a plurality of load bins based, at least in part, on the determined circuit loads;
determining an observed additional latency average for each of the plurality of load bins;
determining an average of the observed additional latency averages of at least a subset of the plurality of load bins;
determining an average of expected additional latencies of the subset of the load bins; and
scoring health of the network path based, at least in part, on the average of the observed additional latency averages and the average of expected additional latencies.
1. A method comprising:
based on time-series latency data of a network path,
determining observed additional latencies with respect to a base latency of the network path;
determining load of each of a plurality of time intervals of the time-series latency data;
binning the observed additional latencies by load;
determining an observed additional latency average for each load bin;
determining an average of the observed additional latency averages of a subset of the load bins;
determining an average of expected additional latencies of the subset of the load bins; and
scoring health of the network path based, at least in part, on the average of the observed additional latency averages and the average of expected additional latencies.
Claim Rejections - 35 USC § 101
Claim 1-28 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to an abstract idea without significantly more. The claim recites determining observed additional latencies of a network path; determining circuit load of latency data based on both ingress and egress loads; binning observed additional latencies on determined circuit loads; determining an observed additional latency average for each of the plurality of load bins; determining an average of the observed additional latency of at least a subset of the plurality of load bins; determining an average of expected additional latencies of the subset of the load bins; and scoring health of the network path based on average of the observed additional latency averages and the average of the expected additional latencies.
The limitations of determining observed additional latencies, determining an observed additional latency average, and scoring health of the network path, as drafted, are processes that, under their broadest reasonable interpretation, cover performance of the limitations in the mind but for the recitation of generic computer components. That is, other than reciting “load bin”, “a processor”, and “machine-readable medium” nothing in the claim elements precludes the steps from practically being performed in the mind. For example, but for the “determining observed additional latencies”, “determining an observed additional latency averages”, and “scoring health of the network path” in the context of this claim encompass a user recording latencies, averaging latency values, and scoring them as health of the network path, and then mentally analyzing the organized data. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular, the claim only recites additional elements of load bins, processor, and machine-readable medium to perform the determining latencies, binning latencies, and scoring health of the network path step. The load bins, processor, and machine-readable medium are recited at a high level of generality (i.e., as generic computer components performing generic computer functions of collecting, organizing, and analyzing information) such that they amount to no more than mere instructions to apply the exception using generic computer components. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of a load bins, processor, and machine-readable medium to determining observed latencies, determining average latencies, and scoring health of the network path steps amount to no more than mere instructions to apply the exception using generic computer components. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The claim is not patent eligible.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gunmaste et al. U.S. Patent Application Publication Number 2019/0319876 A1. Using observed latency value for optimization (see section [0086]).
Joliveau et al. U.S. Patent Number 11,706,146 B1. Monitoring network health and performing path computation to determine latency (see section [0018]).
Peach et al. U.S. Patent Application Publication Number 2016/0277272 A1. System for continuously measurement of transit latency (see Abstract).
Reddy et al. U.S. Patent Application Publication Number 2023/0091734 A1. Network path scoring system (see Abstract).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALAN S CHOU whose telephone number is (571)272-5779. The examiner can normally be reached Monday-Friday 9:00-5:00 EST.
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/ALAN S CHOU/Primary Examiner, Art Unit 2451
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