Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawano (US 20110294444 A1), in view of Kamada (US 20180090476 A1).
Regarding independent claim 1, Kawano teaches a semiconductor device comprising: a substrate (Fig. 1B, 109; [0066], "On the semiconductor substrate 109, the epitaxial layer 116 is formed to achieve good crystallinity. "); a compound semiconductor layer provided on the substrate (Fig. 1B, 113, 114; [0067], "...the channel layer 113 is formed of undoped InGaAs; the Schottky barrier layer 114 is formed of AlGaAs…", (In the present application, the semiconductor layer is made from a barrier layer and a channel layer)); and a plurality of unit FETs arranged in a second direction intersecting a first direction (Fig. 1A, 108; [0073], "As illustrated in FIG. 1B, the FET 100 is formed in the active region 104 in the straight-line portions 108, and one straight-line portion 108 functions as one unit FET."), each of the unit FETs including: a source electrode provided on the compound semiconductor layer and extending in the first direction; a drain electrode provided on the compound semiconductor layer and extending in the first direction (Fig. 1B, 101; [0068], "Usually, the contact layer 115 is a high-concentration n-type semiconductor layer, and two source/drain electrodes 101 are formed thereon."); a gate electrode provided on the compound semiconductor layer and extending in the first direction and interposed between the source electrode and the drain electrode (Fig. 1B, 102; [0068], "In addition, the two gate electrodes 102 are formed in a region between the source/drain electrodes 101."); wherein the plurality of unit FETs include: a first unit FET; and a second unit FET closer to an end of the plurality of unit FETs in the second direction than the first unit FET (Fig. 1A, 108; [0073], "As illustrated in FIG. 1B, the FET 100 is formed in the active region 104 in the straight-line portions 108, and one straight-line portion 108 functions as one unit FET.", (There are multiple of these illustrated)).
However, Kawano does not teach and a field plate electrode provided between the gate electrode and the drain electrode and above the compound semiconductor layer with an insulating film interposed between the compound semiconductor layer and the field plate electrode; and wherein a first distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the first unit FET is shorter than a second distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the second unit FET.
However, in the same field of endeavor, Kamada teaches and a field plate electrode provided between the gate electrode and the drain electrode and above the compound semiconductor layer with an insulating film interposed between the compound semiconductor layer and the field plate electrode (Fig. 12, F41-44, 111, G41-44, D41-44; [0041], "An insulating film 111 covering the source electrodes S11 to S13 and the drain electrodes D11 to D14 is over the cap layer 106.", [0086], "The field plate portions F41 to F46 are insulated from the gate electrodes G41 to G46 by the insulating film 111. In planar view, the field plate portion F41 is between the gate electrode G41 and the drain electrode D41, the field plate portion F42 is between the gate electrode G42 and the drain electrode D42, the field plate portion F43 is between the gate electrode G43 and the drain electrode D42, the field plate portion F44 is between the gate electrode G44 and the drain electrode D43, the field plate portion F45 is between the gate electrode G45 and the drain electrode D43, and the field plate portion F46 is between the gate electrode G46 and the drain electrode D44."); and wherein a first distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the first unit FET is shorter than a second distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the second unit FET (Fig. 12, Lfp41, Lfp42; [0087], "As illustrated in FIG. 12, the length Lfp42 is larger than the length Lfp41…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device of Kawano with the field plates of Kamada so that the device has "high withstand voltage and high power", (Kamada, [0003]).
Regarding dependent claim 2, Kawano, as previously modified by Kamada, teaches the semiconductor device according to claim 1. However, as previously combined, they do not teach wherein a distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in a unit FET closest to a center of the plurality of unit FETs in the second direction is the shortest in distances in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the plurality of unit FETs.
However, Kamada further teaches wherein a distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in a unit FET closest to a center of the plurality of unit FETs in the second direction is the shortest in distances in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the plurality of unit FETs (Fig. 10, Lfp31,32,33; [0074], "As illustrated in FIG. 10, the length Lfp32 is larger than the length Lfp31, the length Lfp33 is larger than the length Lfp32, and the length Lfp34 is equal to the length Lfp33.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device as described by the combination of Kawano and Kamada with the distances of Kamada so that the device has "high withstand voltage and high power", (Kamada, [0003]).
Regarding dependent claim 3, Kawano, as previously modified by Kamada, teaches the semiconductor device according to claim 1. However, as previously combined, they do not teach wherein a distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in an unit FET closest to an end of the plurality of unit FETs in the second direction is the longest in distances in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the plurality of unit FETs.
However, Kamada further teaches wherein a distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in an unit FET closest to an end of the plurality of unit FETs in the second direction is the longest in distances in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the plurality of unit FETs (Fig. 11, Lfp41-46; [0088], "In the fourth embodiment thus structured, the length Lfp42 is larger than the length Lfp41, the length Lfp43 is larger than the length Lfp42, the length Lfp44 is larger than the length Lfp45, and the length Lfp45 is larger than the length Lfp46.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device as described by the combination of Kawano and Kamada with the distances of Kamada so that the device has "high withstand voltage and high power", (Kamada, [0003]).
Regarding dependent claim 5, Kawano, as previously modified by Kamada, teaches the semiconductor device according to claim 1. However, as previously combined, they do not teach wherein the plurality of unit FETs include a third unit FET provided between the first unit FET and the second unit FET in the second direction, a third distance between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the third unit FET in the second direction is longer than the first distance and shorter than the second distance.
However, Kamada further teaches wherein the plurality of unit FETs include a third unit FET provided between the first unit FET and the second unit FET in the second direction, a third distance between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode in the third unit FET in the second direction is longer than the first distance and shorter than the second distance (Fig. 10, Lfp31,32,33; [0074], "As illustrated in FIG. 10, the length Lfp32 is larger than the length Lfp31, the length Lfp33 is larger than the length Lfp32, and the length Lfp34 is equal to the length Lfp33.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device as described by the combination of Kawano and Kamada with the third plate of Kamada so that the device has "high withstand voltage and high power", (Kamada, [0003]).
Regarding dependent claim 6, Kawano, as previously modified by Kamada, teaches the semiconductor device according to claim 1. However, as previously combined, they do not teach wherein a first length of the field plate electrode in the second direction in the first unit FET is shorter than a second length of the field plate electrode in the second direction in the second unit FET.
However, Kamada further teaches wherein a first length of the field plate electrode in the second direction in the first unit FET is shorter than a second length of the field plate electrode in the second direction in the second unit FET (Fig. 11, Lfp41-46; [0088], "In the fourth embodiment thus structured, the length Lfp42 is larger than the length Lfp41, the length Lfp43 is larger than the length Lfp42, the length Lfp44 is larger than the length Lfp45, and the length Lfp45 is larger than the length Lfp46.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device as described by the combination of Kawano and Kamada with the distances of Kamada so that the device has "high withstand voltage and high power", (Kamada, [0003]).
Regarding independent claim 7, Kawano teaches a semiconductor device comprising: a substrate (Fig. 1B, 109; [0066], "On the semiconductor substrate 109, the epitaxial layer 116 is formed to achieve good crystallinity. "); a compound semiconductor layer provided on the substrate (Fig. 1B, 113, 114; [0067], "...the channel layer 113 is formed of undoped InGaAs; the Schottky barrier layer 114 is formed of AlGaAs…", (In the present application, the semiconductor layer is made froma barrier layer and a channel layer)); and a plurality of unit FETs arranged in a second direction intersecting a first direction (Fig. 1A, 108; [0073], "As illustrated in FIG. 1B, the FET 100 is formed in the active region 104 in the straight-line portions 108, and one straight-line portion 108 functions as one unit FET."), each of the unit FETs including: a source electrode provided on the compound semiconductor layer and extending in the first direction; a drain electrode provided on the compound semiconductor layer and extending in the first direction (Fig. 1B, 101; [0068], "Usually, the contact layer 115 is a high-concentration n-type semiconductor layer, and two source/drain electrodes 101 are formed thereon."); and a gate electrode provided on the compound semiconductor layer and extending in the first direction and interposed between the source electrode and the drain electrode (Fig. 1B, 102; [0068], "In addition, the two gate electrodes 102 are formed in a region between the source/drain electrodes 101.").
However, Kawano does not teach and a field plate electrode provided between the gate electrode and the drain electrode and above the compound semiconductor layer with an insulating film interposed between the compound semiconductor layer and the field plate electrode; wherein in at least one unit FET of the plurality of unit FETs, a first distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode at a center of the at least one unit FET in the first direction is shorter than a second distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode at an end of the at least one unit FET in the first direction.
However, in the same field of endeavor, Kamada teaches and a field plate electrode provided between the gate electrode and the drain electrode and above the compound semiconductor layer with an insulating film interposed between the compound semiconductor layer and the field plate electrode (Fig. 12, F41-44, 111, G41-44, D41-44; [0041], "An insulating film 111 covering the source electrodes S11 to S13 and the drain electrodes D11 to D14 is over the cap layer 106.", [0086], "The field plate portions F41 to F46 are insulated from the gate electrodes G41 to G46 by the insulating film 111. In planar view, the field plate portion F41 is between the gate electrode G41 and the drain electrode D41, the field plate portion F42 is between the gate electrode G42 and the drain electrode D42, the field plate portion F43 is between the gate electrode G43 and the drain electrode D42, the field plate portion F44 is between the gate electrode G44 and the drain electrode D43, the field plate portion F45 is between the gate electrode G45 and the drain electrode D43, and the field plate portion F46 is between the gate electrode G46 and the drain electrode D44."); wherein in at least one unit FET of the plurality of unit FETs, a first distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode at a center of the at least one unit FET in the first direction is shorter than a second distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode at an end of the at least one unit FET in the first direction (Fig. 12, Lfp41, Lfp42; [0087], "As illustrated in FIG. 12, the length Lfp42 is larger than the length Lfp41…").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device of Kawano with the field plates of Kamada so that the device has "high withstand voltage and high power", (Kamada, [0003]).
Claim(s) 4 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawano (US 20110294444 A1), in view of Kamada (US 20180090476 A1) and Hwang (US 20220013659 A1).
Regarding dependent claim 4, Kawano, as previously modified by Kamada, teaches the semiconductor device according to claim 1. However, as previously combined, they do not teach wherein the first distance at the center of the first unit FET in the first direction is shorter than the first distance at the end of the first unit FET in the first direction.
However, in the same field of endeavor, Hwang teaches wherein the first distance at the center of the first unit FET in the first direction is shorter than the first distance at the end of the first unit FET in the first direction (Fig. 11, 412, Fig. 8, 154; [0086], "Referring to FIG. 8, the gate wiring 162 may be connected to the gate electrode 154...", [0105], "The sixth source field plate 411, the third drain field plate 412 and the seventh source field plate 413 may be arranged obliquely with an angle less than 90 degrees with respect to the arrangement direction of the first source field plate 161, the second source field plate 163, and the drain field plate 164.", (Given that the field plates are disposed at an angle, the distance between them and the gate electrode(s) increases towards an end in one direction)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device as described by the combination of Kawano and Kamada with the distances of Hwang so that "reliability of a short circuit may increase", (Hwang, [0107]).
Regarding dependent claim 8, Kawano, as previously modified by Kamada, teaches the semiconductor device according to claim 7. However, as previously combined, they do not teach wherein in a central portion included in the at least one unit FET, the central portion including the center in the first direction and having a constant width in the first direction, a distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode is constant, and a distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode gradually increases from the central portion toward an end in the first direction.
However, Kamada further teaches wherein in a central portion included in the at least one unit FET, the central portion including the center in the first direction and having a constant width in the first direction, a distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode is constant (Fig. 16, F41-46; [0087], "A length Lfp41 of the field plate portion F41 is constant, a length Lfp42 of the field plate portion F42 is constant, a length Lfp43 of the field plate portion F43 is constant, a length Lfp44 of the field plate portion F44 is constant, a length Lfp45 of the field plate portion F45 is constant, and a length Lfp46 of the field plate portion F46 is constant."), and in the same field of endeavor, Hwang teaches and a distance in the second direction between an end of the gate electrode closer to the drain electrode and an end of the field plate electrode closer to the drain electrode gradually increases from the central portion toward an end in the first direction (Fig. 11, 412, Fig. 8, 154; [0086], "Referring to FIG. 8, the gate wiring 162 may be connected to the gate electrode 154...", [0105], "The sixth source field plate 411, the third drain field plate 412 and the seventh source field plate 413 may be arranged obliquely with an angle less than 90 degrees with respect to the arrangement direction of the first source field plate 161, the second source field plate 163, and the drain field plate 164.", (Given that the field plates are disposed at an angle, the distance between them and the gate electrode(s) increases towards an end in one direction)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device as described by the combination of Kawano and Kamada with the distances of Kamada so that the device has "high withstand voltage and high power", (Kamada, [0003]), and the distances of Hwang so that "reliability of a short circuit may increase", (Hwang, [0107]).
Claim(s) 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawano (US 20110294444 A1), in view of Kamada (US 20180090476 A1) and Yamanobe (US 20190259873 A1).
Regarding dependent claim 9, Kawano, as previously modified by Kamada, teaches the semiconductor device according to claim 1. However, as previously combined, they do not teach wherein in the plurality of unit FETs, the field plate electrode is electrically short-circuited to the source electrode.
However, in the same field of endeavor, Yamanobe teaches wherein in the plurality of unit FETs, the field plate electrode is electrically short-circuited to the source electrode (Fig. 1, 208, 204; [0041], "At this time, the P type field plates 208 short-circuit to the potential of the N+ type source layer 204.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device as described by the combination of Kawano and Kamada with the short-circuit of Yamanobe so that "a PN junction diode is formed at the side near the lower end portion of the field plate", (Yamanobe, [0026]).
Regarding dependent claim 10, Kawano, as previously modified by Kamada, teaches the semiconductor device according to claim 7. However, as previously combined, they do not teach wherein in the plurality of unit FETs, the field plate electrode is electrically short-circuited to the source electrode.
However, in the same field of endeavor, Yamanobe teaches wherein in the plurality of unit FETs, the field plate electrode is electrically short-circuited to the source electrode (Fig. 1, 208, 204; [0041], "At this time, the P type field plates 208 short-circuit to the potential of the N+ type source layer 204.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device as described by the combination of Kawano and Kamada with the short-circuit of Yamanobe so that "a PN junction diode is formed at the side near the lower end portion of the field plate", (Yamanobe, [0026]).
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawano (US 20110294444 A1), in view of Kamada (US 20180090476 A1) and Senda (US 20130341680 A1).
Regarding dependent claim 11, Kawano, as previously modified by Kamada, teaches the semiconductor device according to claim 1. However, as previously combined, they do not teach wherein the compound semiconductor layer is a nitride semiconductor layer.
However, in the same field of endeavor, Senda teaches wherein the compound semiconductor layer is a nitride semiconductor layer (Fig. 1, 26; [0021], "...a stacked body 11 provided on the substrate 10 and made of a nitride-based semiconductor, a source electrode 18, a gate electrode 22, a drain electrode 20, a silicon nitride film 26, and a dielectric layer 24.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device as described by the combination of Kawano and Kamada with the nitride semiconductor layer of Senda so as to "perform high-voltage and high-temperature operation in the microwave band or the higher frequency band", (Senda, [0003]).
Regarding dependent claim 12, Kawano, as previously modified by Kamada, teaches the semiconductor device according to claim 7. However, as previously combined, they do not teach wherein the compound semiconductor layer is a nitride semiconductor layer.
However, in the same field of endeavor, Senda teaches wherein the compound semiconductor layer is a nitride semiconductor layer (Fig. 1, 26; [0021], "...a stacked body 11 provided on the substrate 10 and made of a nitride-based semiconductor, a source electrode 18, a gate electrode 22, a drain electrode 20, a silicon nitride film 26, and a dielectric layer 24.").
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the semiconductor device as described by the combination of Kawano and Kamada with the nitride semiconductor layer of Senda so as to "perform high-voltage and high-temperature operation in the microwave band or the higher frequency band", (Senda, [0003]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20190181232 A1,.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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