DETAILED ACTION
Claims 1-11 and 20 are present for examination.
Claims 1-2, 4, 6, 8-9, 11 and 20 have been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Species I (claims 1-11 and 20) in the reply filed on 09/19/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe et al. (US 5,906,000) in view of Cain, III et al. (US 2009/0113132).
With respect to claim 1, Abe et al. teaches a processor configured to input and output commands for data to an outside (see Fig. 5; column 4, lines 66-67 and column 5, lines 1-2; CPU 10 supplies the CPU bus 12 with a request for access; the cache controller 14 detects the request for access);
a data memory configured to store the data as cache data (see Fig. 5 column 3, line 67 and column 4, lines 1-3; cache memory 18 has a data area for storing data items);
a tag memory configured to store a replacement priority with respect to replacement of the cache data (see Fig. 5 column 3, line 67 and column 4, lines 1-3; cache memory 18 has a tag area for storing information. Also in column 5, lines 38-67; cache controller 14 determines that one of the cache blocks in which data replacement should be performed (step S8), and compares a priority stored in the tag of the one cache block, with the priority of the new data to be written… if the priority stored in the tag is lower, i.e. if the priority of the newly read data is higher, the cache controller 14 erases data stored in the cache block in the cache memory, thereby writing the newly read data into the cache block (step S12)); and
a cache controller (see Fig. 5 and column 5, lines 20-21; controller 14)
Abe et al. does not teach wherein the cache controller is configured to determine the replacement priority based on a history of types of the commands with respect to the data stored as the cache data.
However, Cain, III et al. teaches wherein the cache controller is configured to determine the replacement priority based on a history of types of the commands with respect to the data stored as the cache data (see paragraphs 38-39; counter is incremented by one on each write (such a counter could be updated with ECC mechanisms, which already require a read/modify/write per store operation), and decremented on each read. On a replacement, in step 530, the associated counter is compared to a certain threshold value to determine the write-mostly prediction used by the replacement algorithm. In step 540, a replacement algorithm replaces a block associated with a counter greater than or equal to the threshold value. A counter greater than or equal to a threshold value indicates that that the cache block is a "write-mostly" block. Write-mostly blocks using this method are weighted more heavily when selecting victims (i.e., history of write vs read commands in a block)).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the storage controller taught by Abe et al. to include the above mentioned to exhibit better performance (see Cain III, paragraph 32).
With respect to claim 20, Abe et al. teaches a host device configured to execute an application and provide an input/output commands with respect to data based on execution of the application (see Figs. 1 and 5 and column 4, lines 48-67 and column 5, lines 1-2; CPU 10 supplies the CPU bus 12 with a request for access; the cache controller 14 detects the request for access); and
a storage device comprising: a non-volatile memory device configured to store the data according to the input/output commands (see Fig. 1 and column 4, lines 4-5; main storage 20 consist, for example, of a DRAM, and stores data to be accessed by the CPU 10); and
a cache memory (see Figs 1 and 5; column 3, lines 65-67 and column 4, lines 1-3; cache memory 18) configured to:
store the data as cache data (see Fig. 5 column 3, line 67 and column 4, lines 1-3; cache memory 18 has a data area for storing data items),
store a replacement priority with respect to replacement of the cache data (see Fig. 5 column 3, line 67 and column 4, lines 1-3; cache memory 18 has a tag area for storing information. Also in column 5, lines 38-67; cache controller 14 determines that one of the cache blocks in which data replacement should be performed (step S8), and compares a priority stored in the tag of the one cache block, with the priority of the new data to be written… if the priority stored in the tag is lower, i.e. if the priority of the newly read data is higher, the cache controller 14 erases data stored in the cache block in the cache memory, thereby writing the newly read data into the cache block (step S12)).
Abe et al. does not teach determine the replacement priority based on the application, a history of types of the input/output commands for the data stored as the cache data.
However, Cain, III et al. teaches wherein the cache controller is configured to determine the replacement priority based on a history of types of the commands with respect to the data stored as the cache data (see paragraphs 38-39; counter is incremented by one on each write (such a counter could be updated with ECC mechanisms, which already require a read/modify/write per store operation), and decremented on each read. On a replacement, in step 530, the associated counter is compared to a certain threshold value to determine the write-mostly prediction used by the replacement algorithm. In step 540, a replacement algorithm replaces a block associated with a counter greater than or equal to the threshold value. A counter greater than or equal to a threshold value indicates that that the cache block is a "write-mostly" block. Write-mostly blocks using this method are weighted more heavily when selecting victims (i.e., history of write vs read commands in a block)).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Abe et al. to include the above mentioned to exhibit better performance (see Cain III, paragraph 32).
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abe et al. (US 5,906,000) and Cain, III et al. (US 2009/0113132) as applied to claim 1 above, and further in view of Usui (US2009/0063777).
With respect to claim 10, Abe et al. and Cain, III et al. do not teach wherein the data memory is further configured to store the cache data in a full-associative method.
However, Usui teaches wherein the data memory is further configured to store the cache data in a full-associative method (see paragraph 27; cache 20 is classified into any of a plurality of types, i.e., a direct cache, set-associative cache, and full-associative cache, in accordance with the associative. However, the object of this embodiment is a set-associative cache or full-associative cache).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the storage controller taught by Abe et al. and Cain, III et al. to include the above mentioned to improve performance and reliability of the device (see Usui, paragraphs 23).
With respect to claim 11, Abe et al. does not explicitly teach wherein the data comprises a first data and a second data different from the first data, and wherein the cache controller is further configured to, based on the first data being stored in the data memory as a first cache data, the second data being stored in a cache memory and the data memory being full, remove the first cache data based on the priority.
However, Abe et al. teaches wherein if, a cache miss occurs (i.e. if the cache memory 18 does not store the data to be accessed), the cache controller 14 reads the to-be-accessed data from another storage. While the newly read data is output to the CPU 10, the cache controller 14 performs caching of the newly read data… If, on the other hand, the data area of the cache memory 18 has no empty cache block and new data must be written into an occupied cache block, i.e. if it is necessary to replace old data with new one in one of cache blocks (step S6), the cache controller 14 determines that one of the cache blocks in which data replacement should be performed… if the priority stored in the tag is lower, i.e. if the priority of the newly read data is higher, the cache controller 14 erases data stored in the cache block in the cache memory 18, thereby writing the newly read data into the cache block (see column 5, lines 8-66).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the storage controller to include the above mentioned to increase the overall operation speed of the computer (see Abe, column6, lines 46-56).
Allowable Subject Matter
Claims 2-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: No prior art or combination of prior art teaches or suggest wherein the priority table comprises a priority setting list, and wherein the priority setting list comprises a preceding command, a following command sequentially generated for one cache data, and a priority value corresponding to a type of the preceding command and a type of the following command as recited in claim 2.
Response to Arguments
Applicant’s arguments, see page 10, filed 01/22/2026, with respect to the objection of the Specification have been fully considered and are persuasive. The objection of the specification has been withdrawn.
Applicant's arguments with respect to claims 1-11 and 20 have been considered but are moot in view of the new ground(s) of rejection, necessitated by amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ARACELIS RUIZ/Primary Examiner, Art Unit 2139
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