DETAILED ACTION
The present Office Action is in response to Applicant Arguments/Remarks and amended claimed filed on 11/12/2025. Claims 1 and 5-10 have been amended. Claims 11-12 have been added. Claims 1-12 are pending in the application.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments and Arguments
Applicant’s amendments and remarks have been fully considered, with the Examiner’s response set forth below.
(1)In view of the amendments, claim 10 is no longer interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph,
(2) Applicant’s arguments are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
(3) Another iteration of claim analysis has been made. Refer to the corresponding sections of the claim analysis below for details.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2020/0286533), hereinafter Zhang in view of Khwa et al. (US 2022/0230681), hereinafter Khwa, and further in view of Moshayedi (US 2009/0327591), hereinafter Moshayedi.
Regarding claim 1, Zhang teaches a memory system comprising:
a nonvolatile memory including memory cells configured to store user data by a plurality of different storage methods (Zhang, [0030], non-volatile memory cells; [0031], A few example modes include, but are not limited to, SLC program (program a single bit per memory cell), MLC program (programs multiple bits per memory cell), SLC read (reads a single bit per memory cell), MLC read (reads multiple bits per memory cell)); and
a memory controller (Zhang, [0043], Microcontroller 112 provides die-level control of memory operations; [0045]) configured to control the nonvolatile memory,
wherein the nonvolatile memory includes a firmware storage area (Zhang, [0047], code (software) such as a set of instructions (including firmware) … one or more processors 122 c can access code from a storage device in memory structure 126, such as a reserved area of memory cells connected to one or more word lines; [0157], a copy of the first instructions … a copy of the second instructions … and a copy of the third instructions … are stored in non-volatile storage in order to persist the instructions (and possibly parameters) ) and a user data area (Zhang, [0042], Commands and data are transferred between a host 140 and controller 122 via a data bus 120, and between controller 122 and the one or more memory die 108; [0080], when a host needs to read data from or write data to the flash memory), the firmware storage area configured to store firmware and the user data area configured to store user data (Zhang, [0047], [0157]; [0042], [0080]), and firmware corresponding to each of the storage methods is stored in the firmware storage area (Zhang, [0157], the instruction loader 828 may load a copy of the instructions (and possibly parameters) from the memory structure 126 into the core processor storage 812, the sense processor storage 814, and the main processor storage 816; [0166], Main Processor Storage 816 may contain more than one set of instructions for a program operation, as there may be different modes of program operations (e.g., SLC, MLC, TLC etc.).),
wherein the memory controller uses the firmware corresponding to an externally instructed storage method among the storage methods, thereby controls settings of the nonvolatile memory, and
wherein, when having a first storage method switch to the externally instructed second storage method which is different from the first storage method, all data stored in the user data area is deleted.
Zhang does not explicitly teach wherein the memory controller uses the firmware corresponding to an externally instructed storage method among the storage methods, thereby controls settings of the nonvolatile memory, and wherein, when having a first storage method switch to the externally instructed second storage method which is different from the first storage method, all data stored in the user data area is deleted, as claimed.
However, Zhang in view of Khwa teaches wherein the memory controller uses the firmware corresponding to an externally instructed storage method among the storage methods, thereby controls settings of the nonvolatile memory (Khwa, [0074], a host device … may issue a configuration change command to a memory controller … As one example, a configuration change command may be a SLC mode to MLC mode type configuration change command instructing the memory controller … to transition a memory structure, such as a PCRAM cell 100 of a PCRAM structure 10 that is part of a memory structure 20 having a plurality of PCRAM cells 100 (e.g., an array of PCRAM cells 100), from a SLC mode to a MLC mode; Zhang, [0084], The components of controller 122 … use with other components, a portion of a program code (e.g., software or firmware) executable by a (micro) processor or processing circuitry that usually performs a particular function of related functions).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhang to incorporate teachings of Khwa to receive a command by a storage controller to use a specific storage mode, in response, the storage controller executes firmware instructions to control the setting of a nonvolatile memory and performs operations under the specific storage mode. A person of ordinary skill in the art would have been motivated to combine the teachings of Zhang with Khwa because it improves efficiency of the storage system disclosed in Zhang by changing from a first operational mode to a second operational mode in response to a received command.
The combination of Zhang does not explicitly teach wherein, when having a first storage method switch to the externally instructed second storage method which is different from the first storage method, all data stored in the user data area is deleted, as claimed.
However, the combination of Zhang in view of Moshayedi teaches wherein, when having a first storage method switch to the externally instructed second storage method which is different from the first storage method, all data stored in the user data area is deleted (Moshayedi, [0066], The proportions of SLC and MLC that are made available to the user can only be set when the unit is initialized, so if these are to be changed the user would need to copy off all the data, re-initialize the unit and put the data back on again; Note – “copy off all the data” and “reinitialization” indicate that all original data has been deleted.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhang to incorporate teachings of Moshayedi to remove existing data stored in a storage unit when the storage unit configuration is changed and reinitialized. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Zhang with Moshayedi because it improves reliability and flexibility of the storage system disclosed in the combination of Zhang by clearing old data from a storage device when the configuration and/or layout of the storage device has been changed in order to avoid data corruption.
Regarding claim 2, the combination of Zhang teaches all the features with respect to claim 1 as outlined above. The combination of Zhang further teaches the memory system according to claim 1, wherein a plurality of pieces of firmware are stored in the firmware storage area, and the pieces of firmware correspond to the different storage methods (Zhang, [0157], the instruction loader 828 may load a copy of the instructions (and possibly parameters) from the memory structure 126 into … and the main processor storage 816; [0166], Main Processor Storage 816 may contain more than one set of instructions for a program operation, as there may be different modes of program operations (e.g., SLC, MLC, TLC etc.)).
Regarding claim 12, the combination of Zhang teaches all the features with respect to claim 1 as outlined above. The combination of Zhang further teaches the memory system according to claim 1, wherein the storage method is switched without switching to another memory cell or another memory system having different storage methods (Khwa, [0053], to transition a PCRAM cell 100 from a SLC mode of operation to a MLC mode of operation or from a MLC mode of operation to a SLC mode of operation).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhang to incorporate teachings of Khwa to transition PCRAM cells from a SLC mode of operation to a MLC mode of operation. A person of ordinary skill in the art would have been motivated to combine the teachings of Zhang with Khwa because it improves efficiency of the storage system disclosed in Zhang by changing from a first operational mode to a second operational mode in response to a received command.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Zhang, Khwa, and Moshayedi as applied to claim 2 above, and further in view of Yu et al. (US2014/0006688), hereinafter Yu.
Regarding claim 3, the combination of Zhang teaches all the features with respect to claim 2 as outlined above. The combination of Zhang does not explicitly teach the memory system according to claim 2, wherein switching firmware configured to switch the storage methods of the nonvolatile memory is further stored in the firmware storage area, as claimed.
However, the combination of Zhang in view of Yu teaches the memory system according to claim 2, wherein switching firmware configured to switch the storage methods of the nonvolatile memory is further stored in the firmware storage area (Yu, [0129], Once the TLC chip is hardwired or firmware programmed to MLC or SLC mode, the TLC chip cannot used as TLC, unless the mode is changed by the hardwired control or by a firmware program; [0093], ETL DRAM buffer 194 may also store … firmware; [0101], so that endurance controller 192 may write data from ETL DRAM buffer 194 to flash memory 124 when power fails).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhang to incorporate teachings of Yu to include a switching firmware and store the switch firmware in a nonvolatile storage, such as memory structure 126 (in Zhang). A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Zhang with Yu because it improves efficiency and performance of the storage system disclosed in the combination of Zhang by allowing the storage system to switch into a different operational mode by executing a firmware.
Claim(s) 4 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Zhang, Khwa, Moshayedi, and Yu as applied to claim 3 above, and further in view of Segawa et al. (US 10,203,740), hereinafter Segawa and Brandt et al. (US11,256,620), hereinafter Brandt.
Regarding claim 4, the combination of Zhang teaches all the features with respect to claim 3 as outlined above. The combination of Zhang does not explicitly teach the memory system according to claim 3, wherein the memory controller loads and executes the firmware corresponding to the instructed storage method after loading and executing the switching firmware in switching to the instructed storage method, as claimed.
However, the combination of Zhang in view of Segawa teaches the memory system according to claim 3, wherein the memory controller loads and executes the firmware corresponding to the instructed storage method after loading and executing the switching firmware in switching to the instructed storage method (Segawa, col.16, lines 7-35, In that regard, a computer program for switching the main memory 30 from the power saving mode to the normal mode is stored in the internal memory 125, which is promptly accessible to the processor core 101 upon returning from the idle state. Thus, firstly, the processor core 101 executes that computer program, and then executes the computer programs stored in the main memory 30; col.22, lines 16 – 31, Meanwhile, of the computer programs of the process switcher 411, the computer programs corresponding to operations which should be performed during the power saving mode of the main memory 30 need to be loaded either in the internal memory 125 of the SoC 100).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhang to incorporate teachings of Segawa to switch from a first mode to a second mode after loading and executing a switching firmware . A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Zhang with Segawa because it improves efficiency and performance of the storage system disclosed in the combination of Zhang by allowing the storage system to switch into a different operational mode by executing a switching firmware.
The combination of Zhang teachings loading and executing firmware for switching a first mode to a second mode, nevertheless the combination of Zhang does not explicitly teach switching to the instructed storage method, as claimed.
However, the combination of Zhang in view of Brandt teaches wherein the memory controller loads and executes the firmware corresponding to the instructed storage method after loading and executing the switching firmware in switching to the instructed storage method (Brandt, col.2, lines 52-65, The firmware then switches from the SLC mode to a TLC mode).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhang to include a switching firmware to switch a SLC mode to a TLC mode for read/write. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Zhang with Brandt because it improves efficiency and performance of the storage system disclosed in the combination of Zhang to switch to a desired read/write mode by executing a firmware.
Regarding claim 5, the combination of Zhang teaches all the features with respect to claim 4 as outlined above. The combination of Zhang further teaches the memory system according to claim 4, wherein all of the data stored in the user data area is deleted by executing the switching firmware (Moshayedi, [0066], The proportions of SLC and MLC that are made available to the user can only be set when the unit is initialized, so if these are to be changed the user would need to copy off all the data, re-initialize the unit and put the data back on again; Note – “copy off all the data” and “reinitialization” indicate that all existing data has been deleted.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhang to incorporate teachings of Moshayedi to remove existing data stored in a storage unit when the storage unit configuration is changed and reinitialized. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Zhang with Moshayedi because it improves efficiency and flexibility of the storage system disclosed in the combination of Zhang by clearing old data from a storage device when the configuration and/or layout of the storage device has been changed in order to avoid data corruption.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Zhang, Khwa, and Moshayedi as applied to claim 1 above, and further in view of Nakazato (US 2006/0176514), hereinafter Nakazato.
Regarding claim 6, the combination of Zhang teaches all the features with respect to claim 1 as outlined above. The combination of Zhang does not explicitly teach the memory system according to claim 1, wherein one piece of firmware is stored in the firmware storage area, the one piece of firmware includes a plurality of individual modules and a common module, an individual module of the individual modules is configured to perform a process corresponding to each of the plurality of different storage methods, and the common module is configured to perform a common process regardless of the storage methods, as claimed.
However, the combination of Zhang in view of Nakazato teaches the memory system according to claim 1, wherein one piece of firmware is stored in the firmware storage area (Nakazato, Fig.2A, see flash memory 123 stores second firmware portion), the one piece of firmware includes a plurality of individual modules and a common module, an individual module of the individual modules is configured to perform a process corresponding to each of the plurality of different storage methods, and the common module is configured to perform a common process regardless of the storage methods (Nakazato, [0060], and the second firmware portion includes a plurality of modules, e.g., a module defining control content common to the consumable units (unit common module) and modules respectively defining the control content unique to the respective consumable units (unit unique modules) (see FIG. 2B); Zhang, [0166])).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhang to incorporate teachings of Nakazato to organize firmware into groups of common modules and unique modules. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Zhang with Nakazato because it improves efficiency and performance of the storage system disclosed in Zhang by deduplicating identical redundant portions of firmware for different modes of program operations.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Zhang, Khwa, Moshayedi, and Nakazato as applied to claim 6 above, and further in view of Nagashima et al. (US2015/0078094), hereinafter Nagashima.
Regarding claim 7, the combination of Zhang teaches all the features with respect to claim 6 as outlined above. The combination of Zhang does not explicitly teach the memory system according to claim 6, wherein the memory controller selects and executes the individual module corresponding to the instructed storage method and the common module after all of the data stored in the user data area has been deleted in switching to the instructed storage method, as claimed.
However, the combination of Zhang in view of Nagashma teaches the memory system according to claim 6, wherein the memory controller selects and executes the individual module corresponding to the instructed storage method and the common module after all of the data stored in the user data area has been deleted in switching to the instructed storage method (Nagashima, [0047], When using commands, the control unit 23 of the memory controller 2 transmits an instruction for the reading method to the memory I/F 22. The memory I/F 22 inputs a command corresponding to the instruction from the control unit 23 to the semiconductor memory unit 3 … If the reading method is designated by setting the parameters, when changing the reading method, the control unit 23 transmits an instruction to change the internal parameters to the semiconductor memory unit 3 through the memory I/F 22; Zhang, [0165], Main Processor 806 determines what set of instructions Main Processor 806 needs to execute for the memory command; [0166]; Moshayedi, [0066], The proportions of SLC and MLC that are made available to the user can only be set when the unit is initialized, so if these are to be changed the user would need to copy off all the data, re-initialize the unit and put the data back on again; Note – “copy off all the data” and “reinitialization” indicate that all original data has been deleted).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhang to incorporate teachings of Nagashima to transmits instructions to memory dies (in Zhang) to change from a first operational mode to a second operational mode by executing a specific set of firmware (i.e. instructions in Zhang) loaded to the main processor storage 816. A person of ordinary skill in the art would have been motivated to combine the teachings of Zhang with Nagashima because it improves efficiency of the storage system disclosed in the storage disclosed in Zhang by changing from a first operational mode to a second operational mode in response to a received command.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2020/0286533), hereinafter Zhang in view of Nagashima et al. (US2015/0078094), hereinafter Nagashima, and further in view of Moshayedi (US2009/0327591), hereinafter Moshayedi.
Regarding claim 8, Zhang teaches a control method of controlling a memory system, the memory system comprising a nonvolatile memory including memory cells configured to store user data by a plurality of different storage methods (Zhang,[0030], non-volatile memory cells; [0031], A few example modes include, but are not limited to, SLC program (program a single bit per memory cell), MLC program (programs multiple bits per memory cell), SLC read (reads a single bit per memory cell), MLC read (reads multiple bits per memory cell)), the control method comprising:
loading firmware corresponding to a first storage method (SLC) from the nonvolatile memory and executing the loaded firmware (Zhang, [0157], the instruction loader 828 may load a copy of the instructions (and possibly parameters) from the memory structure 126 into the core processor storage 812, the sense processor storage 814, and the main processor storage 816; [0166], Main Processor Storage 816 may contain more than one set of instructions for a program operation, as there may be different modes of program operations (e.g., SLC, MLC, TLC etc.); [0170]; [0178]); and
loading and executing firmware corresponding to a second storage method (MLC or TLC) different from the first storage method (Zhang, [0157], the instruction loader 828 may load a copy of the instructions (and possibly parameters) from the memory structure 126 into the core processor storage 812, the sense processor storage 814, and the main processor storage 816; [0166], Main Processor Storage 816 may contain more than one set of instructions for a program operation, as there may be different modes of program operations (e.g., SLC, MLC, TLC etc.); [0170]; [0178]) after deleting all data in an area storing user data in the nonvolatile memory when an instruction to switch to the second storage method is received.
Zhang does not explicitly teach loading and executing firmware corresponding to a second storage method after deleting data in an area storing user data in the nonvolatile memory when an instruction to switch to the second storage method is received, as claimed.
However, Zhang in view of Nagashma teaches loading and executing firmware corresponding to a second storage method when an instruction to switch to the second storage method is received (Nagashima, [0047], The control unit 23 of the memory controller 2 determines whether to use the fast read mode or the normal read mode (reading method). When using commands, the control unit 23 of the memory controller 2 transmits an instruction for the reading method to the memory I/F 22. The memory I/F 22 inputs a command corresponding to the instruction from the control unit 23 to the semiconductor memory unit 3 … If the reading method is designated by setting the parameters, when changing the reading method, the control unit 23 transmits an instruction to change the internal parameters to the semiconductor memory unit 3 through the memory I/F 22).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhang to incorporate teachings of Nagashima to have a controller to transmits instructions to memory dies (in Zhang) to change from a SLC operational mode to a TLC operational mode by executing a specific set of firmware (i.e. instructions in Zhang) loaded to the main processor storage 816. A person of ordinary skill in the art would have been motivated to combine the teachings of Zhang with Nagashima because it improves efficiency of the storage system disclosed in the storage disclosed in Zhang by changing from a first operational mode to a second operational mode in response to a received command.
The combination of Zhang does not explicitly teach loading and executing firmware corresponding to a second storage method after deleting all data in an area storing user data in the nonvolatile memory, as claimed.
However, the combination of Zhang in view of Moshayedi teaches loading and executing firmware corresponding to a second storage method different from the first storage method (Zhang, [0157]; [0166]; [0170]; [0178]) after deleting all data in an area storing user data in the nonvolatile memory (Moshayedi, [0066], The proportions of SLC and MLC that are made available to the user can only be set when the unit is initialized, so if these are to be changed the user would need to copy off all the data, re-initialize the unit and put the data back on again; Note – copy off all the data and reinitialization indicating all existing data has been deleted.) when an instruction to switch to the second storage method is received (Nagashima, [0047]; Note – Nagashima teaches a controller determines a storage mode (such as switching from SLC mode to a TLC mode) and issues instructions to a memory die (in Zhang) to set up the storage mode. Existing data has been deleted when the instructions are issued to the memory die.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhang to include a switching firmware that initiates a process to switch from a first operational mode to a second operational mode, which includes receiving a command, backing up existing data, reinitialization (deleting all of the existing data), and sending instructions to memory dies/controllers to set up the second operational mode. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Zhang with Moshayedi because it improves efficiency and reliability of the system disclosed in the combination of Zhang by deleting data written in previous operational mode when switching to a new operational mode.
Regarding claim 9, Zhang teaches a control method of controlling a memory system, the memory system comprising a nonvolatile memory including memory cells configured to store user data by a plurality of different storage methods (Zhang, [0030], non-volatile memory cells; [0031], A few example modes include, but are not limited to, SLC program (program a single bit per memory cell), MLC program (programs multiple bits per memory cell), SLC read (reads a single bit per memory cell), MLC read (reads multiple bits per memory cell)), the control method comprising:
loading firmware from the nonvolatile memory and selecting and executing a module corresponding to a first storage method (SLC) included in the loaded firmware (Zhang, [0157], the instruction loader 828 may load a copy of the instructions (and possibly parameters) from the memory structure 126 into the core processor storage 812, the sense processor storage 814, and the main processor storage 816; [0166], Main Processor Storage 816 may contain more than one set of instructions for a program operation, as there may be different modes of program operations (e.g., SLC, MLC, TLC etc.); [0170]; [0178]); and
selecting a module corresponding to a second storage method different from the first storage method from the firmware and executing the selected module (Zhang, [0157], the instruction loader 828 may load a copy of the instructions (and possibly parameters) from the memory structure 126 into the core processor storage 812, the sense processor storage 814, and the main processor storage 816; [0165]; [0166], Main Processor Storage 816 may contain more than one set of instructions for a program operation, as there may be different modes of program operations (e.g., SLC, MLC, TLC etc.); [0170]; [0178]) after deleting all date in an area storing user data in the nonvolatile memory when an instruction to switch to the second storage method is received.
Zhang does not explicitly teach selecting a module corresponding to a second storage method different from the first storage method from the firmware and executing the selected module after deleting all date in an area storing user data in the nonvolatile memory when an instruction to switch to the second storage method is received, as claimed.
However, Zhang in view of Nagashma teaches selecting a module corresponding to a second storage method different from the first storage method from the firmware and executing the selected module (Zhang, [0157], the instruction loader 828 may load a copy of the instructions (and possibly parameters) from the memory structure 126 into the core processor storage 812, the sense processor storage 814, and the main processor storage 816; [0165]; [0166], Main Processor Storage 816 may contain more than one set of instructions for a program operation, as there may be different modes of program operations (e.g., SLC, MLC, TLC etc.); [0170]; [0178]) when an instruction to switch to the second storage method is received (Nagashima, [0047], The control unit 23 of the memory controller 2 determines whether to use the fast read mode or the normal read mode (reading method). When using commands, the control unit 23 of the memory controller 2 transmits an instruction for the reading method to the memory I/F 22. The memory I/F 22 inputs a command corresponding to the instruction from the control unit 23 to the semiconductor memory unit 3 … If the reading method is designated by setting the parameters, when changing the reading method, the control unit 23 transmits an instruction to change the internal parameters to the semiconductor memory unit 3 through the memory I/F 22).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhang to incorporate teachings of Nagashima to have a controller to determine a desired storage method and transmits instructions to memory dies (in Zhang) to change from a SLC operational mode to a TLC operational mode by executing a specific set of firmware (i.e. instructions in Zhang) loaded to the main processor storage 816. A person of ordinary skill in the art would have been motivated to combine the teachings of Zhang with Nagashima because it improves efficiency of the storage system disclosed in the storage disclosed in Zhang by changing from a first operational mode to a second operational mode in response to a received command.
The combination of Zhang does not explicitly teach selecting a module corresponding to a second storage method and executing the selected module after deleting all data in an area storing user data in the nonvolatile memory, as claimed.
However, the combination of Zhang in view of Moshayedi teaches selecting a module corresponding to a second storage method different from the first storage method from the firmware and executing the selected module (Zhang, [0157]; [0166]; [0170]; [0178]) after deleting data in an area storing user data in the nonvolatile memory (Moshayedi, [0066], The proportions of SLC and MLC that are made available to the user can only be set when the unit is initialized, so if these are to be changed the user would need to copy off all the data, re-initialize the unit and put the data back on again; Note – “copy off all the data” before initialization indicating all existing data has been deleted.) when an instruction to switch to the second storage method is received (Nagashima, [0047]; Note – Nagashima teaches a controller determines a storage mode (such as switching from SLC mode to a TLC mode) and issues instructions to a memory die (in Zhang) to set up the storage mode. Existing data has been deleted when the instructions are issued to the memory die.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhang to include a switching firmware that initiates a process to switch from a first operational mode to a second operational mode, which includes receiving a command, backing up existing data, reinitialization (deleting all of the existing data), and sending instructions to memory dies/controllers to set up the second operational mode. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Zhang with Moshayedi because it improves efficiency and reliability of the system disclosed in the combination of Zhang by deleting data written in previous operational mode when switching to a new operational mode.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2020/0286533), hereinafter Zhang in view of Nagashima et al. (US2015/0078094), hereinafter Nagashima, and further in view of Okada et al. (US2018/0018231), hereinafter Okada and Moshayedi (US 2009/0327591), hereinafter Moshayedi.
Regarding claim 10, Zhang teaches an information-processing device capable of reading and writing user data from and to a memory system (Zhang, [0041], each memory die 108 includes a memory structure 126, control circuitry 110, and read/write circuits 128 … Read/write circuits 128 include multiple sense blocks 150 including SB1, SB2, . . . , SBp (sensing circuitry) and allow a page of memory cells to be read or programmed in parallel; [0042]), wherein the memory system including:
a nonvolatile memory (Fig.1, 126) including memory cells configured to store user data by a plurality of different storage methods (Zhang, [0030], non-volatile memory cells; [0031], A few example modes include, but are not limited to, SLC program (program a single bit per memory cell), MLC program (programs multiple bits per memory cell), SLC read (reads a single bit per memory cell), MLC read (reads multiple bits per memory cell))); and
a memory controller (Zhang, [0043], microcontroller (MCU) 112; Fig.1, MCU 112) configured to control the nonvolatile memory (Zhang, [0043], Microcontroller 112 provides die-level control of memory operations; [0045]), the information-processing device (Zhang, Fig.1, controller 122) comprising:
input circuitry configured to set a storage method of the user data in the nonvolatile memory to a second storage method different from a first storage method which has been set;
a processor (Zhang, Fig.1, processor 122c) configured to instruct the memory controller to switch to the second storage method (Zhang, [0048], One or more processors 122 c can issue commands to control circuitry 110 (or another component of memory die 108) via Memory Interface 122 d; [0166], Main Processor 806 determines the addresses for the set of instructions Main Processor 806 needs to execute for the memory operation; ); and
an interface (Zhang, Fig.1, MI 122d) configured to transmit an instruction from the processor to the memory controller and to receive a response from the memory controller (Zhang, [0048], Memory interface 122 d, in communication with ROM 122 a, RAM 122 b and processor 122 c, is an electrical circuit that provides an electrical interface between controller 122 and one or more memory die 108 … One or more processors 122 c can issue commands to control circuitry 110 (or another component of memory die 108) via Memory Interface 122 d; [0094]),
wherein, when having the first method switch to the second storage method, all data stored in the nonvolatile memory is deleted.
Zhang does not explicitly teach an information-processing device comprising input circuitry configured to set a storage method of the user data in the nonvolatile memory to a second storage method different from a first storage method which has been set; a processor configured to instruct the memory controller to switch to the second storage method, and an interface receive a response from the memory controller, wherein, when having the first method switch to the second storage method, all data stored in the nonvolatile memory is deleted, as claimed.
However, Zhang in view of Nagashima teaches the information-processing device (Nagashima, Fig.1, see memory controller 2) comprising:
input circuitry (Nagashima, Fig.1, control unit 23) configured to set a storage method of the user data in the nonvolatile memory to a second storage method different from a first storage method which has been set (Nagashima, [0047], The control unit 23 of the memory controller 2 determines whether to use the fast read mode or the normal read mode (reading method));
a processor (Nagashima, Fig.1, control unit 23) configured to instruct the memory controller (Zhang, Fig.1, MCU 112) to switch to the second storage method (Nagashima, [0047], When using commands, the control unit 23 of the memory controller 2 transmits an instruction for the reading method to the memory I/F 22. The memory I/F 22 inputs a command corresponding to the instruction from the control unit 23 to the semiconductor memory unit 3; Zhang, Fig.1)
an interface (Fig.1, memory I/F 22) configured to transmit an instruction from the processor (Nagashima, Fig.1, control unit 23) to the memory controller (Zhang, Fig.1 MCU 112).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhang to incorporate teachings of Nagashima to have a controller to determine a desired storage method and transmits instructions to memory dies (in Zhang) to change from a SLC operational mode to a TLC operational mode by executing a specific set of firmware (i.e. instructions in Zhang) loaded to the main processor storage 816. A person of ordinary skill in the art would have been motivated to combine the teachings of Zhang with Nagashima because it improves efficiency of the storage system disclosed in the storage disclosed in Zhang by changing from a first operational mode to a second operational mode in response to a received command.
The combination of Zhang does not explicitly teach an interface configured to receive a response from the memory controller and wherein, when having the first method switch to the second storage method, all data stored in the nonvolatile memory is deleted, as claimed, as claimed.
However, the combination of Zhang in view of Okada teaches an interface configured to receive a response from the memory controller (Okada, [0030], FIG. 1 shows an overview of an embodiment. A storage unit 10 includes a storage controller 100 and storage, devices 310 to 340; [0032], Each of the storage devices 310 to 340 includes a device controller 310; [0039], The storage controller 100 includes … a storage interface 140, which is a device that performs communication with the storage 300; [0061], The device controller 410 includes … the processor 415; [0128], The processor 415 returns the restored data to the storage controller 100 ).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhang to incorporate teachings of Okada to return a response from a device controller (i.e. microcontroller 112 in Zhang) to an interface in an information-processing device (i.e. MI 122d in controller 122). A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Zhang with Okada because it improves efficiency and communication of the storage system disclosed in the combination of Zhang by providing required data/messages from a storage device to a control unit.
The combination of Zhang does not teach wherein, when having the first method switch to the second storage method, all data stored in the nonvolatile memory is deleted, as claimed, as claimed.
However, the combination of Zhang in view of Moshayedi teaches wherein, when having the first method switch to the second storage method, all data stored in the nonvolatile memory is deleted (Moshayedi, [0066], The proportions of SLC and MLC that are made available to the user can only be set when the unit is initialized, so if these are to be changed the user would need to copy off all the data, re-initialize the unit and put the data back on again; Note – copy off all the data and reinitialization indicating all existing data has been deleted.).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhang to incorporate teachings of Moshayedi to remove existing data stored in a storage unit when the storage unit configuration is changed and reinitialized. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Zhang with Moshayedi because it improves efficiency and flexibility of the storage system disclosed in the combination of Zhang by clearing old data from a storage device when the configuration and/or layout of the storage device has been changed in order to avoid data corruption.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Zhang, Khwa, and Moshayedi as applied to claim 1 above, and further in view of Jung et al. (US2018/0081594), hereinafter Jung.
Regarding claim 11, the combination of Zhang teaches all the features with respect to claim 1 as outlined above. The combination of Zhang does not explicitly teach the memory system according to claim 1, wherein the storage method is switched based on requirement of data retention (DR) period in which the data written to the memory cells is maintained in a state in which the data is correctly read from the memory cells, as claimed.
However, the combination of Zhang in view of Jung teaches the memory system according to claim 1, wherein the storage method is switched based on requirement of data retention (DR) period in which the data written to the memory cells is maintained in a state in which the data is correctly read from the memory cells (Jung, [0104]; [0113]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Zhang to incorporate teachings of Jung to switch from a TLC mode to a SLC mode when data retention time is less than a threshold and the P/E cycle count exceeds a threshold. A person of ordinary skill in the art would have been motivated to combine the teachings of the combination of Zhang with Jung because it improves performance and reliability of the storage system disclosed in the combination of Zhang by storing data in faster and more reliable type of memory cells for short-term storage.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NANCI N WONG/Primary Examiner, Art Unit 2137