DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6, 7, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Logvinov et al (“Radio Receivers for Systems of Fixed and Mobile Communications”).
Regarding claim 1, Figure 3.26 of Logvinov discloses polyphase filter circuitry, comprising:
an input node configured to receive an input signal VIN having a dominant frequency fPPF [Input]
a common-source amplifier circuit [VT1]
wherein the common-source amplifier circuit comprises a field-effect transistor M1 with its gate terminal connected to the input node [VT1] and with a capacitor CPFF connected to its source terminal [C3]
for the common-source amplifier circuit, the output resistance RM1 seen at the source terminal of the field-effect transistor M1 and the capacitance of the capacitor CPFF are configured to define the frequency response of the common-source amplifier circuit so that, based on the input signal VIN, a signal VLEAD is generated at the drain terminal of the transistor M1 which leads the input signal VIN in phase by a given phase shift ∆ϕLEAD and a signal VLAG is generated at the source terminal of the transistor M1 which lags the input signal VIN in phase by a given phase shift ∆ϕLAG [description of Figure 3.26]
Regarding claim 2, Figure 3.26 of Logvinov discloses
a source-follower circuit [VT1]
wherein the source-follower circuit comprises a field-effect transistor M1 with its gate terminal connected to the input node [VT1] and with a capacitor CPPF connected to its source terminal [C3]
for the source-follower circuit, the output resistance RM1 seen at the source terminal of the field-effect transistor M1 and the capacitance of the capacitor CPPF are configured to define the frequency response of the source-follower circuit so that, based on the input signal VIN, a signal VLAG is generated at the source terminal of the transistor M1 which lags the input signal VIN in phase by a given phase shift ∆ϕLAG; and the signal VLEAD of the common-source amplifier circuit and the signal VLAG of the source-follower circuit are output signals of the polyphase filter circuitry [description of Figure 3.26]
Regarding claim 3, Figure 3.26 of Logvinov discloses
wherein, for each common-source amplifier circuit or source-follower circuit the capacitor CPPF is connected between, or substantially directly between, the source terminal of the transistor M1 and a supply voltage node
or the capacitor CPPF is implemented as a capacitor CPPF1 connected between, or substantially directly between, the source terminal of the transistor M1 and a first supply voltage node and a capacitor CPPF2 connected between, or substantially directly between, the source terminal of the transistor M1 and a second supply voltage node [C2 and C3]
Regarding claim 6, Figure 3.26 of Logvinov discloses wherein, for each common-source amplifier circuit or source-follower circuit, a current source or a resistor is connected between the source terminal of the transistor M1 and a supply voltage node [R2], optionally wherein that current source or resistor is implemented as a field-effect transistor.
Regarding claim 7, Figure 3.26 of Logvinov discloses wherein: for each common-source amplifier circuit or source-follower circuit, the field-effect transistors of the common-source amplifier circuit are of the same or similar type and/or of the same semiconductor fabrication process; and/or said field-effect transistors are of the same or similar type and/or of the same semiconductor fabrication process [description of Figure 3.26].
Regarding claim 15, Figure 3.26 of Logvinov discloses integrated circuitry, such as an IC chip, comprising the polyphase filter circuitry [description of Figure 3.26].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 5, 8, 9, 12-14, 16, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Logvinov et al (“Radio Receivers for Systems of Fixed and Mobile Communications”).
Regarding claim 4, Logvinov does not explicitly disclose wherein, for each common-source amplifier circuit or source-follower circuit: the capacitor CPPF, or each of the capacitors CPPF1 and CPPF2, is implemented as a MOS capacitor, optionally as a field-effect transistor configured as a MOS capacitor.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Logvinov by using MOS capacitors as a matter of simple design-choice, since it was well-known in the art to use MOS capacitors.
Regarding claim 5, Logvinov does not explicitly disclose wherein, for each common-source amplifier circuit, a resistor RDRAIN is connected between the drain terminal of the transistor M1 and a supply voltage node, wherein, for each common-source amplifier circuit, the resistor RDRAIN is implemented as a diode-connected field-effect transistor.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Logvinov by using a diode-connected field-effect transistor as a matter of simple design-choice, since it was well-known in the art to use diode-connected field-effect transistors as resistors.
Regarding claim 8, Logvinov does not explicitly disclose multi-phase clock generation circuitry comprising: the polyphase filter circuitry; and a source clock generation circuit configured to generate and provide to the polyphase filter circuitry the input signal VIN as a source clock signal, the output signals of the polyphase filter circuitry being output clock signals of the multi-phase clock generation circuitry having different relative phases from one another.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Logvinov by using it to filter clock signals as a matter of simple design-choice, since it was well-known in the art to use filters with clock signals.
Regarding claim 9, Figure 3.26 of Logvinov discloses a source-follower circuit, comprising:
an input node configured to receive an input signal VIN having a dominant frequency fPPF [Input]
a field-effect transistor M1 with its gate terminal connected to the input node [VT1]
a capacitor CPPF connected to the source terminal of the field-effect transistor M1 [C3]
wherein the output resistance RM1 seen at the source terminal of the field-effect transistor M1 and the capacitance of the capacitor CPPF are configured to define the frequency response of the source-follower circuit so that, based on the input signal VIN, a signal VLAG is generated at the source terminal of the transistor M1 which lags the input signal VIN in phase by a given phase shift ∆ϕLAG [description of Figure 3.26]
the capacitor CPFF is substantially directly connected between the source terminal of the field-effect transistor and a supply voltage node and is implemented a capacitor CPPF1 connected between, or substantially directly between, the source terminal of the transistor M1 and a first supply voltage node, and a capacitor CPPF2 connected between, or substantially directly between, the source terminal of the transistor M1 and a second supply voltage node [C2 and C3]
Logvinov does not explicitly disclose the capacitor CPPF, or each of the capacitors CPPF1 and CPPF2, is implemented as a field-effect transistor configured as a MOS capacitor.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Logvinov by using MOS capacitors as a matter of simple design-choice, since it was well-known in the art to use MOS capacitors.
Regarding claim 12, Figure 3.26 of Logvinov, as applied to claim 9, discloses wherein: a current source or a resistor is connected between the source terminal of the transistor and a supply voltage node [R2], optionally wherein that current source or resistor is implemented as a field- effect transistor.
Regarding claim 13, Logvinov, as applied to claim 9, does not explicitly disclose wherein: the drain terminal of the transistor is connected directly to its supply voltage node.
However, it would have been obvious to of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Logvinov, as applied to claim 9, by removing the drain resistor as a matter of simple design-choice, since it was well-known in the art to connect drains directly to supply in source-follower circuits.
Regarding claim 14, Figure 3.26 of Logvinov, as applied to claim 9, discloses wherein each field-effect transistor is of the same or similar type and/or of the same semiconductor fabrication process [description of Figure 3.26].
Regarding claim 16, Figure 3.26 of Logvinov, as applied to claim 8, discloses integrated circuitry, such as an IC chip, comprising the multi-phase clock generation circuitry [description of Figure 3.26].
Regarding claim 17, Figure 3.26 of Logvinov, as applied to claim 9, discloses integrated circuitry, such as an IC chip, comprising the source-follower circuit [description of Figure 3.26].
Conclusion
Applicant's submission of an information disclosure statement under 37 CFR 1.97(c) with the timing fee set forth in 37 CFR 1.17(p) on 04/24/2026 prompted the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 609.04(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tomi S Skibinski whose telephone number is (571)270-7581. The examiner can normally be reached Mon. - Thurs. 8am - 6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at (571)270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TOMI SKIBINSKI/Primary Examiner, Art Unit 2836
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