SYSTEM INCLUDING PLURALITY OF HOSTS AND PLURALITY OF MEMORY DEVICES AND OPERATION METHOD THEREOF

DETAILED ACTION Claims 1, 3-16 and 18-21 are pending in this application. Claims 1, 3-4, 9-11, 16, 18-19 and 21 are rejected. Claims 5-8, 12-15 and 20 are objected to. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 3-4, 9-11, 16, 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. PGPub No. 2019/0333570) in view of Lee et al. (U.S. PGPub No. 2025/0208780). Claim 1 Kim (2019/0333570) teaches: A system comprising: […] each of the plurality of memory device[s] comprising a plurality of memory areas; P. 0077 the memory area of a memory device shared by at least two processors is partitioned into at least two memory regions a host configured to communicate with the plurality of memory device[s]; and FIG. 1 first and second processors 20, 30 coupled to common memory 100 a switch circuit configured to store mapping information for a memory area allocated to the host from among the plurality of memory areas […] P. 0049 memory controller 60 may store a mapping table that includes information regarding the independent memory mapping associated with each of the memory regions; P. 0032 and FIG. 3 memory controller 60 may send refresh masking information regarding at least one memory region wherein a first memory device […] is configured to receive at least a portion of the mapping information from the switch circuit, P. 0032 and FIG. 3 MRS circuit 131 on common memory device 100a may store refresh masking information regarding at least one memory region in response to the MRS setting command received from the memory controller 60 perform a refresh operation on a first memory area from a plurality of first memory areas in the first memory device based on the portion of the mapping information indicating that the first memory area is allocated to the host, and P. 0033 refresh circuit 133 may control a refresh to be selectively performed on a memory region according to the refresh masking information; P. 0047 MRS setting command may also include identification information regarding the processor that is associated with the memory region skip the refresh operation on a second memory area not allocated to the host from among the plurality of first memory areas. P. 0034 refresh circuit 133 will perform the self-refresh on memory banks associated with at least one unmasked memory region, but will not perform a self-refresh on memory regions that are restricted based on the received masking information; P. 0058 self-refresh masking information may indicates self-refresh is performed on each of the first and second memory regions 210 and 220, and whether the first processor 20 and/or the second processor 30 is enabled Kim does not explicitly teach the system comprising a plurality of memory devices. Lee (2025/0208780) teaches: a plurality of memory devices, each of the plurality of memory devices comprising a plurality of memory areas; P. 0064 and FIG. 2 memory areas of the plurality of memory cards 850A, 850B, 850C, 850D in the pooled memory device 810 a host configured to communicate with the plurality of memory devices; and FIG. 2 and P. 0060 hosts 102A and 102B are coupled to memory cards 850A-D a switch circuit configured to store mapping information for a memory area allocated to the host from among the plurality of memory areas in the plurality of memory devices, FIG. 2 Controller 830; FIG. 8 Controller 430; FIG. 7 and P. 0090 the address range table in partition manager 332 within controller 330 may include ownership information indicating which host processor uses each of logical address ranges in pooled memory 310 It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Kim with the plurality of memory devices taught by Lee. The motivation being to provide enormous persistent memory capacity and on-demand memory resources to resource-limited computing devices (see Lee P. 0064) The systems of Kim and Lee are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems. Therefore it would have been obvious to combine Kim with Lee to obtain the invention as recited in claims 1-8. Claim 3 Kim (2019/0333570) teaches: The system of claim 1, wherein the first memory device comprises a memory controller configured to provide a refresh command to the plurality of first memory areas, based on an allocation flag indicating whether the plurality of first memory areas are allocated to the host. P. 0032 and FIG. 3 MRS circuit 131, within control circuit 130 of common memory device 100a, may store self-refresh masking information regarding at least one memory region; P. 0045 each of the processors 20 and 30 may use the corresponding memory region 210 or 220 as a separate memory device, and one or more memory regions may be masked so a self-refresh operation is not performed Claim 4 Kim (2019/0333570) teaches: The system of claim 3, wherein the memory controller comprises a plurality of first selection circuits, each of the plurality of first selection circuits corresponding to a respective memory area from the plurality of first memory areas, FIG. 3 and P. 0035 the refresh circuit 133 may include independent refresh circuits for each of the respective memory regions. Each refresh circuit controlling one of the memory regions. wherein the plurality of first selection circuits commonly receive the refresh command, and P. 0033 refresh circuit 133 may perform a refresh operation in response to a refresh command such as self-refresh wherein each of the plurality of first selection circuits is configured to generate an internal refresh command based on the refresh command and the allocation flag indicating whether a corresponding first memory area from among the plurality of first memory areas is allocated to the host, and P. 0035 control of the plurality of memory regions may be provided by one or more refresh circuits that each control one or more memory regions of the plurality of memory regions; P. 0052 when a refresh operation of the second memory region 220 is masked, only the memory bank Bank1 belonging to the first memory region 210 may be controlled to perform a refresh operation output the internal refresh command to the corresponding first memory area. P. 0059 when the second processor 30 is disabled and only the first processor 20 is enabled, a self-refresh is performed only on the first memory region 210 in the entire memory area of the common memory device 100a Claim 9 Lee (2025/0208780) teaches: An operating method of a system, the operating method comprising: generating allocation information between a plurality of hosts and a plurality of memory devices; FIG. 2 Controller 830; FIG. 8 Controller 430; FIG. 7 and P. 0090 the address range table in partition manager 332 within controller 330 may include ownership information indicating which host processor uses each of logical address ranges in pooled memory 310 providing, to a first memory device from among the plurality of memory devices, partial allocation information related to the first memory device from the allocation information, P. 0032 and FIG. 3 MRS circuit 131 on common memory device 100a may store refresh masking information regarding at least one memory region in response to the MRS setting command received from the memory controller 60 the first memory device comprising a plurality of memory areas; P. 0064 and FIG. 2 memory areas of the plurality of memory cards 850A, 850B, 850C, 850D in the pooled memory device 810 Lee does not explicitly teach sending allocation information to a memory device, and performing a refresh operation based on the allocation information. Kim (2019/0333570) teaches: performing, based on the partial allocation information indicating a memory area is allocated to at least one of the plurality of hosts from among the plurality of memory areas in the first memory device, a refresh operation on the memory area allocated to at least one of the plurality of hosts; and P. 0033 refresh circuit 133 may control a refresh to be selectively performed on a memory region according to the refresh masking information; P. 0047 MRS setting command may also include identification information regarding the processor that is associated with the memory region skipping, based on the partial allocation information, the refresh operation on a memory area not allocated to the plurality of hosts from among the plurality of memory areas in the first memory device, the refresh operation on the memory area not allocated the plurality of hosts. P. 0034 refresh circuit 133 will not perform a self-refresh on memory regions that are restricted based on the received masking information; P. 0058 self-refresh masking information may indicates self-refresh is performed on each of the first and second memory regions 210 and 220, and whether the first processor 20 and/or the second processor 30 is enabled It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Lee with sending allocation information to a memory device, and performing a refresh operation based on the allocation information taught by Kim. The motivation being power consumption of the memory device is reduced (see Kim P. 0059) The systems of Lee and Kim are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems. Therefore it would have been obvious to combine Lee with Kim to obtain the invention as recited in claims 9-15. Claim 10 Kim (2019/0333570) teaches: The operating method of claim 9, wherein the performing the refresh operation comprises providing a refresh command to at least one of the plurality of memory areas, based on an allocation flag indicating whether the plurality of memory areas has been allocated to at least one of the plurality of hosts. P. 0032 and FIG. 3 MRS circuit 131, within control circuit 130 of common memory device 100a, may store self-refresh masking information regarding at least one memory region; P. 0045 each of the processors 20 and 30 may use the corresponding memory region 210 or 220 as a separate memory device, and one or more memory regions may be masked so a self-refresh operation is not performed The rationale to combine Lee with Kim for claim 9 equally applies for dependent claim 10. Claim 11 Kim (2019/0333570) teaches: The operating method of claim 10, wherein the providing the refresh command to the plurality of memory areas comprises: generating an internal refresh command based on the refresh command and the allocation flag; and FIG. 3 and P. 0035 the refresh circuit 133 may include independent refresh circuits for each of the respective memory regions. Each refresh circuit controlling one of the memory regions; P. 0033 refresh circuit 133 may perform a refresh operation in response to a refresh command such as self-refresh providing the internal refresh command to a first memory area allocated to at least one of the plurality of hosts from among the plurality of memory areas. P. 0059 when the second processor 30 is disabled and only the first processor 20 is enabled, a self-refresh is performed only on the first memory region 210 in the entire memory area of the common memory device 100a Claim 16 Kim (2019/0333570) teaches: A system comprising: a plurality of hosts; FIG. 1 first and second processors 20, 30 […] memory device[s] configured to communicate with the plurality of hosts, […] memory device[s] comprising a plurality of memory areas; and P. 0077 the memory area of a memory device shared by at least two processors is partitioned into at least two memory regions a switch circuit configured to store mapping information about a memory area allocated to at least one of the plurality of hosts from among the plurality of memory areas […] P. 0049 memory controller 60 may store a mapping table that includes information regarding the independent memory mapping associated with each of the memory regions; P. 0032 and FIG. 3 memory controller 60 may send refresh masking information regarding at least one memory region wherein a first memory device […] is configured to receive at least a portion of the mapping information from the switch circuit, P. 0032 and FIG. 3 MRS circuit 131 on common memory device 100a may store refresh masking information regarding at least one memory region in response to the MRS setting command received from the memory controller 60 perform a refresh operation on a first memory area from a plurality of first memory areas in the first memory device based on the portion of the mapping information indicating that the first memory area is allocated to a host, and. P. 0033 refresh circuit 133 may control a refresh to be selectively performed on a memory region according to the refresh masking information; P. 0033 refresh circuit 133 may control a refresh to be selectively performed on a memory region according to the refresh masking information; P. 0047 MRS setting command may also include identification information regarding the processor that is associated with the memory region skip the refresh operation on a second memory area from the plurality of memory areas based on the portion of the mapping information indicating that the second memory area is not allocated to the host. P. 0034 refresh circuit 133 will perform the self-refresh on memory banks associated with at least one unmasked memory region, but will not perform a self-refresh on memory regions that are restricted based on the received masking information; P. 0058 self-refresh masking information may indicates self-refresh is performed on each of the first and second memory regions 210 and 220, and whether the first processor 20 and/or the second processor 30 is enabled Kim does not explicitly teach the system comprising a plurality of memory devices. Lee (2025/0208780) teaches: a plurality of hosts; FIG. 2 and P. 0060 hosts 102A and 102B are coupled to memory cards 850A-D a plurality of memory devices configured to communicate with the plurality of hosts, each of the plurality of memory devices comprising a plurality of memory areas; and P. 0064 and FIG. 2 memory areas of the plurality of memory cards 850A, 850B, 850C, 850D in the pooled memory device 810 a switch circuit configured to store mapping information about a memory area allocated to at least one of the plurality of hosts from among the plurality of memory areas in the plurality of memory devices, FIG. 2 Controller 830; FIG. 8 Controller 430; FIG. 7 and P. 0090 the address range table in partition manager 332 within controller 330 may include ownership information indicating which host processor uses each of logical address ranges in pooled memory 310 It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Kim with the plurality of memory devices taught by Lee. The motivation being to provide enormous persistent memory capacity and on-demand memory resources to resource-limited computing devices (see Lee P. 0064) The systems of Kim and Lee are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems. Therefore it would have been obvious to combine Kim with Lee to obtain the invention as recited in claims 16-20. Claim 18 Kim (2019/0333570) teaches: The system of claim 16, wherein the first memory device comprises a memory controller configured to provide a refresh command to the plurality of first memory areas, based on an allocation flag indicating whether the plurality of first memory areas have been allocated to at least one of the plurality of hosts. P. 0032 and FIG. 3 MRS circuit 131, within control circuit 130 of common memory device 100a, may store self-refresh masking information regarding at least one memory region; P. 0045 each of the processors 20 and 30 may use the corresponding memory region 210 or 220 as a separate memory device, and one or more memory regions may be masked so a self-refresh operation is not performed Claim 19 Kim (2019/0333570) teaches: The system of claim 18, wherein the memory controller comprises a plurality of first selection circuits, each of the plurality of first selection circuits corresponding to a respective memory area from the plurality of first memory areas, FIG. 3 and P. 0035 the refresh circuit 133 may include independent refresh circuits for each of the respective memory regions. Each refresh circuit controlling one of the memory regions. wherein the plurality of first selection circuits commonly receive the refresh command, and P. 0033 refresh circuit 133 may perform a refresh operation in response to a refresh command such as self-refresh wherein each of the plurality of first selection circuits is configured to generate an internal refresh command based on the refresh command and the allocation flag indicating whether a corresponding first memory area from among the plurality of first memory areas has been allocated to a host, and P. 0035 control of the plurality of memory regions may be provided by one or more refresh circuits that each control one or more memory regions of the plurality of memory regions; P. 0052 when a refresh operation of the second memory region 220 is masked, only the memory bank Bank1 belonging to the first memory region 210 may be controlled to perform a refresh operation output the internal refresh command to the corresponding first memory area. P. 0059 when the second processor 30 is disabled and only the first processor 20 is enabled, a self-refresh is performed only on the first memory region 210 in the entire memory area of the common memory device 100a Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (U.S. PGPub No. 2019/0333570) in view of Lee et al. (U.S. PGPub No. 2025/0208780) in view of Kang et al. (U.S. PGPub No. 2017/0047110). Claim 21 The systems of Kim and Lee do not explicitly teach performing a refresh operation on a memory area when a write operation has been performed on the memory area. Kang (2017/0047110) teaches: The system of claim 1, wherein the refresh operation is performed on the first memory area from the plurality of first memory areas based on determining a write operation is performed on the first memory area. P. 0006 A refresh operation of a memory area of a DRAM that is not used or in which data is not stored may be skipped It would have been obvious to a person with ordinary skill in the art before the effective filing date of the application to include the invention of Kim and Lee with performing a refresh operation on a memory area when a write operation has been performed on the memory area taught by Kang. The motivation being to reduce power consumption and/or increase performance (see Kang P. 0006) The systems of Kim, Lee and Kang are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems. Therefore it would have been obvious to combine Kim and Lee with Kang to obtain the invention as recited in claim 21. Allowable Subject Matter Claims 5-8, 12-15 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 5 recites the limitation “wherein each of the plurality of first selection circuits is further configured to generate the internal refresh command based on a write flag indicating whether a write operation has been performed in the corresponding first memory area, and output the internal refresh command to the corresponding first memory area” Said limitation is taught by the specification of the instant application as originally filed at least at [P. 0110, 0114-117 and FIG. 10C]. Said limitations, in combination with the other recited limitations of claim 5, are not taught or suggested by the prior art of record. The closest prior art of record includes: Kim (2019/0333570) which teaches a common memory device with a controller, the controller including a circuit storing refresh masking information regarding each region, the controller including refresh circuits for each memory region, the refresh circuits controlling self-refresh operations for each region, and only performing refresh operations on enabled memory regions; and Lee (2025/0208780) which teaches sending a command releasing memory areas/logical address ranges within the pooled memory devices, and an address ranger table including information tracking the ownership of the logical address ranges by the host processors. None of the references teach a plurality of first selection circuits within the memory controller of a memory device, each first selection circuit corresponding to a memory area of the memory device, generating an internal refresh command based on an allocation flag and a write flag corresponding to the memory area Claim 6 depends from claim 5, and is considered allowable for at least the same reasons as claim 5. Claim 20 contains similar limitations to claim 5, and is considered allowable for at least the same reasons as claim 5. Claim 7 recites the limitation “a plurality of second selection circuits each configured to generate a control signal controlling the refresh operation on a corresponding memory array, based on the internal refresh command and a write flag indicating whether a write operation has been performed on the corresponding memory array” Said limitation is taught by the specification of the instant application as originally filed at least at [P. 0110, 0114-117 and FIG. 10C]. Said limitations, in combination with the other recited limitations of claim 7, are not taught or suggested by the prior art of record. The closest prior art of record includes: Kim (2019/0333570) which teaches a common memory device with a controller, the controller including a circuit storing refresh masking information regarding each region, the controller including refresh circuits for each memory region, the refresh circuits controlling self-refresh operations for each region, and only performing refresh operations on enabled memory regions; and Lee (2025/0208780) which teaches sending a command releasing memory areas/logical address ranges within the pooled memory devices, and an address ranger table including information tracking the ownership of the logical address ranges by the host processors. None of the references teach a plurality of second selection circuits within the memory controller of a memory device, generating a control signal based on an internal refresh command generated by a first selection circuit within the memory controller and a write flag. Claim 8 depends from claim 7, and is considered allowable for at least the same reasons as claim 7. Claim 12 recites the limitation “wherein the generating the internal refresh command comprises generating the internal refresh command based on a write flag indicating whether a write operation has been performed on the plurality of memory areas” Said limitation is taught by the specification of the instant application as originally filed at least at [P. 0110, 0114-117 and FIG. 10C]. Said limitations, in combination with the other recited limitations of claim 12, are not taught or suggested by the prior art of record. The closest prior art of record includes: Kim (2019/0333570) which teaches a common memory device with a controller, the controller including a circuit storing refresh masking information regarding each region, the controller including refresh circuits for each memory region, the refresh circuits controlling self-refresh operations for each region, and only performing refresh operations on enabled memory regions; and Lee (2025/0208780) which teaches sending a command releasing memory areas/logical address ranges within the pooled memory devices, and an address ranger table including information tracking the ownership of the logical address ranges by the host processors. None of the references teach generating an internal refresh for a memory area command based on the allocation and writes flags corresponding to the memory area. Claim 13 depends from claim 12, and is considered allowable for at least the same reasons as claim 12. Claim 14 recites the limitation “generating a control signal controlling a refresh operation on a plurality of memory arrays, based on the internal refresh command and a write flag indicating whether a write operation has been performed on the plurality of memory arrays in the first memory area” Said limitation is taught by the specification of the instant application as originally filed at least at [P. 0110, 0114-117 and FIG. 10C]. Said limitations, in combination with the other recited limitations of claim 14, are not taught or suggested by the prior art of record. The closest prior art of record includes: Kim (2019/0333570) which teaches a common memory device with a controller, the controller including a circuit storing refresh masking information regarding each region, the controller including refresh circuits for each memory region, the refresh circuits controlling self-refresh operations for each region, and only performing refresh operations on enabled memory regions; and Lee (2025/0208780) which teaches sending a command releasing memory areas/logical address ranges within the pooled memory devices, and an address ranger table including information tracking the ownership of the logical address ranges by the host processors. None of the references teach a generating a control signal based on an internal refresh command generated based on an allocation flag, and a write flag. Claim 15 depends from claim 14, and is considered allowable for at least the same reasons as claim 14. Response to Arguments Applicant's arguments filed 7/15/2026 have been fully considered but they are not persuasive. The applicant argues that because Kim does not teach a host, Kim cannot teach a refresh operation that is performed or skipped based on mapping information indicating whether a memory area is allocated to a host. The applicant also argues that Kim fails to disclose a refresh operation is performed or skipped based on whether a processor is listed in the MRS setting command. The examiner notes the rejection is in view of Kim and Lee, and Lee teaches an address range table which includes ownership information indicating which logical address ranges are used by which of the hosts (e.g. hosts 102A-B of FIG. 2) in P. 0090. The address range table is analogous to the mapping table taught by Kim (P. 0049), and the mapping information in claim 1. A person of ordinary skill in the art would recognize the mapping table taught by Kim in combination with the address range table with ownership information taught by Lee teaches mapping information that identifies whether a memory area is allocated to a host. Additionally, Kim P. 0042 mentions first and second memory regions may be allocated to first and second processors, respectively. The first and second processors of Kim are analogous to first and second hosts of Kim. Kim P. 0058 further states “a host may set self-refresh masking information … according to whether either the first processor 20 and/or the second processor 30 is enabled … The received self-refresh masking information indicates whether a self-refresh is performed on each of the first and second memory regions 210 and 220 … The self-refresh masking information may be set in the mode register”. In other words, masking information for a region may be set based on whether the region is assigned to an enabled processor, and self-refresh is performed based on the masking information set in the mode register (i.e. by the MRS command). This, in combination with the ownership information taught by Lee, teaches performing refresh on a memory area based on mapping information indicating whether a memory area is allocated to a host. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Subbrao et al. (U.S. Patent No. 11281601) which teaches a plurality of hosts sharing access to a plurality of SSDs, each SSD including a plurality of NVMs, mapping each host to a storage device, and a controller for the plurality of sending FTL map updates to the FLT maps in each SSD controller. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHANIE WU whose telephone number is (571)272-0257. The examiner can normally be reached 1pm to 6pm, and 10pm to 1am Eastern time (10am to 3pm, and 7pm to 10pm Pacific time). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio Del Mar Perez-Velez can be reached at (571) 270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEPHANIE WU/Primary Examiner, Art Unit 2133