DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 09/06/2024, 12/11/2024, and 03/18/2026 were filed after the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1-20 are objected to because of the following informalities: The claims contain “or both” at the last line of the independent claims. It is not clear this is referring to, i.e., whether it is for both providing steps in the last limitations of the independent claims, or both the first display driver and second display driver. Also, the or is the alternative language, and it is unclear it is the alternative for the last three limitations (i.e., one of them is sufficient). Correction is required to avoid ambiguity. The following rejection is given at best understood by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Holland et al. (US. Patent App. Pub. No. 2015/0371607, “Holland” hereinafter).
As per claim 1, as shown in Fig. 1, Holland teaches an electronic device, comprising:
a display (display 120);
mode selection circuitry configured to provide a mode selection indication of a mode for the display, wherein the mode is selected from at least one of a first mode or a second mode (¶ [95]);
a first display pipeline (display pipe 116) configured to process first image data (¶ [41]);
a second display pipeline (display pipe 117) configured to process second image data (¶ [41]);
frame merge circuitry configured to selectively merge first processed image data of the first display pipeline with second processed image data of the second display pipeline (¶ [39], and ¶ [60]);
mode implementation circuitry configured to:
when the mode selection indication indicates the first mode:
cause the frame merge circuitry to merge the first processed image data and the second processed image data into a first merged image data output; and
provide the first merged image data output to a first display driver (further addressed below); or
when the mode selection indication indicates the second mode:
provide the first processed image data to the first display driver for presentation;
provide the second processed image data to a second display driver different than the first display driver; or both (see Claim Objection above. Fig. 7, ¶ [90], first display pipeline would be driving the left side of the video frame to the display and a second display pipeline would be driving the right side of the video frame to the display. See also Fig. 10, ¶ [97-98], selecting dual pipe mode for a split display using two controllers 1014 and 1016).
Holland does not explicitly teach when the mode selection indication indicates the first mode: cause the frame merge circuitry to merge the first processed image data and the second processed image data into a first merged image data output; and provide the first merged image data output to a first display driver. Holland does, however, teach, as shown in Fig. 7 and 10, a non-split display screen and a two-way split display screen, wherein the entire video frame being displayed on screen 702 using a single display pipeline (¶ [90]) using a single controller is driving the entire display (¶ [98]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the single controller taught by Holland above to a first display driver (different from the second display controller) so that in a first mode (non-split display mode), the entire frame is merged by the two display pipeline (addressed above, ¶ [39]) and sent to the single controller (first display controller) because this is implicitly taught by Holland as shown in Fig. 8, ¶ [91], where the output of processed images of both display pipelines are provided to the single controller.
As per claim 2, Holland further teaches the mode implementation circuitry comprises a multiplexer coupled to: a first input, comprising an output of the frame merge circuitry; and a second input, comprising an output of the first display pipeline (Fig. 10, ¶ [98], mux 1020 to select either dual pipe mode or single pipe mode with reference to Fig. 8 recited above in claim 1).
As per claim 3, as addressed in claims 1 and 2 above, Holland also impliedly teaches wherein the multiplexer is configured to: when the mode selection indication indicates the first mode, output the first merged image data output from the frame merge circuitry; and when the mode selection indication indicates the second mode, provide the output of the first display pipeline (¶ [98], “…mux 1020 may be configured to select dual pipe mode (for a split display) or single pipe mode when a single controller is driving the entire display”).
As per claim 4, Holland does also teach wherein the first display pipeline, the second display pipeline, or both comprise corresponding timing generators configured to synchronize outputs of the first display pipeline and the second display pipeline (¶ [100-101]).
As per claim 5, Holland does also implicitly teach the frame merge circuitry comprises rate match circuitry configured to align the first processed image data and the second processed image data to a clocking rate of the rate match circuitry (Fig. 8, ¶ [91-92], running the same clock rate. See also, ¶ [99]).
As per claim 6, as addressed in claims 3-5 above, Holland does impliedly teach the frame merge circuitry comprises data merge circuitry configured to receive input from the rate match circuitry and perform merging operations on the input from the rate match circuitry (addressed in claims 4-5); and an output of the data merge circuitry is provided as the first input coupled to the multiplexer (addressed in claim 3).
As per claim 7, Holland also teaches the merging operations comprise: video line merging (¶ [91], merging two half lines), display stream compression (DSC) slice merging, or both.
As per claim 8, Holland does teach wherein the mode implementation circuitry comprises a switch configured to:
when the mode selection indication indicates the first mode, selectively couple the first display pipeline or the second display pipeline to the frame merge circuitry (at best understood since this is opposite to claim 1, where “the frame merge circuitry to merge the first processed image data and the second processed image data into a first merged image data output”, and thus, the frame merge circuitry should be coupled to the first display pipeline and second display pipeline in the first mode); and
when the mode selection indication indicates the second mode, selectively couple the first display pipeline or the second display pipeline to a corresponding image data output (as addressed in claim 1, i.e., using single display pipeline, ¶ [90]).
As per claim 9, as addressed, Holland does implicitly teach the mode selection circuitry is configured to provide an indication of a particular merged image data output comprising either the first merged image data output or a second merged image data output of a second frame merge circuitry (at best understood by the examiner since it is unclear where this second merged image data is established and how it is distinguished from the first merged image data).
As per claim 10, Holland impliedly teaches wherein the mode implementation circuitry comprises a second multiplexer (such as multiplexer 1018, Fig. 10) coupled to:
a third input, comprising the second frame merge circuitry configured to merge the first processed image data and the second processed image data into the second merged image data output (at best understood since first, it is quite confusing these inputs are circuitry (i.e., frame merge circuitry and display pipeline), not data inputs into the multiplexer, and second, it is unclear the second merged image data is different from the first merged image data because it is merged from the same first processed data and second processed data. Thus, given the broadest reasonable interpretation, the second frame merge circuitry is interpreted one of the blending units 302 in each display pipeline shown in Fig. 3, referring ¶ [60]); and
a fourth input, comprising the second display pipeline (Fig. 10, ¶ [98], either of the display pipes for use in single pipe mode).
As per claim 11, because of the unclear features addressed in claims 9 and 10, Holland does impliedly teach when the mode selection indication indicates the first mode:
when the indication of the particular merged image data output indicates the first merged image data output, the multiplexer is configured to output the first merged image data output from the frame merge circuitry (see claims 1-3); and
when the indication of the particular merged image data output indicates the second merged image data output, the second multiplexer is configured to output the second merged image data output from the second frame merge circuitry (see claims 9-10).
As per claim 12, Holland further impliedly teaches a controller configured to select the particular merged image data output based upon relative proximities of the first merged image data output and the second merged image data output to a target portion of the display (¶ [100], “For example, in one embodiment, each display pipeline may be working on a given frame, and the configuration data (i.e., frame packet) for the next frame may be sent to the two display pipelines close in proximity to the frame boundary between the current frame and the next frame”.
Claim 13, which is similar in scope to claim 1 as addressed above, is thus rejected under the same rationale.
Claim 14, which is similar in scope to claim 9 as addressed above, is thus rejected under the same rationale.
Claim 15, which is similar in scope to claim 12 as addressed above, is thus rejected under the same rationale.
Claim 16, which is similar in scope to claim 8 as addressed above, is thus rejected under the same rationale.
Claim 17, which is similar in scope to claims 4 and 5 as addressed above, is thus rejected under the same rationale.
Claim 18, which is similar in scope to claim 1 as addressed above, is thus rejected under the same rationale.
Claim 19, which is similar in scope to claim 9 as addressed above, is thus rejected under the same rationale.
Claim 20, which is similar in scope to claim 12 as addressed above, is thus rejected under the same rationale.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hau H. Nguyen whose telephone number is: 571-272-7787. The examiner can normally be reached on MON-FRI from 8:30-5:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tammy Goddard, can be reached on (571) 272-7773.
The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAU H NGUYEN/Primary Examiner, Art Unit 2611