Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
1. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claim(s) 1-12, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al (Pub. No.: US 2019/0092038).
3. Regarding independent claim 1, Choi et al teaches a device (Fig. 1) comprising: first and second staircases (Fig. 35, stair case from first portion and second portion of the memory block Fig. 35) configured to access (Fig. 35, where WCTR and BL access the block Fig.35) a same block (Fig. 35) in a memory array (Fig. 1, Fig. 35), wherein the first staircase (Fig. 35, staircase in the first portion) descends in a first direction (Fig. 35, staircase descending from upper left corner to lower right corner), and the second staircase (Fig. 35, staircase in the second portion) descends in a second direction (Fig. 35, the staircase descending from upper right corner to lower left corner).
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4. Regarding claim 2, Choi et al teaches the second direction (Fig. 35, the staircase descending from upper right corner to lower left corner) is opposite (Fig. 35) to the first direction (Fig. 35, staircase descending from upper left corner to lower right corner).
5. Regarding claim 3, Choi et al teaches steps of the first and second staircases (Fig. 35, stair case from first portion and second portion of the memory block Fig. 35) correspond to tiers (Fig. 35, multiple tiers from first and second portions) of the memory array (Fig. 1, Fig. 35).
6. Regarding claim 4, Choi et al teaches the first and second staircases (Fig. 35, stair case from first portion and second portion of the memory block Fig. 35) are configured to access word lines (Fig. 35, WCTR ) of the memory array (Fig. 1, Fig. 35).
5. Regarding claim 5, Choi et al teaches each staircase (see Fig. 35) has steps provided by edges of conductive layers (see Fig. 35 edge of WCTR) used to access memory cells in the memory array (Fig. 1, Fig. 35).
6. Regarding independent claim 6, Choi teaches a device (Fig. 1, Fig. 35) comprising: a first staircase (Fig. 35, staircase in the first portion) located between (Fig. 35, where both staircases located between first and second portion of memory array in Fig. 35) first and second portions (Fig. 4, see figure above) of a memory array (Fig. 1, Fig. 35); a second staircase located between the first and second portions (Fig. 35, where both staircases located between first and second portion of memory array in Fig. 35) of the memory array (Fig. 1, Fig. 35); and conductive connectors connecting the first and second staircases(Fig. 35, stair case from first portion and second portion of the memory block Fig. 35).
7. Regarding claim 7, Choi teaches driver circuitry (Fig. 1, DCR, SAR, PPR) connected to each conductive connector (Fig. 35, GWL connected to DCR).
8. Regarding claim 8, Choi et al teaches the each conductive connector (Fig. 35, GWL connected to DCR) electrically connects opposite (see Fig. 1) portions of corresponding word lines (Fig. 35, WCTR).
9. Regarding claim 9, Choi et al teaches each conductive connector (Fig. 35, GWL connected to DCR) includes a vertical interconnect (Fig. 35, WPLG).
10. Regarding claim 10, Choi et al teaches the first and second staircases (See Fig. 35, stair case from B region as first and DST region as second staircase (Fig. 35, staircase in the second portion)) descend in opposite directions (see Fig. 35).
11. Regarding claim 11, Choi et al teaches the second staircase (Fig. 35, staircase in the second portion) is adjacent to the first staircase (Fig. 35, staircase in the first portion).
12. Regarding claim 12, Choi et al teaches a word line (Fig. 35, WCTR) ordering for the first portion is opposite from a word line (Fig. 35, WCTR) ordering for the second portion (See Fig. 35).
Claim Rejections - 35 USC § 103
13. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
14. Claim(s) 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al (Pub. No.: US 2019/0092038) in view of KIM et al (Pub. No.: US 2019/0139985).
15. Regarding independent claim 13, Choi et al teaches a device (Fig. 1) comprising: a first staircase (Fig. 35, staircase in the first portion) connected to a first portion (Fig. 35, see Figure above) of a block (Fig. 35) in a memory array (Fig. 1, Fig. 35); and a second staircase (Fig. 35, staircase in the second portion) connected to a second portion (Fig. 35, see figure above) of the block (Fig. 35) in the memory array (Fig. 1, Fig. 35).
Choi et al is silent with respect to wherein the first and second portions are located at different heights.
Kim et al teaches wherein the first and second portions (Fig. 6, Ps vs GE_f) are located at different heights (Fig. 6, where one portion is higher than the other portion)
It would have been obvious to one of ordinary skill in the art at the time of the invention to apply the teachings of Kim et al to the teaching of Choi et al such that higher level stair case would have more memory cells.
16. Regarding claim 14, Choi et al teaches the first and second staircases (Fig. 35, stair case from first portion and second portion of the memory block Fig. 35) electrically connect tiers (See Fig. 35) of the first and second portions to provide a plurality of word lines (Fig. 35, WCTR).
17. Regarding claim 15, Choi et al teaches each staircase (See Fig. 35) has contact configured to vertically contact landing pads (see Fig. 31) on the tiers (see Fig. 11A).
18. Regarding claim 16, Choi et al teaches the first and second staircases(Fig. 35, stair case from first portion and second portion of the memory block Fig. 35) descend in opposite directions (See Fig. 35).
19. Regarding claim 17, Choi et al teaches the first and second portions are on opposite sides (See Fig. 35) of the first and second staircases (Fig. 35, stair case from first portion and second portion of the memory block Fig. 35).
20. Regarding claim 18, Choi et al teaches the block is a first block (Fig. 35), the device further comprises a second block (see Fig. 30, there are separate blocks separate by #230) having third and fourth portions (see Fig. 30 and Fig. 35), and the first and second staircases(Fig. 35, stair case from first portion and second portion of the memory block Fig. 35) are connected to the third and fourth portions (see Fig. 30 and Fig. 35).
19. Regarding claim 19, Choi et al teaches the third portion is overlying the first portion, and the second portion is overlying the fourth portion (see Fig. 30, Fig. 35).
20. Regarding claim 20, Choi et al teaches first bitlines (Fig. 30, BL) located between the first and third portions (see Fig. 30 and Fig. 35), and second bitlines (Fig. 30, BL) located between the second and fourth portions (see Fig. 30, and Fig. 35).
Conclusion
21. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure, Tessariol et al (Pub. No: US 2017/0263556).
Tessariol et al (Pub. No: US 2017/0263556) shows staircases in the memory block.
22. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Han Yang whose telephone is (571) 270-3048. The examiner can normally be reached on Monday-Friday 8am-5pm with alternate Friday off. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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HY
09/19/2026
/HAN YANG/
Primary Examiner, Art Unit 2824
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