DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The IDS filed on 09/07/2024; 02/27/2025; and 01/28/2026 have been considered and made of record.
Oath/Declaration
The oath/declaration filed on 11/08/2024 is acceptable.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. [US 2016/0050744].
Regarding claim 1, Lee et al., disclose a semiconductor storage device (100, figures 1-10A-D) comprising:
a first board (110, figure 1B) including a first surface (110T, figure 1B) and a second surface (110B, figure 1B), the second surface being on a side opposite to the first surface (figure 1B);
a molded resin (140, figure 1B) covering the first surface when viewed in a thickness direction (a vertical direction, figure 1B) of the first board; and
a memory chip (120, figure 1B) between the first surface and the molded resin, wherein the first board includes a terminal (115S, 115G, 115G, figure 1B), the terminal being on the second surface, the terminal being exposed to the outside (115S, 115G, 115P, figure 1B), and the terminal includes a first non-planar portion (a bottom surface of the printed circuit board is not planar surface, figure 1B), the first non-planar portion includes at least one of a plurality of recesses (a plurality of recess to hold a plurality of conductive pads 115, figure 1B) and a plurality of protrusions (a plurality of 119b, figure 1B), the first non-planar portion includes a first recessed portion (at least one right recess to disposed a conductive pad 115S, figure 1B) and a first protruding portion (119b, figure 1B), and the first recessed portion and the first protruding portion are aligned alternately on the first non-planar portion (a bottom surface of the printed circuit board 110, figure 1B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., in view of ISHIMURA [WO 2023026510].
Regarding claim 2, Lee et al., disclose the claimed invention except for wherein the semiconductor storage device is detachably attachable to a socket connector on a second board of a host device.
ISHIMURA discloses a semiconductor memory device (10, figures 1-15) is detachably attachable to a socket connector (50, figures 3-5) on a second board (40, figures 3-5) of a host device (figures 3-5).
It would have been to one of ordinary skill in the art at the time the invention was made to use a semiconductor device of Lee et al., with a socket connector of a host computer, as suggested by ISHIMURA, for the purpose of enabling rapid read/write access to data and applications in a host computer.
Regarding claim 3, Lee et al., disclose the claimed invention except for wherein the semiconductor storage device is detachably attachable to the connector in a state in which a contact pin of the connector is in contact with the terminal.
ISHIMURA further discloses wherein the semiconductor storage device is detachably attachable to the connector in a state in which a contact pin (51/52/53/54, figures 3-5) of the connector is in contact with the terminal (P1/P2/P3/P4, figures 3-5).
It would have been to one of ordinary skill in the art at the time the invention was made to use a plurality of pins disposed within a socket connector of a host computer of ISHIMURA, and wherein the plurality of pins are contacted to their corresponding terminals of a semiconductor memory device of Lee et al., in order to provide electrical connections between a semiconductor memory device and a host computer’s socket connector.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al.
Regarding claim 17, Lee et al., disclose wherein the first board (110, figure 1B) includes a surface layer portion (119b, figure 1B), the surface layer portion is a surface layer portion forming the second surface (110B, figure 1B), the surface layer portion includes a conductive pattern including the terminal (115S, 115G, 115G, figure 1B), the surface layer portion includes an insulating layer covering a part of the conductive pattern, and the terminal includes a first non-planar portion (a bottom surface of the printed circuit board is not planar surface, figure 1B), the first non-planar portion includes a first recessed portion (at least one right recess to disposed a conductive pad 115S, figure 1B) and a first protruding portion (119b, figure 1B), and the first recessed portion and the first protruding portion are aligned alternately on the first non-planar portion (a bottom surface of the printed circuit board 110, figure 1B).
Lee et al., disclose the claimed invention except for the surface layer portion includes a third non-planar portion in a region outside the terminal, the third non-planar portion includes at least one of a plurality of recesses and a plurality of protrusions, the third non-planar portion includes a third recessed portion and a third protruding portion, and the third recessed portion and the third protruding portion are aligned alternately on the third non-planar portion.
It would have been to one of ordinary skill in the art at the time the invention was made to set a first non-planar portion in a region outside the terminal of a semiconductor memory device of Lee et al., in order to provide additional terminal contacts on the semiconductor memory device for increased density and/or enhanced input/output capabilities, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co. 193 USPQ 8.
Allowable Subject Matter
Claims 4-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The claim 4 discloses the combination features of “wherein the contact pin includes a curved portion, the curved portion is at a distal end part of the contact pin and is curved toward a side opposite to the terminal, the terminal includes a first region and a second region, when viewed in a thickness direction of the first board, the first region has at least a part overlapping the curved portion the second region is outside the first region, and the first non-planar portion is at least in the second region.” These features, in conjunction with other features, as claimed in the combination features of the claims 3, 2 and 1, were neither found to be disclosed, nor suggested by the prior art of records. Claims 5-16 depend on the allowed claim 4.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
SATO [US 2023/0091779] discloses memory card and memory system.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hung S. Bui whose telephone number is (571)272-2102. The examiner can normally be reached on M-F: 8am-5pm.
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/HUNG S. BUI/
Primary Examiner
Art Unit 2841
/Hung S. Bui/
Primary Examiner, Art Unit 2841
02/04/2026