DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
00. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
00. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
00. Claims 15-16, 20-21, 23 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US Patent Application Publication No. 2018/0240399 A1) in view of Ma et al. (US Patent Application Publication No. 2022/0214855 A1).
00. Regarding Claim 15, Lin discloses A method of controlling a display panel (paragraph [0073] reciting “The driving apparatus 500 descripted in FIG. 5 and FIG. 7 may be used for driving a display panel in which a gate scan …” Driving a display panel corresponds to a method of controlling a display panel.) for a display driver circuit, (paragraph [0032] reciting “FIG. 5 is a circuit block diagram of a driving apparatus according to an embodiment of the present invention.” Driving apparatus in FIG. 5 corresponds to display driver circuit.) the display driver circuit having a frame buffer, (see FIG. 5 wherein the display driver circuit has RAM which corresponds to frame buffer.) and the method comprising: receiving a first frame of display data and writing the first frame of display data into the frame buffer; (paragraph [0061] reciting “… According to the MIPI related specification, a still image (as host data) may be transmitted from the host device via the frame memory 540 to the timing control circuit 510 and to the digital control circuit (where the compensation circuit 520 is included) in a command mode, and a video stream (as host data) may be transmitted from the host device to the timing control circuit 510 and to the digital control circuit via the frame memory 540 or bypass the frame memory 540 in a video mode, which are called a video mode via RAM and a video mode bypass RAM respectively.”
Still image is a first frame of the still and video stream data, which together correspond to the display data. The still image is stored into frame memory 540 before being sent to display for rendering.) receiving a second frame of display data which is not in response to a control signal of the display driver circuit after receiving the first frame of display data; (paragraph [0061] reciting “… According to the MIPI related specification, a still image (as host data) may be transmitted from the host device via the frame memory 540 to the timing control circuit 510 and to the digital control circuit (where the compensation circuit 520 is included) in a command mode, and a video stream (as host data) may be transmitted from the host device to the timing control circuit 510 and to the digital control circuit via the frame memory 540 or bypass the frame memory 540 in a video mode, which are called a video mode via RAM and a video mode bypass RAM respectively.”
The video stream can be received after the still image. This video stream is not received in response to control signal of the display driver since it is not mentioned as such.) and outputting the second frame of display data to the display panel by bypassing the frame buffer. (see FIG. 5; paragraph [0061] reciting “… According to the MIPI related specification, a still image (as host data) may be transmitted from the host device via the frame memory 540 to the timing control circuit 510 and to the digital control circuit (where the compensation circuit 520 is included) in a command mode, and a video stream (as host data) may be transmitted from the host device to the timing control circuit 510 and to the digital control circuit via the frame memory 540 or bypass the frame memory 540 in a video mode, which are called a video mode via RAM and a video mode bypass RAM respectively.” The video stream bypasses the frame memory 540 and is outputted into the OLED Pixel array for display.)
While not explicitly disclosed by Lin, Ma discloses a second frame (paragraph [0115] reciting “… During analysis data selection, consecutive video stream frames may be selected. To prevent the obtained video stream frames from being excessively similar, it may be set that one frame is taken at a predetermined time interval …” A second frame is just one of consecutive frames of the video stream)
the second frame (paragraph [0115] reciting “… During analysis data selection, consecutive video stream frames may be selected. To prevent the obtained video stream frames from being excessively similar, it may be set that one frame is taken at a predetermined time interval …” A second frame is just one of consecutive frames of the video stream)
It would have been obvious to a person of ordinary skills in the art before the effective filing date of the claimed invention to modify Lin with Ma so that video stream comprises consecutive frames which are delivered into the OLED pixel array of Lin for display while bypassing the frame memory. This is an obviously beneficial modification since Lin discloses a video stream and Ma discloses that a video stream is series of consecutive frames which allows for each frame to be sent to the OLED pixel array.
00. Regarding Claim 16, Lin further discloses The method of claim 15, wherein the second frame of display data is different from the first frame of display data. (see FIG. 5; paragraph [0061] reciting “… According to the MIPI related specification, a still image (as host data) may be transmitted from the host device via the frame memory 540 to the timing control circuit 510 and to the digital control circuit (where the compensation circuit 520 is included) in a command mode, and a video stream (as host data) may be transmitted from the host device to the timing control circuit 510 and to the digital control circuit via the frame memory 540 or bypass the frame memory 540 in a video mode, which are called a video mode via RAM and a video mode bypass RAM respectively.” Video stream frames are different from still image frames.)
00. Regarding Claim 20, Lin further discloses The method of claim 15, wherein the display driver circuit is operated in a first operation mode, and the method further comprises: leaving the first operation mode to enter a second operation mode when receiving the second frame of display data. (paragraph [0061] reciting “
For data transfer from a host device, such as an application processor used in a mobile device as the OLED display device which includes the driving apparatus 500, a high speed serial data interface such as a mobile industry processor interface (MIPI) may be used to communicate with the driving apparatus 500. A frame memory 540 such as a random access memory (RAM) is installed in the driving apparatus 500. According to the MIPI related specification, a still image (as host data) may be transmitted from the host device via the frame memory 540 to the timing control circuit 510 and to the digital control circuit (where the compensation circuit 520 is included) in a command mode, and a video stream (as host data) may be transmitted from the host device to the timing control circuit 510 and to the digital control circuit via the frame memory 540 or bypass the frame memory 540 in a video mode, which are called a video mode via RAM and a video mode bypass RAM respectively.” A still image is transmitted from host to digital control circuit in command mode whereas video stream is transmitted from hos to digital control circuit in video mode. Command mode and video mode are a first operation mode and second operation mode.)
00. Regarding Claim 21, Lin further discloses The method of claim 20, further comprising: refreshing the display panel by reading out the first frame of display data from the frame buffer when the display driver circuit is in the first operation mode. (see FIG. 5 where the still image is fed onto the OLED pixel array and displayed onto the OLED display panel, which refreshes the OLED display panel with the still image from OLED pixel array.)
00. Regarding Claim 23, Lin further discloses The method of claim 20, further comprising: controlling a plurality of display data received by the display driver circuit to bypass the frame buffer when the display driver circuit is in the second operation mode. (paragraph [0061] reciting “For data transfer from a host device, such as an application processor used in a mobile device as the OLED display device which includes the driving apparatus 500, a high speed serial data interface such as a mobile industry processor interface (MIPI) may be used to communicate with the driving apparatus 500. A frame memory 540 such as a random access memory (RAM) is installed in the driving apparatus 500. According to the MIPI related specification, a still image (as host data) may be transmitted from the host device via the frame memory 540 to the timing control circuit 510 and to the digital control circuit (where the compensation circuit 520 is included) in a command mode, and a video stream (as host data) may be transmitted from the host device to the timing control circuit 510 and to the digital control circuit via the frame memory 540 or bypass the frame memory 540 in a video mode, which are called a video mode via RAM and a video mode bypass RAM respectively.” In video mode, the accepted frames bypass memory.)00. Regarding Claim 26, Lin discloses A display driver circuit (paragraph [0032] reciting “FIG. 5 is a circuit block diagram of a driving apparatus according to an embodiment of the present invention.” Driving apparatus in FIG. 5 corresponds to display driver circuit.) for controlling a display panel, (paragraph [0073] reciting “The driving apparatus 500 descripted in FIG. 5 and FIG. 7 may be used for driving a display panel in which a gate scan …” Driving a display panel corresponds to a method of controlling a display panel.) the display driver circuit having a frame buffer and being to: (see FIG. 5 wherein the display driver circuit has RAM which corresponds to frame buffer.)
receive a first frame of display data and write the first frame of display data into the frame buffer; (paragraph [0061] reciting “… According to the MIPI related specification, a still image (as host data) may be transmitted from the host device via the frame memory 540 to the timing control circuit 510 and to the digital control circuit (where the compensation circuit 520 is included) in a command mode, and a video stream (as host data) may be transmitted from the host device to the timing control circuit 510 and to the digital control circuit via the frame memory 540 or bypass the frame memory 540 in a video mode, which are called a video mode via RAM and a video mode bypass RAM respectively.”
Still image is written into frame buffer 540.)
receive a second frame of display data which is not in response to a control signal of the display driver circuit after receiving the first frame of display data; (paragraph [0061] reciting “… According to the MIPI related specification, a still image (as host data) may be transmitted from the host device via the frame memory 540 to the timing control circuit 510 and to the digital control circuit (where the compensation circuit 520 is included) in a command mode, and a video stream (as host data) may be transmitted from the host device to the timing control circuit 510 and to the digital control circuit via the frame memory 540 or bypass the frame memory 540 in a video mode, which are called a video mode via RAM and a video mode bypass RAM respectively.”
The video stream can be received after the still image. This video stream is not received in response to control signal of the display driver since it is not mentioned as such.)
and output the second frame of display data to the display panel by bypassing the frame buffer. (see FIG. 5; paragraph [0061] reciting “… According to the MIPI related specification, a still image (as host data) may be transmitted from the host device via the frame memory 540 to the timing control circuit 510 and to the digital control circuit (where the compensation circuit 520 is included) in a command mode, and a video stream (as host data) may be transmitted from the host device to the timing control circuit 510 and to the digital control circuit via the frame memory 540 or bypass the frame memory 540 in a video mode, which are called a video mode via RAM and a video mode bypass RAM respectively.” The video stream bypasses the frame memory 540 and is outputted into the OLED Pixel array for display.)
While not explicitly disclosed by Lin, Ma discloses a second frame (paragraph [0115] reciting “… During analysis data selection, consecutive video stream frames may be selected. To prevent the obtained video stream frames from being excessively similar, it may be set that one frame is taken at a predetermined time interval …” A second frame is just one of consecutive frames of the video stream)
the second frame (paragraph [0115] reciting “… During analysis data selection, consecutive video stream frames may be selected. To prevent the obtained video stream frames from being excessively similar, it may be set that one frame is taken at a predetermined time interval …” A second frame is just one of consecutive frames of the video stream)
It would have been obvious to a person of ordinary skills in the art before the effective filing date of the claimed invention to modify Lin with Ma so that video stream comprises consecutive frames which are delivered into the OLED pixel array of Lin for display while bypassing the frame memory. This is an obviously beneficial modification since Lin discloses a video stream and Ma discloses that a video stream is series of consecutive frames which allows for each frame to be sent to the OLED pixel array.
00. Claims 27-30 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Kohji Yamada (US Patent Application Publication No. 2021/0306660 A1).
00. Regarding Claim 27, Lin discloses A method of controlling a display panel (paragraph [0073] reciting “The driving apparatus 500 descripted in FIG. 5 and FIG. 7 may be used for driving a display panel in which a gate scan …” Driving a display panel corresponds to a method of controlling a display panel.) for a display driver circuit, (paragraph [0032] reciting “FIG. 5 is a circuit block diagram of a driving apparatus according to an embodiment of the present invention.” Driving apparatus in FIG. 5 corresponds to display driver circuit.) the display driver circuit having a frame buffer, (see FIG. 5 wherein the display driver circuit has RAM which corresponds to frame buffer.) and the method comprising:
receiving a plurality of display data; (paragraph [0061] reciting “… According to the MIPI related specification, a still image (as host data) may be transmitted from the host device via the frame memory 540 to the timing control circuit 510 and to the digital control circuit (where the compensation circuit 520 is included) in a command mode, and a video stream (as host data) may be transmitted from the host device to the timing control circuit 510 and to the digital control circuit via the frame memory 540 or bypass the frame memory 540 in a video mode, which are called a video mode via RAM and a video mode bypass RAM respectively.” Both the still image and the video stream corresponds to a plurality of display data that is transmitted from a host device. There can be multiple still images and/or video streams that all correspond to a plurality of display data.)
and writing the plurality of display data into the frame buffer or outputting the plurality of display data to the display panel by bypassing the frame buffer (paragraph [0061] reciting “For data transfer from a host device, such as an application processor used in a mobile device as the OLED display device which includes the driving apparatus 500, a high speed serial data interface such as a mobile industry processor interface (MIPI) may be used to communicate with the driving apparatus 500. A frame memory 540 such as a random access memory (RAM) is installed in the driving apparatus 500. According to the MIPI related specification, a still image (as host data) may be transmitted from the host device via the frame memory 540 to the timing control circuit 510 and to the digital control circuit (where the compensation circuit 520 is included) in a command mode, and a video stream (as host data) may be transmitted from the host device to the timing control circuit 510 and to the digital control circuit via the frame memory 540 or bypass the frame memory 540 in a video mode, which are called a video mode via RAM and a video mode bypass RAM respectively.” Still images are written into a frame memory 540 before being sent to the digital control circuit. Video stream images can be sent to digital control circuit, bypassing the frame memory 540.)
While not explicitly disclosed by Lin, Yamada discloses determining a frequency of the plurality of display data; (paragraph [0085] reciting “A region determination unit 812 determines whether the update frequency determined by the update frequency determination unit 811 is equal to or higher than a predetermined threshold for each of the divided regions. The region determination unit 812 determines that a region is the video region when the update frequency for the region is equal to or higher than the predetermined threshold, and determines that a region is the still-image region when the update frequency for the region is lower than the predetermined threshold.” A still image or video stream is determined based on frequency higher or lower than a threshold.)
according to the frequency. (paragraph [0085] reciting “A region determination unit 812 determines whether the update frequency determined by the update frequency determination unit 811 is equal to or higher than a predetermined threshold for each of the divided regions. The region determination unit 812 determines that a region is the video region when the update frequency for the region is equal to or higher than the predetermined threshold, and determines that a region is the still-image region when the update frequency for the region is lower than the predetermined threshold.”
A still image or video stream is determined based on frequency higher or lower than a threshold. Therefore, in Lin, the still image or video stream can be detected based on detected frequency.)
It would have been obvious to a person of ordinary skills in the art before the effective filing date of the claimed invention to modify Lin with Yamada so that the still image and video stream can be detected based on frequency determination. This is an obviously beneficial modification since Yamada discloses determining still image or video stream based on threshold and Lin allows video stream to bypass the frame memory while the still image is sent to frame memory.
00. Regarding Claim 28, the limitation The method of claim 27, wherein the step of writing the plurality of display data into the frame buffer or outputting the plurality of display data to the display panel by bypassing the frame buffer according to the frequency comprises: writing the plurality of display data into the frame buffer when the frequency is lower than a first threshold is obvious in view of Lin modified by Yamada. Lin discloses putting still images into a frame memory before sending those still images off for display. Lin discloses allowing video stream to bypass the frame memory and be directly fed into digital control circuit. Yamada discloses that still images and video streams are differentiated based on frequency with still images being lower than a frequency. Thus that frequency is the first predetermined threshold. Therefore, Lin modified by Yamada can detect frequency to determine that still images are being received when the frequency falls below a first predetermined threshold.
00. Regarding Claim 29, the limitation The method of claim 27, wherein the step of writing the plurality of display data into the frame buffer or outputting the plurality of display data to the display panel by bypassing the frame buffer according to the frequency comprises: outputting the plurality of display data to the display panel by bypassing the frame buffer when the frequency is higher than a second threshold is obvious in view of Lin modified by Yamada. Lin discloses putting still images into a frame memory before sending those still images off for display. Lin discloses allowing video stream to bypass the frame memory and be directly fed into digital control circuit. Yamada discloses that still images and video streams are differentiated based on frequency with video streams having frequency equal to or above a threshold. Therefore, the next available value immediately below that threshold is a second predetermined threshold. Therefore, Lin modified by Yamada can detect frequency to determine that video stream is being received when the detected frequency is above a threshold.
00. Regarding Claim 30, Lin discloses A display driver circuit (paragraph [0032] reciting “FIG. 5 is a circuit block diagram of a driving apparatus according to an embodiment of the present invention.” Driving apparatus in FIG. 5 corresponds to display driver circuit.) for controlling a display panel, (paragraph [0073] reciting “The driving apparatus 500 descripted in FIG. 5 and FIG. 7 may be used for driving a display panel in which a gate scan …” Driving a display panel corresponds to a method of controlling a display panel.) the display driver circuit having a frame buffer and being to: (see FIG. 5 wherein the display driver circuit has RAM which corresponds to frame buffer.)
receive a plurality of display data; (paragraph [0061] reciting “… According to the MIPI related specification, a still image (as host data) may be transmitted from the host device via the frame memory 540 to the timing control circuit 510 and to the digital control circuit (where the compensation circuit 520 is included) in a command mode, and a video stream (as host data) may be transmitted from the host device to the timing control circuit 510 and to the digital control circuit via the frame memory 540 or bypass the frame memory 540 in a video mode, which are called a video mode via RAM and a video mode bypass RAM respectively.” Both the still image and the video stream corresponds to a plurality of display data that is transmitted from a host device. There can be multiple still images and/or video streams that all correspond to a plurality of display data.)
and write the plurality of display data into the frame buffer or output the plurality of display data to the display panel by bypassing the frame buffer (paragraph [0061] reciting “For data transfer from a host device, such as an application processor used in a mobile device as the OLED display device which includes the driving apparatus 500, a high speed serial data interface such as a mobile industry processor interface (MIPI) may be used to communicate with the driving apparatus 500. A frame memory 540 such as a random access memory (RAM) is installed in the driving apparatus 500. According to the MIPI related specification, a still image (as host data) may be transmitted from the host device via the frame memory 540 to the timing control circuit 510 and to the digital control circuit (where the compensation circuit 520 is included) in a command mode, and a video stream (as host data) may be transmitted from the host device to the timing control circuit 510 and to the digital control circuit via the frame memory 540 or bypass the frame memory 540 in a video mode, which are called a video mode via RAM and a video mode bypass RAM respectively.” Still images are written into a frame memory 540 before being sent to the digital control circuit. Video stream images can be sent to digital control circuit, bypassing the frame memory 540.)
While not explicitly disclosed by Lin, Yamada discloses determine a frequency of the plurality of display data; (paragraph [0085] reciting “A region determination unit 812 determines whether the update frequency determined by the update frequency determination unit 811 is equal to or higher than a predetermined threshold for each of the divided regions. The region determination unit 812 determines that a region is the video region when the update frequency for the region is equal to or higher than the predetermined threshold, and determines that a region is the still-image region when the update frequency for the region is lower than the predetermined threshold.” A still image or video stream is determined based on frequency higher or lower than a threshold.)
according to the frequency. (paragraph [0085] reciting “A region determination unit 812 determines whether the update frequency determined by the update frequency determination unit 811 is equal to or higher than a predetermined threshold for each of the divided regions. The region determination unit 812 determines that a region is the video region when the update frequency for the region is equal to or higher than the predetermined threshold, and determines that a region is the still-image region when the update frequency for the region is lower than the predetermined threshold.”
A still image or video stream is determined based on frequency higher or lower than a threshold. Therefore, in Lin, the still image or video stream can be detected based on detected frequency.)
It would have been obvious to a person of ordinary skills in the art before the effective filing date of the claimed invention to modify Lin with Yamada so that the still image and video stream can be detected based on frequency determination. This is an obviously beneficial modification since Yamada discloses determining still image or video stream based on threshold and Lin allows video stream to bypass the frame memory while the still image is sent to frame memory.
00. Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Ma and further in view of Yamada.
00. Regarding Claim 24, while the combination of Lin and Ma does not explicitly disclose, Yamada discloses The method of claim 23, wherein the plurality of display data are received with a frequency greater than a predetermined threshold. (paragraph [0085] reciting “A region determination unit 812 determines whether the update frequency determined by the update frequency determination unit 811 is equal to or higher than a predetermined threshold for each of the divided regions. The region determination unit 812 determines that a region is the video region when the update frequency for the region is equal to or higher than the predetermined threshold, and determines that a region is the still-image region when the update frequency for the region is lower than the predetermined threshold.”
A still image or video stream is determined based on frequency higher or lower than a threshold. Therefore, in Lin, the still image or video stream can be detected based on detected frequency.)
It would have been obvious to a person of ordinary skills in the art before the effective filing date of the claimed invention to modify Lin and Ma with Yamada so that the still image and video stream can be detected based on frequency determination. This is an obviously beneficial modification since Yamada discloses determining still image or video stream based on threshold and Lin allows video stream to bypass the frame memory while the still image is sent to frame memory.
Allowable Subject Matter
00. Claims 1-14 are allowed.
00. The following is an examiner’s statement of reasons for allowance: Claim 1 recites the limitation starting counting time in a time period for receiving the first frame of display data, to determine whether a timeout occurs; receiving a second frame of display data after the timeout occurs; and writing the second frame of display data into the frame buffer which is neither disclosed nor suggested by the cited references, either singly or in combination.
00. Claim 14 recites the limitation start counting time in a time period for receiving the first frame of display data, to determine whether a timeout occurs; receive a second frame of display data after the timeout occurs; and write the second frame of display data into the frame buffer which is neither disclosed nor suggested by the cited references, either singly or in combination.
00. A close art is Han et al. (US Patent Application Publication No. 2021/0065652 A1). Han at FIG. 2 discloses PATH1 and PATH2. PATH1 uses the frame buffer while PATH2 bypasses the frame buffer. The video mode bypasses the frame buffer while the virtual control model passes through the frame buffer. However, nothing in Han discloses start counting time in a time period for receiving the first frame of display data, to determine whether a timeout occurs; receive a second frame of display data after the timeout occurs; and write the second frame of display data into the frame buffer. The video mode or virtual control mode are not determined by a timeout from counting time. Furthermore, Han at paragraph [0043] recites “According to some example embodiment of the present disclosure, the processor 101 may determine whether or not the image data to be transmitted to the display driver IC 200 is still image data or video image data, and may set a display mode to a virtual control (VC) mode or a video mode depending on the determination result. The still image data may be, for example, an AoD image, but is not limited thereto.” This means that Han teaches allowing a processor to determined which display mode it is and Han does not utilize a timeout or counting time to determine if the an incoming display frame bypasses or passes the frame memory.
00. Another close art is Lee et al. (US Patent Application Publication No. 2025/0225955 A1). Lee, at least in paragraph [0068], discloses a control command to bypass or to refrain from storing an image in the memory 130. However, Lee, like Han, fails to disclose start counting time in a time period for receiving the first frame of display data, to determine whether a timeout occurs; receive a second frame of display data after the timeout occurs; and write the second frame of display data into the frame buffer. While Lee discloses a time interval this is not the same as timeout from counting. The time interval is used for refresh rate and the image and is irrelevant to determining whether image is placed into or bypasses the framebuffer. The processor provides a control command that determined whether to bypass/refrain from storing image into the framebuffer and control command is not based on timeout or counting time.
00. Claims 17-19, 22 and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
00. The following is a statement of reasons for the indication of allowable subject matter: Claim 17 recites the limitation starting counting time in a time period for receiving the first frame of display data to determine a timeout which is neither disclosed nor suggested by the cited references, either singly or in combination.
00. Claims 18-19 depend from claim 17.
00. Claim 22 recites the limitation The method of claim 21, wherein the first frame of display data is read out from the frame buffer with sequentially down-converted frequencies which is neither disclosed nor suggested by the cited references, either singly or in combination.
00. Claim 25 recites the limitation leaving the first operation mode to enter the second operation mode without being instructed by a command or an indication received from a host processor which is neither disclosed nor suggested by the cited references, either singly or in combination. Han explicitly teaches away from this by stating that a command mode or video mode is received from the host device.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Pertinent references not relied upon
00. Turnock et al. (US Patent Application Publication No. 2016/0077842 A1) is concerned with reading data from framebuffer and bypassing GOP interface and relying in VGA hardware rasteriser to render pixels.
00. Wyman et al. (US Patent Application Publication No. 2021/0134019 A1) is concerned with video stream from a Blu-ray player and bypassing the decoder. The decoder buffers still images into memory.
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/FRANK S CHEN/Primary Examiner, Art Unit 2611
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