DETAILED ACTION
Claims 1-2, 4-12 and 14-20 are present for examination.
Claims 1, 4-11, 14-20 have been amended.
Claims 3 and 13 have been cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5-6 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over MacDonald (US5,913,224) in view of Harada et al. (US8,266,385) and in further view of Crawford et al. (US 6,542,966).
With respect claim 1, MacDonald teaches checking, by the cache controller, if a cache miss occurs (see column 10, lines 23-25; indicating the existence of a cache miss on line 263 to replacement logic 287);
checking, by an address detector, if the memory access instruction conforms to predetermined conditions only after the cache miss occurs (see column 7, lines 17-18; processor initiates a read request. Also in column 10, lines 23-31; Comparator 260 compares the address to tags from tag logic 255 and indicates the existence of a cache miss on line 263 to replacement logic 287. Comparator 285 consequently compares the address from processor interface 250 to the range of real-time addressed specified by registers 265 and determines that the address from processor interface 250 falls within the range of real-time addresses. Comparator 285 provides a signal on line 288 to replacement logic 287 indicating that the new address pertains to real-time code (i.e., address of the request received is compared to determine if it corresponds to a condition (i.e., falls within the range of real-time addresses) after a cache miss is detected);
transmitting, by the address detector, a signal to inform a replacement mask logic unit if the memory access instruction conforms to the predetermined conditions (see column 10, lines 23-31; comparator 285 consequently compares the address from processor interface 250 to the range of real-time addressed specified by registers 265 and determines that the address from processor interface 250 falls within the range of real-time addresses. Comparator 285 provides a signal on line 288 to replacement logic 287 indicating that the new address pertains to real-time code (i.e., address of the request received is compared to determine if it corresponds to a condition (i.e., a signal is sent to replacement logic of requested address falls within the range of real-time addresses)); and
providing, by the replacement mask logic unit, predetermined data to store the predetermined data into the cache memory (see column 10, lines 7-10, 31-35 and 51-55; replacement logic 287 stores the data corresponding to the address from processor interface 250 in either data way).
MacDonald does not teach providing, by the replacement mask logic unit, predetermined data to store the predetermined data into the cache memory without reading a main memory.
However, Harada et al. teaches wherein if a cache miss occurs in a write, it is preferable that write data be written to the cache memory 210 without reading data from the main memory 200 to the cache memory 210 (see column 6, lines 66-67 and column 7, lines 1-6).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by MacDonald to include the above mentioned to decrease access to the main memory (see Harada, column 7, lines 1-6).
MacDonald and Harada et al. do not teach wherein the memory access instruction is used to perform a store operation.
However, Crawford et al. teaches wherein data targeted by the cache access is specified by an address that can be associated with a cache entry (see column 4, lines 51-56).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by MacDonald and Harada et al. to include the above mentioned to ensure the performance of the device (see Crawford, column 4, lines 39-44).
With respect claim 5, MacDonald and Harada et al. do not teach wherein the predetermined conditions comprise that the store operation covers a region comprising at least a cache line.
However, Crawford et al. teaches wherein when the cache miss is triggered by a store instruction, the line of cache data is updated with target data indicated by the store instruction before it is written to the cache entry (see column 7, lines 5-12).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by MacDonald and Harada et al. to include the above mentioned to ensure the performance of the device (see Crawford, column 4, lines 39-44).
With respect claim 6, MacDonald and Harada et al. do not teach wherein the predetermined conditions comprise that the memory access instruction is corresponding to a store operation in a fixed direction.
However, Crawford et al. teaches wherein data targeted by the cache access is specified by an address that can be associated with a cache entry (see column 4, lines 51-56)… In ACCESS state 640, the cache entry to be accessed is identified through the targeted data's address, and the target data is either read from or written to the entry according to whether the access was triggered by a load or store (see column 7, lines 32-37).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by MacDonald and Harada et al. to include the above mentioned to ensure the performance of the device (see Crawford, column 4, lines 39-44).
With respect claim 10, MacDonald teaches wherein the memory access instruction is corresponding to a predetermined memory range (see column 10, lines 23-31; comparator 285 consequently compares the address from processor interface 250 to the range of real-time addressed specified by registers 265 and determines that the address from processor interface 250 falls within the range of real-time addresses. Comparator 285 provides a signal on line 288 to replacement logic 287 indicating that the new address pertains to real-time code (i.e., address of the request received is compared to determine if it corresponds to a condition (i.e., requested address falls within the range of real-time addresses)).
MacDonald and Harada et al. do not teach wherein the store operation is used to store data into the predetermined memory range.
However, Crawford et al. teaches wherein data targeted by the cache access is specified by an address that can be associated with a cache entry (see column 4, lines 51-56)… In ACCESS state 640, the cache entry to be accessed is identified through the targeted data's address, and the target data is either read from or written to the entry according to whether the access was triggered by a load or store (see column 7, lines 32-37).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by MacDonald to include the above mentioned to ensure the performance of the device (see Crawford, column 4, lines 39-44).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over MacDonald (US5,913,224), Harada et al. (US8,266,385) and Crawford et al. (US 6,542,966) as applied to claim 1 above, and further in view of Kim et al. (US 9,588,570).
With respect claim 2, MacDonald, Harada et al. and Crawford et al. do not teach wherein the predetermined conditions comprise that a bandwidth saving control register is set to have a predetermined value.
However, Kim et al. teaches bandwidth scaler 50 dynamically scales the bandwidth of the external memory 30 (see column 5, lines 38-42). Kim et al. also teaches wherein dynamic scaling of the bandwidth may involve comparing collected cache miss rates to a predetermined threshold, and determining to reduce the bandwidth in response to the collected cache miss rates (see column 2, lines 12-17)…the bandwidth of the external memory may be returned to a default bandwidth (i.e., predetermined value) (see column 10, lines 50-55).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by MacDonald, Harada et al. and Crawford et al. to include the above mentioned to ensure the performance of the device (see Kim, column 10, lines 39-44).
Claim(s) 4 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over MacDonald (US5,913,224), Harada et al. (US8,266,385) and Crawford et al. (US 6,542,966) as applied to claim 1 above, and further in view of Bryg et al. (US 5,586,297).
With respect claim 4, MacDonald, Harada et al. and Crawford et al. do not teach wherein the predetermined conditions comprise that the store operation uses an address conforming to cache line alignment.
However, Bryg et al. teaches wherein during a fast DMA transaction, data for I/O access of the page is aligned on cache line boundaries (see column 4, lines 5-7 and column 7, lines 13-15); and cache is searched to determine whether the cache contains data for the memory location (see column 3, lines 66-67).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by MacDonald, Harada et al. and Crawford et al. to include the above mentioned to improve the performance of the device (see Byrg, column 1, lines 7-10 and column 4, lines 5-35).
With respect claim 8, MacDonald, Harada et al. and Crawford et al. do not teach wherein the predetermined conditions comprise data to be stored in the store operation is allowed to be elongated without affecting other data.
However, Bryg et al. teaches allowing safe DMA to be designated for the case where DMA transactions are not aligned on cache line boundaries (i.e., long writes covering multiple boundaries) (see column 5, line 67, column 6, lines 1-2 and column 7, lines 39-44).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by MacDonald, Harada et al. and Crawford et al. to include the above mentioned to improve the performance of the device (see Byrg, column 1, lines 7-10 and column 4, lines 5-35).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over MacDonald (US5,913,224), Harada et al. (US8,266,385) and Crawford et al. (US 6,542,966) as applied to claim 1 above, and further in view of Han et al. (US 2018/0300086).
With respect claim 7, MacDonald, Harada et al. and Crawford et al. do not teach wherein the predetermined conditions comprise that the memory access instruction is corresponding to a store operation for storing null data.
However, Han et al. teaches I/O request that may bread request, a write request, or a zero request (see paragraph 66)…each time of read/write/zero miss, the IO service time is substantially consistent with the solution of not employing the metadata cache (i.e., zero miss) (see paragraph 43).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by MacDonald, Harada et al. and Crawford et al. to include the above mentioned to improve I/O performance (see Han, paragraph 43).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over MacDonald (US5,913,224), Harada et al. (US8,266,385) and Crawford et al. (US 6,542,966) as applied to claims 1 above, and further in view of Kilmer et al. (US 8,799,566).
With respect claim 9, MacDonald, Harada et al. and Crawford et al. do not teach wherein the memory access instruction is corresponding to a predetermined period, a bandwidth saving operation is performed during the predetermined period, and the main memory is not accessed during the predetermined period.
However, Kilmer et al. teaches wherein total lockout time in each refresh period is equal to tRFC.times.the number of refresh commands issued within the refresh period. Thus, there exists some optimum point for tRFC where the memory bandwidth can be maximized (see column 4, lines 9-24)… multiplexer 102 selects an external row address (e.g., from a read command, from a write command) or a refresh row address 114 from a refresh counter 104. The multiplexer 102 makes this selection based on a value of a refresh mode signal 116 that is output from a timing and mode controller 108. The timing and mode controller 108 issues the refresh mode signal 116 in response to receiving an external command (e.g., a refresh command received from a memory controller). Another refresh command 202 (or other command such as a read command or write command) cannot be issued until a minimum refresh cycle time or tRFC 204 has completed (i.e., memory is not accessed during the refresh operation) (see column 4, lines 39-67 and column 5, lines 1-8).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by MacDonald, Harada et al. and Crawford et al. to include the above mentioned to optimize the performance of the device (see Kilmer, column 4, lines 9-24).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over MacDonald (US5,913,224) in view of Han et al. (US2015/0143049) and in further view of Harada et al. (US8,266,385).
With respect claim 11, MacDonald teaches a processor configured to initiate a memory access instruction (see column 4, lines 7-10 and column 7, lines 17-18; processor initiates a read request);
a cache memory (see column 4, lines 5-10; L2 cache subsystem);
a cache controller coupled to the processor and the cache memory and configured to receive the memory access instruction to search the cache memory (see column 5, lines 6-8; cache management unit 202 preferably includes a memory controller for providing access to L2 cache memory 201), check if a cache miss occurs (see column 10, lines 23-25; indicating the existence of a cache miss on line 263 to replacement logic 287), and transmit a first signal if the cache miss occurs (see column 7, lines 17-18; processor initiates a read request. Also in column 10, lines 23-31; Comparator 260 compares the address to tags from tag logic 255 and indicates the existence of a cache miss on line 263 to replacement logic 287 (i.e., comparator included in the management unit of L2 cache subsystem sends a signal when a cache miss occurs));
an address detector coupled to the controller and configured to receive the second signal, check if the memory access instruction is corresponding to predetermined conditions only after the cache miss occurs (see column 7, lines 17-18; processor initiates a read request. Also in column 10, lines 23-31; Comparator 260 compares the address to tags from tag logic 255 and indicates the existence of a cache miss on line 263 to replacement logic 287. Comparator 285 consequently compares the address from processor interface 250 to the range of real-time addressed specified by registers 265 and determines that the address from processor interface 250 falls within the range of real-time addresses. Comparator 285 provides a signal on line 288 to replacement logic 287 indicating that the new address pertains to real-time code (i.e., address of the request received is compared to determine if it corresponds to a condition (i.e., falls within the range of real-time addresses) after a cache miss is detected), and transmit a third signal if the memory access instruction conforms to the predetermined conditions (see column 10, lines 23-31; comparator 285 consequently compares the address from processor interface 250 to the range of real-time addressed specified by registers 265 and determines that the address from processor interface 250 falls within the range of real-time addresses. Comparator 285 provides a signal on line 288 to replacement logic 287 indicating that the new address pertains to real-time code (i.e., address of the request received is compared to determine if it corresponds to a condition (i.e., a signal is sent to replacement logic of requested address falls within the range of real-time addresses)); and
a replacement mask logic unit coupled to the address detector and the controller and configured to receive the third signal (see column 10, lines 23-31; comparator 285 provides a signal on line 288 to replacement logic 287 indicating that the new address pertains to real-time code (i.e., address of the request received is compared to determine if it corresponds to a condition (i.e., a signal is sent to replacement logic of requested address falls within the range of real-time addresses)) and provide predetermined data to the bus transaction controller to store the predetermined data into the cache memory (see column 10, lines 7-10, 31-35 and 51-55; replacement logic 287 stores the data corresponding to the address from processor interface 250 in either data way);
MacDonald does not teach a bus transaction controller coupled to the cache controller and configured to receive the first signal, and transmit a second signal corresponding to the first signal; and wherein the memory access instruction is used to perform a store operation.
However, Han et al. teaches a controller coupled to a cache controller (see Fig. 2 and paragraph 36; memory controller 10 coupled to coherency controller) and configured to receive the first signal (see paragraph 36; coherency controller received hit/miss information from memory controller 10), and transmit a second signal corresponding to the first signal (see paragraph 36; coherency controller sends a read/write start to miss controller in response to the hit/miss information); and wherein the memory access instruction is used to perform a store operation (see paragraph 34; a write start instruction signal is received from the coherency controller 20).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by MacDonald to include the above mentioned to maintain or secure coherency (see Kim, paragraphs 2 and 13).
MacDonald and Han et al. do not teach provide predetermined data to the bus transaction controller to store the predetermined data into the cache memory without reading a main memory.
However, Harada et al. teaches wherein if a cache miss occurs in a write, it is preferable that write data be written to the cache memory 210 without reading data from the main memory 200 to the cache memory 210 (see column 6, lines 66-67 and column 7, lines 1-6).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by MacDonald and Han et al. to include the above mentioned to decrease access to the main memory (see Harada, column 7, lines 1-6).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over MacDonald (US5,913,224), Han et al. (US2015/0143049) and Harada et al. (US8,266,385) as applied to claim 11 above, and further in view of Kim et al. (US 9,588,570).
With respect claim 12, MacDonald, Han et al. and Harada et al. do not teach a bandwidth saving control register coupled to the address detector; wherein the address detector checks if the memory access instruction is corresponding to the predetermined conditions by checking if the bandwidth saving control register is set to have a predetermined value.
However, Kim et al. teaches bandwidth scaler 50 dynamically scales the bandwidth of the external memory 30 (see column 5, lines 38-42). Kim et al. also teaches wherein dynamic scaling of the bandwidth may involve comparing collected cache miss rates to a predetermined threshold, and determining to reduce the bandwidth in response to the collected cache miss rates (see column 2, lines 12-17)…the bandwidth of the external memory may be returned to a default bandwidth (i.e., predetermined value) (see column 10, lines 50-55).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by MacDonald, Han et al. and Harada et al. to include the above mentioned to ensure the performance of the device (see Kim, column 10, lines 39-44).
Claim(s) 14 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over MacDonald (US5,913,224), Han et al. (US2015/0143049) and Harada et al. (US8,266,385) as applied to claim 11 above, and further in view of Bryg et al. (US 5,586,297).
With respect claim 14, MacDonald, Han et al. and Harada et al. do not teach wherein the predetermined conditions comprise that the store operation uses an address conforming to cache line alignment.
However, Bryg et al. teaches wherein during a fast DMA transaction, data for I/O access of the page is aligned on cache line boundaries (see column 4, lines 5-7 and column 7, lines 13-15); and cache is searched to determine whether the cache contains data for the memory location (see column 3, lines 66-67).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by MacDonald, Han et al. and Harada et al. to include the above mentioned to improve the performance of the device (see Byrg, column 1, lines 7-10 and column 4, lines 5-35).
With respect claim 18, MacDonald, Han et al. and Harada et al. do not teach wherein the predetermined conditions comprise that data to be stored in the store operation is allowed to be elongated without affecting other data.
However, Bryg et al. teaches allowing safe DMA to be designated for the case where DMA transactions are not aligned on cache line boundaries (i.e., long writes covering multiple boundaries) (see column 5, line 67, column 6, lines 1-2 and column 7, lines 39-44).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by MacDonald, Han et al. and Harada et al. to include the above mentioned to improve the performance of the device (see Byrg, column 1, lines 7-10 and column 4, lines 5-35).
Claim(s) 15 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over MacDonald (US5,913,224), Han et al. (US2015/0143049) and Harada et al. (US8,266,385) as applied to claim 11 above, and further in view of Crawford et al. (US 6,542,966).
With respect claim 15, MacDonald, Han et al. and Harada et al. do not teach wherein the predetermined conditions comprise that the store operation covers a region comprising at least a cache line.
However, Crawford et al. teaches wherein when the cache miss is triggered by a store instruction, the line of cache data is updated with target data indicated by the store instruction before it is written to the cache entry (see column 7, lines 5-12).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by MacDonald, Han et al. and Harada et al. to include the above mentioned to ensure the performance of the device (see Crawford, column 4, lines 39-44).
With respect claim 20, MacDonald teaches wherein the memory access instruction is corresponding to a predetermined memory range (see column 10, lines 23-31; comparator 285 consequently compares the address from processor interface 250 to the range of real-time addressed specified by registers 265 and determines that the address from processor interface 250 falls within the range of real-time addresses. Comparator 285 provides a signal on line 288 to replacement logic 287 indicating that the new address pertains to real-time code (i.e., address of the request received is compared to determine if it corresponds to a condition (i.e., requested address falls within the range of real-time addresses)).
MacDonald, Han et al. and Harada et al. do not teach wherein the store operation is used to store data into predetermined memory range.
However, Crawford et al. teaches wherein data targeted by the cache access is specified by an address that can be associated with a cache entry (see column 4, lines 51-56)… In ACCESS state 640, the cache entry to be accessed is identified through the targeted data's address, and the target data is either read from or written to the entry according to whether the access was triggered by a load or store (see column 7, lines 32-37).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by MacDonald, Han et al. and Harada et al. to include the above mentioned to ensure the performance of the device (see Crawford, column 4, lines 39-44).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over MacDonald (US5,913,224), Han et al. (US2015/0143049) and Harada et al. Harada et al. (US8,266,385) as applied to claim 11 above, and further in view of Shindo (US 9,892,049).
With respect claim 16, MacDonald, Han et al. and Harada et al. do not teach wherein the predetermined conditions comprise that the store operation is performed in a fixed direction for writing data into consecutive addresses of the cache memory sequentially.
However, Shindo teaches wherein an address change direction flag (66) is provided for each of the ways to indicate either the direction in which the address is incremented or decremented with respect to the last two accesses to the way… When a first way and a second way are accesses that are performed in succession to consecutive addresses from the processor to the memory (see column 4, lines 21-27).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by MacDonald, Han et al. and Harada et al. to include the above mentioned to reduce the probability if cache misses (see Shindo, column 5, lines 50-56).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over MacDonald (US5,913,224), Han et al. (US2015/0143049) and Harada et al. (US8,266,385) as applied to claim 11 above, and further in view of Han et al. (US 2018/0300086).
With respect claim 17, MacDonald, Han et al. and Harada et al. do not teach wherein the predetermined conditions comprise that store operation I performed for storing null data.
However, Han et al. teaches I/O request that may bread request, a write request, or a zero request (see paragraph 66)…each time of read/write/zero miss, the IO service time is substantially consistent with the solution of not employing the metadata cache (i.e., zero miss) (see paragraph 43).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by MacDonald, Han et al. and Harada et al. to include the above mentioned to improve I/O performance (see Han, paragraph 43).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over MacDonald (US5,913,224), Harada et al. (US8,266,385) and Harada et al. (US8,266,385) as applied to claim 11 above, and further in view of Kilmer et al. (US 8,799,566).
With respect claim 19, MacDonald, Han et al. and Harada et al. do not teach wherein the memory access instruction is corresponding to a predetermined period, a bandwidth saving operation is performed during the predetermined period, and the main memory is not accessed during the predetermined period.
However, Kilmer et al. teaches wherein total lockout time in each refresh period is equal to tRFC.times.the number of refresh commands issued within the refresh period. Thus, there exists some optimum point for tRFC where the memory bandwidth can be maximized (see column 4, lines 9-24)… multiplexer 102 selects an external row address (e.g., from a read command, from a write command) or a refresh row address 114 from a refresh counter 104. The multiplexer 102 makes this selection based on a value of a refresh mode signal 116 that is output from a timing and mode controller 108. The timing and mode controller 108 issues the refresh mode signal 116 in response to receiving an external command (e.g., a refresh command received from a memory controller). Another refresh command 202 (or other command such as a read command or write command) cannot be issued until a minimum refresh cycle time or tRFC 204 has completed (i.e., memory is not accessed during the refresh operation) (see column 4, lines 39-67 and column 5, lines 1-8).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by MacDonald, Han et al. and Harada et al. include the above mentioned to optimize the performance of the device (see Kilmer, column 4, lines 9-24).
Response to Arguments
Applicant's arguments with respect to claims 1-2, 4-12 and 14-20 have been considered but are moot in view of the new ground(s) of rejection, necessitated by amendment.
Applicant’s arguments, see page 6, filed 03/16/2026, with respect to the objection of claim 11 have been fully considered and are persuasive. The objection of the claim has been withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARACELIS RUIZ whose telephone number is (571)270-1038. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald G. Bragdon can be reached at (571)272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ARACELIS RUIZ/Primary Examiner, Art Unit 2139
Prosecution Insights