1676DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/29/2025 has been entered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 10733938. Although the claims at issue are not identical, they are not patentably distinct from each other because both applications recite substantially similar claim limitations.
18/827881
U.S. Patent No. 10733938
A display panel comprising:
a plurality of pixels, wherein a pixel of the plurality of pixels comprises:
a light emitting element;
a first transistor comprising a control electrode connected to a first node, a first electrode configured to receive a first power source signal and a second electrode connected to a first electrode of the light emitting element;
a first capacitor connected between an initialization electrode and the first node;
a second transistor comprising a control electrode configured to receive a scan signal, a first electrode connected to the first node and a second electrode connected to a first intermediate node;
a third transistor comprising a control electrode configured to receive the scan signal, a first electrode connected to the first intermediate node and a second electrode connected to a first electrode of a second capacitor; and
a fourth transistor connected between the initialization electrode and the first electrode of the light emitting element.
1. A display apparatus which comprises a plurality of pixels, each pixel of the plurality of pixels comprising:
an organic light emitting diode emitting a light;
a first voltage line receiving a first driving signal;
a second voltage line receiving a power source signal;
a third voltage line receiving a second driving signal;
a first transistor comprising a first electrode connected to the second voltage line and a second electrode connected to the organic light emitting diode;
a second transistor comprising a control electrode connected to an n-th scan line (wherein, ‘n’ is a natural number), a first electrode connected to a control electrode of the first transistor and a second electrode connected to the organic light emitting diode; and
a third transistor comprising a control electrode connected to the third voltage line, a first electrode connected to the first voltage line and a second electrode connected to the organic light emitting diode.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 - 12 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Many claims failed to comply with the written description requirement.
As one of example, claim 1 recites “a second transistor” in line 8.
Claim 1 recites “a third transistor” in line 9.
Argument page 5 annotated T2 as second transistor and third transistor are two separate transistor.
Spec [00217] discloses: "According to the exemplary embodiment, the second transistor T2 may have a dual gate structure to avoid a leakage current".
Spec discloses T2 is a single transistor has dual gate structure.
Therefore, spec discloses T2 is a single transistor.
Applicant intended to amend “a [2-1] transistor and a [2-2] transistor” to “a second transistor” and “a third transistor”.
“a second transistor” and “a third transistor” are two separate transistor.
Therefore, claim 1 fails to comply with written description requirement.
Claim 1 recites “a fourth transistor” in line 14.
Argument page 5 annotated T3 as fourth transistor.
Spec [0218] discloses Referring to FIG. 10 , a pixel circuit PC3 may include a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor Cst, a second capacitor Cpr and an organic light emitting diode OLED. According to the exemplary embodiment, the second transistor T2 may have a dual gate structure to avoid a leakage current”.
Independent claims 7 and 10 have similar issue as claim 1.
Claims 2 – 6, 8, 9, 11, 12 have same issue because of claim dependency.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 - 12 are rejected under 35 U.S.C. 103 as being unpatentable over Zhou et al. (U.S. Patent Publication 20160314742 A1, Filed: 4/23/2015) in view of Kim et al. (U.S. Patent Publication 20130321376 A1).
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Regarding claim 1, Zhou discloses “A display panel comprising:
a plurality of pixels, wherein a pixel of the plurality of pixels comprises: ([0006] organic light-emitting diode (OLED) pixel compensation circuit)
a light emitting element; (Fig 1. OLED, [0005])
a first transistor (Fig 1. T3) comprising a control electrode connected to a first node, a first electrode configured to receive a first power source signal (Fig 1. ELVDD [0005] [0071]) and a second electrode connected to a first electrode of the light emitting element;
a first capacitor (Fig 1. Cst [0098] [0105]) connected between an initialization electrode and the first node;
a second transistor (Fig 1. upper gate portion of T5 [0005]) comprising a control electrode configured to receive a scan signal (Fig 1. Sn), a first electrode connected to the first node and a second electrode connected to a first intermediate node; ([0005] [0064])
a third transistor (Fig 1. lower gate portion of T5) comprising a control electrode configured to receive the scan signal, (Fig 1. Sn) a first electrode connected to the first intermediate node and; ([0005] [0064] – [0067]) and
a fourth transistor (Fig 1. T7) connected between the initialization electrode and the first electrode of the light emitting element. (Fig 1. OLED)
Zhou does not disclose “a second electrode connected to a first electrode of a second capacitor”.
Kim discloses “a second electrode connected to a first electrode of a second capacitor”. (Fig. 2, C2 [0039] [0045] – [0047])
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate second capacitor by Kim into device of Zhou. The suggestion/motivation would have been to improve efficiency. (Kim: [0012])
Regarding claims 2, 8, 11, Zhou and Kim disclose wherein the second capacitor includes the first electrode connected to the second electrode of the third transistor and a second electrode configured to receive a data voltage. (Kim Fig. 2, C2)
Regarding claim 3, Zhou and Kim disclose wherein the fourth transistor is directly connected to the third transistor. (Zhou Fig. 1, [0005] [0064] – [0067])
Regarding claim 4, Zhou and Kim disclose wherein the fourth transistor is directly connected to the second capacitor. (Zhou Fig. 1, [0005] [0064] – [0067])
Regarding claim 5 Zhou and Kim disclose wherein the fourth transistor is directly connected to the first electrode of the light emitting element, the first electrode of the second capacitor and the second electrode of the third transistor. (Zhou Fig. 1, [0005] [0064] – [0067])
Regarding claim 6, Zhou and Kim disclose wherein a second electrode of the light emitting element is configured to receive a second power source signal. (Zhou Fig. 1, [0005] [0064] – [0067])
Regarding claim 7, Zhou discloses “A display panel comprising:
a plurality of pixels, wherein a pixel of the plurality of pixels comprises: ([0006] organic light-emitting diode (OLED) pixel compensation circuit)
a light emitting element; (Fig 1. OLED, [0005])
a first transistor (Fig 1. T3) comprising a control electrode connected to a first node, a first electrode configured to receive a first power source signal (Fig 1. ELVDD [0005] [0071]) and a second electrode connected to a first electrode of the light emitting element; (Fig 1. OLED, [0005])
a first capacitor (Fig 1. Cst [0098] [0105]) connected between an initialization electrode and the first node;
a second transistor (Fig 1. T1 [0005]) comprising a control electrode configured to receive a scan signal, (Fig 1. Sn) a first electrode connected to the first node and
a third transistor (Fig 1. upper gate portion of T6) and a fourth transistor (Fig 1. lower gate portion of T6) which are connected each other in series and which are connected between the initialization electrode and the first electrode of the light emitting element.
Zhou does not disclose “a second electrode connected to a first electrode of a second capacitor”.
Kim discloses “a second electrode connected to a first electrode of a second capacitor”. (Fig. 2, C2 [0039] [0045] – [0047])
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate second capacitor by Kim into device of Zhou. The suggestion/motivation would have been to improve efficiency. (Kim: [0012])
Regarding claim 9, wherein the third transistor includes a control electrode configured to receive a driving signal, a first electrode connected to the initialization electrode and a second electrode connected to a second intermediate node; (Zhou Fig. 1, [0005] [0064] – [0067])
and wherein the fourth transistor includes a control electrode configured to receive the driving signal, a first electrode connected to the second intermediate node and a second electrode connected to the first electrode of the light emitting element. (Zhou Fig. 1, [0005] [0064] – [0067])
Regarding claim 10, Zhou discloses “A display panel comprising:
a plurality of pixels, wherein a pixel of the plurality of pixels comprises: ([0006] organic light-emitting diode (OLED) pixel compensation circuit)
a light emitting element; (Fig 1. OLED, [0005])
a first transistor (Fig 1. T3) comprising a control electrode connected to a first node, a first electrode configured to receive a first power source signal (Fig 1. ELVDD [0005] [0071]) and a second electrode connected to a first electrode of the light emitting element;
a first capacitor (Fig 1. Cst [0098] [0105]) connected between an initialization electrode and the first node;
a second transistor (Fig 1. upper gate portion of T5 [0005]) comprising a control electrode configured to receive a scan signal, (Fig 1. Sn) a first electrode connected to the first node and a second electrode connected to a first intermediate node;
a third transistor (Fig 1. lower gate portion of T5) comprising a control electrode configured to receive the scan signal, a first electrode connected to the first intermediate node and a second electrode connected to a first electrode of a second capacitor; and
a fourth transistor (Fig 1. upper gate portion of T6) and a fifth transistor (Fig 1. lower gate portion of T6) which are connected each other in series and which are connected between the initialization electrode and the first electrode of the light emitting element. (Fig 1. OLED, [0005])
Zhou does not disclose “a second electrode connected to a first electrode of a second capacitor”.
Kim discloses “a second electrode connected to a first electrode of a second capacitor”. (Fig. 2, C2 [0039] [0045] – [0047])
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate second capacitor by Kim into device of Zhou. The suggestion/motivation would have been to improve efficiency. (Kim: [0012])
Regarding claim 12, wherein the fourth transistor includes a control electrode configured to receive a driving signal, a first electrode connected to the initialization electrode and a second electrode connected to a second intermediate node; (Zhou Fig. 1, [0005] [0064] – [0069])
and wherein the fifth transistor includes a control electrode configured to receive the driving signal, a first electrode connected to the second intermediate node and a second electrode connected to the first electrode of the light emitting element. (Zhou Fig. 1, [0005] [0064] – [0069])
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 - 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/CHUN-NAN LIN/Primary Examiner, Art Unit 2629