Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/09/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-19 are rejected under 35 U.S.C. 103 as being unpatentable over Palanduz in the US Patent Application Publication Number US 20090233047 A1 in view of Eldridge et al. (Hereinafter, “Eldridge”) in the US Patent Application Publication Number US 20020132501 A1.
Regarding claim 1, Palanduz teaches an interposer package [10] (substrate 10 as the interposer package) in Figure 1 mounted between a test device package [20] (an integrated circuit as the test device package) mounted on a burn-in board and a burn-in board [30] (package substrate, a motherboard, or a printed circuit board (PCB) as the burn-in board- Burn-In Board (BIB), also called a Burn-In PCB, is a specialized PCB therefore PCB disclosed by Palanduz can be considered as a burn-in board) (A substrate, such as a package substrate or an interposer substrate, having a gradient coefficient of thermal expansion (CTE) is described herein. Connection of the substrate having a gradient CTE to a die and another substrate or motherboard to reduce thermomechanical stress at the interconnection members is also described herein; Paragraph [0015] Line 1-6; With reference to FIG. 1, a substrate 10 is shown connecting a first device 20 and a second device 30; Paragraph [0017] Line 1-2; In some embodiments, first device 20 is a die having an integrated circuit at a lower surface thereof. In some embodiments, first device 20 is silicon. In some embodiments, second device 30 may be a package substrate, a motherboard, or a printed circuit board (PCB). In some embodiments, second device 30 is another ceramic substrate. In some embodiments, second device 30 is plastic. In some embodiments, second device 30 is a PCB of a plastic package substrate; Paragraph [0018] Line 1-9), the interposer package [10] (A substrate, such as a package substrate or an interposer substrate; Paragraph [0015] Line 1-2) comprising:
a first substrate [16] (lower layer 16 as the first substrate) (Substrate 10 includes an upper layer 12, an intermediate layer 14, and a lower layer 16. A plurality of conductive vias 18 extend through each of the layers 12, 14, 16; Paragraph [0022] Line 1-3; A substrate in semiconductor manufacturing is the base material, typically a thin disc of highly pure silicon, on which all the microscopic circuits of a chip are built; https://scienceinsights.org/what-is-a-substrate-in-semiconductor-devices/; Therefore the lower layer and upper layer can be considered as a substrate) having a coefficient of expansion that is the same or substantially the same as a coefficient of expansion of the burn-in board [30] (In some embodiments, the CTE of the lower layer 16 matches the CTE of the second device 30; Paragraph [0026] Line 1-3);
a second substrate [12] (upper layer 12 as the second substrate) (Substrate 10 includes an upper layer 12, an intermediate layer 14, and a lower layer 16. A plurality of conductive vias 18 extend through each of the layers 12, 14, 16; Paragraph [0022] Line 1-3; A substrate in semiconductor manufacturing is the base material, typically a thin disc of highly pure silicon, on which all the microscopic circuits of a chip are built; https://scienceinsights.org/what-is-a-substrate-in-semiconductor-devices/; Therefore the lower layer and upper layer can be considered as a substrate) having a coefficient of expansion that is the same or substantially the same as a coefficient of expansion of the test device package [20] (In some embodiments, the CTE of upper layer 12 matches the CTE of the first device 20; Paragraph [0026] Line 1-2);
a first sheet contact [14] (intermediate layer 14 as the first sheet contact as this layer function as a contact between first and second layer) inserted between the first
substrate [16] and the second substrate [12] (Substrate 10 includes an upper layer 12, an intermediate layer 14, and a lower layer 16. A plurality of conductive vias 18 extend through each of the layers 12, 14, 16; Paragraph [0022] Line 1-3); and
wherein the first sheet contact [14] is sandwiched between the first substrate [16] and the second substrate [12] (Substrate 10 includes an upper layer 12, an intermediate layer 14, and a lower layer 16. A plurality of conductive vias 18 extend through each of the layers 12, 14, 16; Paragraph [0022] Line 1-3), thereby electrically connecting the burn-in board [30] and the test device packages [20] to each other (With reference to FIG. 1, a substrate 10 is shown connecting a first device 20 and a second device 30; Paragraph [0017] Line 1-2; The first device 20 may include an integrated circuit formed in a lower surface thereof. A plurality of contact pads 22 are formed on a lower surface of the first device 20 and are electrically and mechanically connected to the integrated circuit. Each one of the contact pads 22 matches up with a respective contact pad 23 on an upper surface of the substrate 10. The contact pads 22 of first device 20 are connected to the contact pads 23 of substrate 10 by a respective one of conductive interconnection members 24; Paragraph [0019] Line 1-9; A plurality of contact pads 32 are also provided on an upper surface of the substrate 30. Each one of the contact pads 32 on the upper surface of second device 30 matches up with a respective one of the contact pads 33 on substrate 10. Conductive interconnection members 34 interconnect contact pads 32 of second device 30 with contact pads 33 of substrate 10 to mechanically and electrically connect substrate 10 and second device 30; Paragraph [0020] 1-8).
However, Palanduz fails to teach that a case configured to seal the first substrate, the second substrate, and the first sheet contact, and the first substrate, the second substrate, and the first sheet contact is sealed with the case applying a predetermined pressure, thereby maintaining the electrical connection.
Eldridge teaches wafer level interposers, and more particularly to interposers having double-sided contact elements for interfacing two electrical devices, and to methods for making such interposers (Paragraph [0001] Line 1-4) and a method of the present invention also enables performing wafer-level burn-in and test of a plurality of semiconductor devices (DUTs) resident on a semiconductor wafer (Paragraph [0010] Line 1-4), wherein
a case [1018] (Housing 1018 in Figure 3a/Housing assembly 1034 in Figure 3b as the case) (Wafer 1012 is secured to a base support 1016 and the housing assembly 1018 supports contactor 1010. As shown in FIG. 3a, substrate 1004 has disposed thereupon one or more compression stops 1014 for preventing over-compression of the resilient contact elements 1006 and 1008; Paragraph [0050] Line 10-15; Wafer contactor 1036 is supported in housing assembly 1034. Interposer 1032 comprises a substrate 1040 and a plurality of contact elements 1046 on the top of substrate 1040, and another set of contact elements 1048 attached to the bottom of substrate 1040; Paragraph [0054] Line 4-8) configured to seal the first substrate, the second substrate, and the first sheet contact (Interposer 1002 includes a substrate 1004 with a first surface and a second surface upon each of which surfaces are disposed a plurality of resilient contact elements, 1006 and 1008; Paragraph [0050] Line 4-8; Figure 3a/3b shows housing assembly 1018 with the rigid supports 1020 /housing assembly 1034 with the placement constraints 1042 and 1038 seal the interposer (comprising first substrate, second substrate and first sheet contact as disclosed by Palanduz)), and
the first substrate, the second substrate, and the first sheet contact (Interposer 1002 includes a substrate 1004 with a first surface and a second surface upon each of which surfaces are disposed a plurality of resilient contact elements, 1006 and 1008; Paragraph [0050] Line 4-8; first substrate, second substrate and first sheet contact as disclosed by Palanduz) is sealed with the case applying a predetermined pressure, thereby maintaining the electrical connection (FIGS. 3a and 3b illustrate exemplary interconnect assemblies. The interconnect assembly 1000 is shown to include an interposer 1002. Interposer 1002 includes a substrate 1004 with a first surface and a second surface upon each of which surfaces are disposed a plurality of resilient contact elements, 1006 and 1008. In FIG. 3a, an interposer 1002 establishes contact between a wafer 1012 and a wafer contactor 1010 through pressure contacts applied to the contact elements 1006 and 1008; Paragraph [0050] Line 2-10; In operation, pressure contact is applied to wafer 1012 moving the latter in the z-direction toward wafer contactor 1010, thereby meeting and then compressing resilient contact elements 1008. When contact elements 1008 are compressed, resilient contact elements 1006 are also compressed thereby establishing mechanical contact between the terminals of wafer 1012 and the terminals of the wafer contactor 1010; Paragraph [0052] Line 1-8; therefore, the interposer (the first substrate, the second substrate, and the first sheet contact in view of Palanduz) is sealed with the case applying a predetermined pressure, thereby maintaining the electrical connection). The purpose of doing so is to enable performing wafer-level burn-in and test of a plurality of semiconductor devices (DUTs) resident on a semiconductor wafer, to prevent over-compression of the resilient contact elements, to prevent damage of resilient contact elements, to determine whether the dies are non-functional or partially functional (each, "bad" die), prior to singulating the dies from the wafer, to connect resilient interconnect elements or other types of interconnect elements onto the DUT and/or the device being packaged, to perform testing, exercising and burn-in in particular.
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Rogers in view of Eldridge, because Eldridge teaches to include a case to seal the first substrate, the second substrate, and the first sheet contact enables performing wafer-level burn-in and test of a plurality of semiconductor devices (DUTs) resident on a semiconductor wafer, prevents over-compression of the resilient contact elements (Paragraph [0050]), prevents damage of resilient contact elements (0052), determines whether the dies are non-functional or partially functional (each, "bad" die), prior to singulating the dies from the wafer (Paragraph [0002]), connects resilient interconnect elements or other types of interconnect elements onto the DUT and/or the device being packaged (Paragraph [0008]), performs testing, exercising and burn-in in particular (Paragraph [0045]).
Regarding claim 2, Palanduz teaches an interposer package, further
comprising:
a third substrate [227] (layer 227 as the third substrate as any layer can be considered as the substrate) (In some embodiments, substrate 10 includes a plurality of layers, as illustrated in FIGS. 2 and 3. Layer 14 is shown in FIG. 2 having a plurality of layers 219, 221, 223, . . . 225, 227, 229. Layer 14 may include more or less than the six layers presently illustrated; Paragraph [0033] Line 1-5) disposed between the first substrate [16] and the first sheet contact [223/225] (Figure 2: Modified Figure 2 of Palanduz below shows a third substrate [227] disposed between the first substrate [16] and the first sheet contact [223/225]);
a fourth substrate [221] (layer 221 as the fourth substrate as any layer can be considered as the substrate) (In some embodiments, substrate 10 includes a plurality of layers, as illustrated in FIGS. 2 and 3. Layer 14 is shown in FIG. 2 having a plurality of layers 219, 221, 223, . . . 225, 227, 229. Layer 14 may include more or less than the six layers presently illustrated; Paragraph [0033] Line 1-5) disposed between the second substrate [12] and the first sheet contact [223/225] (Figure 2: Modified Figure 2 of Palanduz below shows a third substrate [221] disposed between the first substrate [16] and the first sheet contact [223/225]);
a second sheet contact [229] (layer 229 as the second sheet contact as any layer can be considered as the sheet contact as the layer contacts with the other layers) disposed between the first substrate [16] and the third substrate [227] (Figure 2: Modified Figure 2 of Palanduz below shows a second sheet contact [229] disposed between the first substrate [16] and the third substrate [227]); and
a third sheet contact [219] (layer 219 as the third sheet contact as any layer can be considered as the sheet contact as the layer contacts with the other layers) (In some embodiments, substrate 10 includes a plurality of layers, as illustrated in FIGS. 2 and 3. Layer 14 is shown in FIG. 2 having a plurality of layers 219, 221, 223, . . . 225, 227, 229. Layer 14 may include more or less than the six layers presently illustrated; Paragraph [0033] Line 1-5) disposed between the second substrate [12] and the fourth substrate [221] ((Figure 2: Modified Figure 2 of Palanduz below shows a third sheet contact [219] disposed between the second substrate [12] and the fourth substrate [221]), wherein
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Figure 2: Modified Figure 2 of Palanduz
when the coefficient of expansion of the burn-in board [30] is larger than the coefficient of expansion of the test device package [20] (The CTE gradient refers to a plurality of CTE's, the plurality of CTE's incrementally increasing or decreasing between the upper and lower surfaces of the substrate; Paragraph [0016] Line 1-3; In some embodiments, the CTE of upper layer 12 matches the CTE of the first device 20 and the CTE of the lower layer 16 matches the CTE of the second device 30; Paragraph [0026] Line 1-3; when CTE incrementally decreasing from bottom to top (from first substrate to second substrate) then the CTE of the burn-in board 30 is larger than CTE of test device package 20 as the CTE of the burn-in board is same as first substrate and CTE of the test device 20 is same as the second substrate),
a coefficient of expansion of the third substrate [227] is smaller than the coefficient of expansion of the first substrate [16] and larger than a coefficient of expansion of the fourth substrate [221] (The CTE of layers 12, 14, 16 gradually vary to create a CTE gradient between the upper and lower surfaces (in the z-direction) of substrate 10. That is, the CTE of the substrate is incrementally increased or decreased between the upper and lower surfaces of the substrate by forming each layer 12, 14, 16, such that each one of the layers 12, 14, 16 has a different CTE corresponding therewith; Paragraph [0023] Line 1-7; As the CTE incrementally decreasing then a coefficient of expansion of the third substrate 227 is smaller than the coefficient of expansion of the first substrate 16 and larger than a coefficient of expansion of the fourth substrate 221 as shown in Figure 2: Modified Figure 2 of Palanduz above), and
the coefficient of expansion of the fourth substrate [221] is larger than the coefficient of expansion of the second substrate [12] and small than the coefficient of expansion of the third substrate [227] (As the CTE incrementally decreasing from bottom to top, the coefficient of expansion of the fourth substrate [221] is larger than the coefficient of expansion of the second substrate [12] and small than the coefficient of expansion of the third substrate [227] as shown in Figure 2: Modified Figure 2 of Palanduz above), and
when the coefficient of expansion of the test device package [20] is larger than a coefficient of expansion of the burn-in board [30] (The CTE gradient refers to a plurality of CTE's, the plurality of CTE's incrementally increasing or decreasing between the upper and lower surfaces of the substrate; Paragraph [0016] Line 1-3; In some embodiments, the CTE of upper layer 12 matches the CTE of the first device 20 and the CTE of the lower layer 16 matches the CTE of the second device 30; Paragraph [0026] Line 1-3; when CTE incrementally increasing from bottom to top (from first substrate to second substrate) then the CTE of the burn-in board 30 is smaller than CTE of test device package 20 as the CTE of the burn-in board is same as first substrate and CTE of the test device 20 is same as the second substrate),
the coefficient of expansion of the fourth substrate [221] is smaller than the coefficient of expansion of the second substrate [12] and larger than the coefficient of expansion of the third substrate [227] (As the CTE incrementally increasing from bottom to top, the coefficient of expansion of the fourth substrate [221] is smaller than the coefficient of expansion of the second substrate [12] and larger than the coefficient of expansion of the third substrate [227] as shown in Figure 2: Modified Figure 2 of Palanduz above), and
the coefficient of expansion of the third substrate [227] is larger than the coefficient of expansion of the first substrate [16] and smaller than the coefficient of expansion of the fourth substrate [221] (As the CTE incrementally increasing from bottom to top, the coefficient of expansion of the third substrate 227 is larger than the coefficient of expansion of the first substrate 16 and smaller than a coefficient of expansion of the fourth substrate 221 as shown in Figure 2: Modified Figure 2 of Palanduz above).
Regarding claim 3, Palanduz teaches an interposer package, further comprising:
at least one through electrode [18] (conductive vias 18 as the electrode as the vias made of conductive material) (A plurality of conductive vias 18 extend through each of the layers 12, 14, 16; Paragraph [0022] Line 2-3; Electrodes are conductive elements that serve as the interface between an electrical circuit and another medium — such as a liquid, gas, or solid — enabling the transfer of electrical energy or signals. In PCBs, electrodes are typically copper traces, pads, or vias that connect components and power planes. In electrochemistry or sensors, they may be metal surfaces that contact an electrolyte or dielectric; Via: A specific type of electrode structure used to interconnect layers in a PCB or IC, formed by a plated hole between layers; https://www.bing.com/search?q=electrode%20and%20via&qs=n&form=QBRE&sp=-1&lq=0&pq=electrode%20and%20via&sc=12-17&sk=&cvid=78D9022617C5418593E69564415EFB83) disposed passing through the first substrate [16], the second substrate [12], and the first sheet contact [14] (Each contact pad 23, 33 of substrate 10 is located on and mechanically and electrically connected to a respective one of the plurality of conductive vias 18. In some embodiments, vias 18 have a CTE gradient similar to or matching the CTE gradient of substrate 10 to reduce stress due to thermal expansivity mismatch within the substrate and at interconnection members 24, 34. Plurality of vias 18 each include an upper conductive via 13, an intermediate conductive via 15 and a lower conductive via 17; Paragraph [0027] Line 1-9; Typically, vias 18 are formed from a conductive material, such as copper, silver, or an alloy of tungsten and molybdenum. By varying the material composition and characteristics of the metallic paste used to form vias 13, 15, 17 of vias 18 between the upper and lower surfaces of the substrate; Paragraph [0030] Line 1-4),
the through electrode [18] having one end welded to the burn-in board [30] (A plurality of contact pads 32 are also provided on an upper surface of the substrate 30. Each one of the contact pads 32 on the upper surface of second device 30 matches up with a respective one of the contact pads 33 on substrate 10. Conductive interconnection members 34 interconnect contact pads 32 of second device 30 with contact pads 33 of substrate 10 to mechanically and electrically connect substrate 10 and second device 30; Paragraph [0020] Line 1-8; through electrode 18 (13+15+17) having welded in one end with the contact pad 32 in the burn-in board and with the contact pad 33 in the first substrate 16) and the other end welded to the test device package [20] (The first device 20 may include an integrated circuit formed in a lower surface thereof. A plurality of contact pads 22 are formed on a lower surface of the first device 20 and are electrically and mechanically connected to the integrated circuit. Each one of the contact pads 22 matches up with a respective contact pad 23 on an upper surface of the substrate 10. The contact pads 22 of first device 20 are connected to the contact pads 23 of substrate 10 by a respective one of conductive interconnection members 24; Paragraph [0019] Line 1-9; through electrode 18 (13+15+17) having welded in one end with the contact pad 22 in the test device package and with the contact pad 23 in the second substrate 12).
Regarding claim 4, Palanduz teaches an interposer package,
wherein the test device package [20] is a BGA package (In some embodiments, the conductive interconnection members 24, 34, 39 are solder balls connections, wirebond connections, tape automated bonding (TAB) connections or C4 connections. In some embodiments, interconnection member 24, 34, 39 are ball grid array (BGA) connections; Paragraph [0021] Line 1-5), and
the first substrate [16] is mounted on the burn-in board [30] with
a BGA [34] (interconnection 34 as the BGA) arranged on the first substrate [16] (Conductive interconnection members 34 interconnect contact pads 32 of second device 30 with contact pads 33 of substrate 10 to mechanically and electrically connect substrate 10 and second device 30; Paragraph [0020] Line 5-8).
Regarding claim 5, Palanduz teaches an interposer package,
Wherein the test device package [20] is an LGA package (In some embodiments, interconnection member 24, 34, 39 are ball grid array (BGA) connections. In some embodiments, interconnections members 39 are I/O connections, such as through-hole and surface mounted connections. Interconnection members 39 may also be pins or land grid array (LGA) connections; Paragraph [0021] Line 4-10), and
the first substrate [16] is mounted on the burn-in board [30] with
a plug pin [34/39] arranged on the first substrate [16] (Figure 1) (Conductive interconnection members 34 interconnect contact pads 32 of second device 30 with contact pads 33 of substrate 10 to mechanically and electrically connect substrate 10 and second device 30; Paragraph [0020] Line 5-8; Figure 1 shows the first substrate [16] is mounted on the burn-in board [30] with a plug pin [34/39] arranged on the first substrate).
Regarding claim 6, Palanduz teaches an interposer package,
wherein the BGA package [24] is mounted to a plug pin [39] arranged on the
second substrate [12] (In some embodiments, interconnection member 24, 34, 39 are ball grid array (BGA) connections. In some embodiments, interconnections members 39 are I/O connections, such as through-hole and surface mounted connections. Interconnection members 39 may also be pins or land grid array (LGA) connections; Paragraph [0021] Line 4-10).
Regarding claim 7, Palanduz teaches an interposer package,
wherein the BGA package [24] is mounted to a pad [23] arranged on the second substrate [12] (Each one of the contact pads 22 matches up with a respective contact pad 23 on an upper surface 12 of the substrate 10. The contact pads 22 of first device 20 are connected to the contact pads 23 of substrate 10 by a respective one of conductive interconnection members 24; Paragraph [0019] Line 5-9).
Regarding claim 8, Palanduz teaches a mounting method comprising:
mounting the interposer package [10] (A substrate, such as a package substrate or an interposer substrate; Paragraph [0015] Line 1-2) according to claim 1 (See rejection of claim 1 above) on the burn-in board [30] (A substrate, such as a package substrate or an interposer substrate, having a gradient coefficient of thermal expansion (CTE) is described herein. Connection of the substrate having a gradient CTE to a die and another substrate or motherboard to reduce thermomechanical stress at the interconnection members is also described herein; Paragraph [0015] Line 1-6; With reference to FIG. 1, a substrate 10 is shown connecting a first device 20 and a second device 30; Paragraph [0017] Line 1-2); and
mounting the test device package [20] on the interposer package [10] (A substrate, such as a package substrate or an interposer substrate, having a gradient coefficient of thermal expansion (CTE) is described herein. Connection of the substrate having a gradient CTE to a die and another substrate or motherboard to reduce thermomechanical stress at the interconnection members is also described herein; Paragraph [0015] Line 1-6; With reference to FIG. 1, a substrate 10 is shown connecting a first device 20 and a second device 30; Paragraph [0017] Line 1-2; In some embodiments, first device 20 is a die having an integrated circuit at a lower surface thereof. In some embodiments, first device 20 is silicon. In some embodiments, second device 30 may be a package substrate, a motherboard, or a printed circuit board (PCB). In some embodiments, second device 30 is another ceramic substrate. In some embodiments, second device 30 is plastic. In some embodiments, second device 30 is a PCB of a plastic package substrate; Paragraph [0018] Line 1-9).
Regarding claim 9, Palanduz teaches a mounting method,
wherein the test device package [20] is a BGA package (In some embodiments, the conductive interconnection members 24, 34, 39 are solder balls connections, wirebond connections, tape automated bonding (TAB) connections or C4 connections. In some embodiments, interconnection member 24, 34, 39 are ball grid array (BGA) connections; Paragraph [0021] Line 1-5), and
when mounting the interposer package [10] on the burn-in board [30] (With reference to FIG. 1, a substrate 10 is shown connecting a first device 20 and a second device 30; Paragraph [0017] Line 1-2),
the first substrate [16] is mounted on the burn-in board [30] with a BGA [34] (interconnection 34 as the BGA) arranged on the first substrate [16] (Conductive interconnection members 34 interconnect contact pads 32 of second device 30 with contact pads 33 of substrate 10 to mechanically and electrically connect substrate 10 and second device 30; Paragraph [0020] Line 5-8).
Regarding claim 10, Palanduz teaches a mounting method,
wherein the test device package [20] is an LGA package (In some embodiments, interconnection member 24, 34, 39 are ball grid array (BGA) connections. In some embodiments, interconnections members 39 are I/O connections, such as through-hole and surface mounted connections. Interconnection members 39 may also be pins or land grid array (LGA) connections; Paragraph [0021] Line 4-10), and
when mounting the interposer package [10] on the burn-in board [30] (With reference to FIG. 1, a substrate 10 is shown connecting a first device 20 and a second device 30; Paragraph [0017] Line 1-2),
the first substrate [16] is mounted on the burn-in board [30] with a plug pin [34/39] arranged on the first substrate [16] (Figure 1) (Conductive interconnection members 34 interconnect contact pads 32 of second device 30 with contact pads 33 of substrate 10 to mechanically and electrically connect substrate 10 and second device 30; Paragraph [0020] Line 5-8; Figure 1 shows the first substrate [16] is mounted on the burn-in board [30] with a plug pin [34/39] arranged on the first substrate).
Regarding claim 11, Palanduz teaches a mounting method,
wherein when mounting the BGA package [24] on the interposer package [10] (With reference to FIG. 1, a substrate 10 is shown connecting a first device 20 and a second device 30; Paragraph [0017] Line 1-2),
the BGA package [24] is mounted to a plug pin [39] arranged on the
second substrate [12] (In some embodiments, interconnection member 24, 34, 39 are ball grid array (BGA) connections. In some embodiments, interconnections members 39 are I/O connections, such as through-hole and surface mounted connections. Interconnection members 39 may also be pins or land grid array (LGA) connections; Paragraph [0021] Line 4-10).
Regarding claim 12, Palanduz teaches a mounting method, wherein
when mounting the BGA package [24] on the interposer package [10] (With reference to FIG. 1, a substrate 10 is shown connecting a first device 20 and a second device 30; Paragraph [0017] Line 1-2),
the BGA package [24] is mounted to a pad [23] arranged on the second substrate [12] (Each one of the contact pads 22 matches up with a respective contact pad 23 on an upper surface 12 of the substrate 10. The contact pads 22 of first device 20 are connected to the contact pads 23 of substrate 10 by a respective one of conductive interconnection members 24; Paragraph [0019] Line 5-9).
Regarding claim 13, Palanduz teaches a burn-in test apparatus in Figure 1 (A system having a silicon die, an organic package substrate, and a substrate having a functionally gradient coefficient of thermal expansion, connecting the silicon die and the organic substrate is also described; Abstract) comprising:
a test device package [20] (an integrated circuit as the test device package) in which a test device configured to test a device under test is housed (In some embodiments, first device 20 is a die having an integrated circuit at a lower surface thereof. In some embodiments, first device 20 is silicon. In some embodiments, second device 30 may be a package substrate, a motherboard, or a printed circuit board (PCB). In some embodiments, second device 30 is another ceramic substrate. In some embodiments, second device 30 is plastic. In some embodiments, second device 30 is a PCB of a plastic package substrate; Paragraph [0018] Line 1-9);
a burn-in board [30] (package substrate, a motherboard, or a printed circuit board (PCB) as the burn-in board- Burn-In Board (BIB), also called a Burn-In PCB, is a specialized PCB therefore PCB disclosed by Palanduz can be considered as a burn-in board) in which the device under test and the test device package are placed (A substrate, such as a package substrate or an interposer substrate, having a gradient coefficient of thermal expansion (CTE) is described herein. Connection of the substrate having a gradient CTE to a die and another substrate or motherboard to reduce thermomechanical stress at the interconnection members is also described herein; Paragraph [0015] Line 1-6; With reference to FIG. 1, a substrate 10 is shown connecting a first device 20 and a second device 30; Paragraph [0017] Line 1-2; In some embodiments, first device 20 is a die having an integrated circuit at a lower surface thereof. In some embodiments, first device 20 is silicon. In some embodiments, second device 30 may be a package substrate, a motherboard, or a printed circuit board (PCB). In some embodiments, second device 30 is another ceramic substrate. In some embodiments, second device 30 is plastic. In some embodiments, second device 30 is a PCB of a plastic package substrate; Paragraph [0018] Line 1-9),
the interposer package [10] (A substrate, such as a package substrate or an interposer substrate; Paragraph [0015] Line 1-2) according to claim 1 (See rejection of claim 1 above) mounted between the burn-in board [30] and the test device package [20] (With reference to FIG. 1, a substrate 10 is shown connecting a first device 20 and a second device 30; Paragraph [0017] Line 1-2)
Palanduz fails to teach a test furnace in which the burn-in board, the device under test, the interposer package, and the test device package are housed; and a test apparatus configured to conduct, for the device under test, an accelerated test of a temperature-voltage stress while conducting a function test.
Eldridge teaches wafer level interposers, and more particularly to interposers having double-sided contact elements for interfacing two electrical devices, and to methods for making such interposers (Paragraph [0001] Line 1-4) and a method of the present invention also enables performing wafer-level burn-in and test of a plurality of semiconductor devices (DUTs) resident on a semiconductor wafer (Paragraph [0010] Line 1-4), wherein
a test furnace in which the burn-in board, the device under test, the interposer package, and the test device package are housed (For certain resilient contact elements, as used in the interposer (or space transformer) embodiments of the present invention, a tip structure can be fabricated as an end of each interconnect element. As shown in FIG. 7a, tip structures 1320 (only two tip structures are shown in the view of FIG. 7a, for illustrative clarity) are aligned with the tips of the interconnection elements (contact element) 1332, using standard flip-chip techniques (e.g., split prism), and the assembly is passed through a brazing furnace to reflow the joining material 1324, thereby joining (e.g., brazing) the prefabricated tip structures 1320 to the ends of the interconnection elements 1332; Paragraph [0079] Line 1-12; brazing furnace is the test furnace through which the assembly comprises the burn-in board, the device under test, the interposer package, and the test device package are housed is passed); and
a test apparatus (Figure 16) configured to conduct, for the device under test (FIG. 16 illustrates an instantiation of the system 1900 of the present invention, illustrating a number of features, which would be applicable to a variety of instantiations of the technique of the present intention. These features are a plurality of ASICs 2006, mounted to an interconnection (support) substrate 2008, and a plurality of DUTs 2002 connected to the ASICs 2006, through an interposer 2001, having double-sided resilient contact elements as discussed hereinabove and indicated by the arrows 2003. A power supply 2018 provides power, via the interconnection substrate 2008, via ASICs 2006 and via interposer 2001, to the DUTs 2002 to power them up for operation. This is especially useful for testing and also useful for burn-in; Paragraph [0110] Line 1-14), an accelerated test of a temperature-voltage stress while conducting a function test (In one embodiment, the assembly is disposed in a vacuum vessel with independent temperature regulation so that the ASICs can be operated at temperatures independent from and in many instances significantly lower than the burn-in temperature of the DUTs. The spring contact elements 110 may be mounted to either the DUTs 102a-102d or the ASICs 106a-106d, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs 106 and the DUTs 102. For the connection 120 to the host controller, a significant reduction in interconnect count and consequent simplification of the interconnection substrate is realized because the ASICs are capable of receiving a plurality of signals for testing the DUTs over relatively few signal lines from a host controller 116 and promulgating these signals over the relatively many interconnections 110 between the ASICs 106 and the DUTs 102. The ASICs 106 can also generate at least a portion of these signals in response to control signals from the host controller 116; Paragraph [0003] Line 20-37). The purpose of doing so is to establish reliable connections between such a large number of contact pads between the wafer and the tester is a significant challenge, to power up for operation for testing and also for burn-in, to test a plurality of complicated electronic components (DUTs).
It would have obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, to modify Rogers in view of Eldridge, because Eldridge teaches to include a test furnace in which the burn-in board, the device under test, the interposer package, and the test device package are housed establishes reliable connections between such a large number of contact pads between the wafer and the tester is a significant challenge (Paragraph [0005]), powers up for operation for testing and also for burn-in (Paragraph [0110]), tests a plurality of complicated electronic components (DUTs) (Paragraph [0112]).
Regarding claim 14, Palanduz teaches a burn-in test apparatus, further
comprising:
a third substrate [227] (layer 227 as the third substrate as any layer can be considered as the substrate) (In some embodiments, substrate 10 includes a plurality of layers, as illustrated in FIGS. 2 and 3. Layer 14 is shown in FIG. 2 having a plurality of layers 219, 221, 223, . . . 225, 227, 229. Layer 14 may include more or less than the six layers presently illustrated; Paragraph [0033] Line 1-5) disposed between the first substrate [16] and the first sheet contact [223/225] (Figure 2: Modified Figure 2 of Palanduz above shows a third substrate [227] disposed between the first substrate [16] and the first sheet contact [223/225]);
a fourth substrate [221] (layer 221 as the fourth substrate as any layer can be considered as the substrate) (In some embodiments, substrate 10 includes a plurality of layers, as illustrated in FIGS. 2 and 3. Layer 14 is shown in FIG. 2 having a plurality of layers 219, 221, 223, . . . 225, 227, 229. Layer 14 may include more or less than the six layers presently illustrated; Paragraph [0033] Line 1-5) disposed between the second substrate [12] and the first sheet contact [223/225] (Figure 2: Modified Figure 2 of Palanduz above shows a third substrate [221] disposed between the first substrate [16] and the first sheet contact [223/225]);
a second sheet contact [229] (layer 229 as the second sheet contact as any layer can be considered as the sheet contact as the layer contacts with the other layers) disposed between the first substrate [16] and the third substrate [227] (Figure 2: Modified Figure 2 of Palanduz above shows a second sheet contact [229] disposed between the first substrate [16] and the third substrate [227]); and
a third sheet contact [219] (layer 219 as the third sheet contact as any layer can be considered as the sheet contact as the layer contacts with the other layers) (In some embodiments, substrate 10 includes a plurality of layers, as illustrated in FIGS. 2 and 3. Layer 14 is shown in FIG. 2 having a plurality of layers 219, 221, 223, . . . 225, 227, 229. Layer 14 may include more or less than the six layers presently illustrated; Paragraph [0033] Line 1-5) disposed between the second substrate [12] and the fourth substrate [221] ((Figure 2: Modified Figure 2 of Palanduz above shows a third sheet contact [219] disposed between the second substrate [12] and the fourth substrate [221]), wherein
when the coefficient of expansion of the burn-in board [30] is larger than the coefficient of expansion of the test device package [20] (The CTE gradient refers to a plurality of CTE's, the plurality of CTE's incrementally increasing or decreasing between the upper and lower surfaces of the substrate; Paragraph [0016] Line 1-3; In some embodiments, the CTE of upper layer 12 matches the CTE of the first device 20 and the CTE of the lower layer 16 matches the CTE of the second device 30; Paragraph [0026] Line 1-3; when CTE incrementally decreasing from bottom to top (from first substrate to second substrate) then the CTE of the burn-in board 30 is larger than CTE of test device package 20 as the CTE of the burn-in board is same as first substrate and CTE of the test device 20 is same as the second substrate),
a coefficient of expansion of the third substrate [227] is smaller than the coefficient of expansion of the first substrate [16] and larger than a coefficient of expansion of the fourth substrate [221] (The CTE of layers 12, 14, 16 gradually vary to create a CTE gradient between the upper and lower surfaces (in the z-direction) of substrate 10. That is, the CTE of the substrate is incrementally increased or decreased between the upper and lower surfaces of the substrate by forming each layer 12, 14, 16, such that each one of the layers 12, 14, 16 has a different CTE corresponding therewith; Paragraph [0023] Line 1-7; As the CTE incrementally decreasing then a coefficient of expansion of the third substrate 227 is smaller than the coefficient of expansion of the first substrate 16 and larger than a coefficient of expansion of the fourth substrate 221 as shown in Figure 2: Modified Figure 2 of Palanduz above), and
the coefficient of expansion of the fourth substrate [221] is larger than the coefficient of expansion of the second substrate [12] and small than the coefficient of expansion of the third substrate [227] (As the CTE incrementally decreasing from bottom to top, the coefficient of expansion of the fourth substrate [221] is larger than the coefficient of expansion of the second substrate [12] and small than the coefficient of expansion of the third substrate [227] as shown in Figure 2: Modified Figure 2 of Palanduz above), and
when the coefficient of expansion of the test device package [20] is larger than a coefficient of expansion of the burn-in board [30] (The CTE gradient refers to a plurality of CTE's, the plurality of CTE's incrementally increasing or decreasing between the upper and lower surfaces of the substrate; Paragraph [0016] Line 1-3; In some embodiments, the CTE of upper layer 12 matches the CTE of the first device 20 and the CTE of the lower layer 16 matches the CTE of the second device 30; Paragraph [0026] Line 1-3; when CTE incrementally increasing from bottom to top (from first substrate to second substrate) then the CTE of the burn-in board 30 is smaller than CTE of test device package 20 as the CTE of the burn-in board is same as first substrate and CTE of the test device 20 is same as the second substrate),
the coefficient of expansion of the fourth substrate [221] is smaller than the coefficient of expansion of the second substrate [12] and larger than the coefficient of expansion of the third substrate [227] (As the CTE incrementally increasing from bottom to top, the coefficient of expansion of the fourth substrate [221] is smaller than the coefficient of expansion of the second substrate [12] and larger than the coefficient of expansion of the third substrate [227] as shown in Figure 2: Modified Figure 2 of Palanduz above), and
the coefficient of expansion of the third substrate [227] is larger than the coefficient of expansion of the first substrate [16] and smaller than the coefficient of expansion of the fourth substrate [221] (As the CTE incrementally increasing from bottom to top, the coefficient of expansion of the third substrate 227 is larger than the coefficient of expansion of the first substrate 16 and smaller than a coefficient of expansion of the fourth substrate 221 as shown in Figure 2: Modified Figure 2 of Palanduz above).
Regarding claim 15, Palanduz teaches a burn-in test apparatus, wherein
the interposer package [10] further comprising:
at least one through electrode [18] (conductive vias 18 as the electrode as the vias made of conductive material) (A plurality of conductive vias 18 extend through each of the layers 12, 14, 16; Paragraph [0022] Line 2-3; Electrodes are conductive elements that serve as the interface between an electrical circuit and another medium — such as a liquid, gas, or solid — enabling the transfer of electrical energy or signals. In PCBs, electrodes are typically copper traces, pads, or vias that connect components and power planes. In electrochemistry or sensors, they may be metal surfaces that contact an electrolyte or dielectric; Via: A specific type of electrode structure used to interconnect layers in a PCB or IC, formed by a plated hole between layers; https://www.bing.com/search?q=electrode%20and%20via&qs=n&form=QBRE&sp=-1&lq=0&pq=electrode%20and%20via&sc=12-17&sk=&cvid=78D9022617C5418593E69564415EFB83) disposed passing through the first substrate [16], the second substrate [12], and the first sheet contact [14] (Each contact pad 23, 33 of substrate 10 is located on and mechanically and electrically connected to a respective one of the plurality of conductive vias 18. In some embodiments, vias 18 have a CTE gradient similar to or matching the CTE gradient of substrate 10 to reduce stress due to thermal expansivity mismatch within the substrate and at interconnection members 24, 34. Plurality of vias 18 each include an upper conductive via 13, an intermediate conductive via 15 and a lower conductive via 17; Paragraph [0027] Line 1-9; Typically, vias 18 are formed from a conductive material, such as copper, silver, or an alloy of tungsten and molybdenum. By varying the material composition and characteristics of the metallic paste used to form vias 13, 15, 17 of vias 18 between the upper and lower surfaces of the substrate; Paragraph [0030] Line 1-4),
the through electrode [18] having one end welded to the burn-in board [30] (A plurality of contact pads 32 are also provided on an upper surface of the substrate 30. Each one of the contact pads 32 on the upper surface of second device 30 matches up with a respective one of the contact pads 33 on substrate 10. Conductive interconnection members 34 interconnect contact pads 32 of second device 30 with contact pads 33 of substrate 10 to mechanically and electrically connect substrate 10 and second device 30; Paragraph [0020] Line 1-8; through electrode 18 (13+15+17) having welded in one end with the contact pad 32 in the burn-in board and with the contact pad 33 in the first substrate 16) and the other end welded to the test device package [20] (The first device 20 may include an integrated circuit formed in a lower surface thereof. A plurality of contact pads 22 are formed on a lower surface of the first device 20 and are electrically and mechanically connected to the integrated circuit. Each one of the contact pads 22 matches up with a respective contact pad 23 on an upper surface of the substrate 10. The contact pads 22 of first device 20 are connected to the contact pads 23 of substrate 10 by a respective one of conductive interconnection members 24; Paragraph [0019] Line 1-9; through electrode 18 (13+15+17) having welded in one end with the contact pad 22 in the test device package and with the contact pad 23 in the second substrate 12).
Regarding claim 16, Palanduz teaches a burn-in test apparatus, wherein
the test device package [20] is a BGA package (In some embodiments, the conductive interconnection members 24, 34, 39 are solder balls connections, wirebond connections, tape automated bonding (TAB) connections or C4 connections. In some embodiments, interconnection member 24, 34, 39 are ball grid array (BGA) connections; Paragraph [0021] Line 1-5), and in the interposer package [10],
the first substrate [16] is mounted on the burn-in board [30] with
a BGA [34] (interconnection 34 as the BGA) arranged on the first substrate [16] (Conductive interconnection members 34 interconnect contact pads 32 of second device 30 with contact pads 33 of substrate 10 to mechanically and electrically connect substrate 10 and second device 30; Paragraph [0020] Line 5-8).
Regarding claim 17, Palanduz teaches a burn-in test apparatus, wherein
the test device package [20] is an LGA package (In some embodiments, interconnection member 24, 34, 39 are ball grid array (BGA) connections. In some embodiments, interconnections members 39 are I/O connections, such as through-hole and surface mounted connections. Interconnection members 39 may also be pins or land grid array (LGA) connections; Paragraph [0021] Line 4-10), and
in the interposer package [10], the first substrate [16] is mounted on the burn-in board [30] with a plug pin [34/39] arranged on the first substrate [16] (Figure 1) (Conductive interconnection members 34 interconnect contact pads 32 of second device 30 with contact pads 33 of substrate 10 to mechanically and electrically connect substrate 10 and second device 30; Paragraph [0020] Line 5-8; Figure 1 shows the first substrate [16] is mounted on the burn-in board [30] with a plug pin [34/39] arranged on the first substrate).
Regarding claim 18, Palanduz teaches a burn-in test apparatus, wherein
in the interposer package [10], the BGA package [24] is mounted to a plug pin [39] arranged on the second substrate [12] (In some embodiments, interconnection member 24, 34, 39 are ball grid array (BGA) connections. In some embodiments, interconnections members 39 are I/O connections, such as through-hole and surface mounted connections. Interconnection members 39 may also be pins or land grid array (LGA) connections; Paragraph [0021] Line 4-10).
Regarding claim 19, Palanduz teaches a burn-in test apparatus, wherein
in the interposer package [10], the BGA package [24] is mounted to a pad [23] arranged on the second substrate [12] (Each one of the contact pads 22 matches up with a respective contact pad 23 on an upper surface 12 of the substrate 10. The contact pads 22 of first device 20 are connected to the contact pads 23 of substrate 10 by a respective one of conductive interconnection members 24; Paragraph [0019] Line 5-9).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chan et al. (US 20070075726 A1) discloses, “Interposer And Test Assembly For Testing Electronic Devices- [0003] The invention relates to test assemblies for testing electronic devices such as semiconductor chips and particularly to interposers for interconnecting such devices to a circuitized substrate such as a printed circuit board whereupon a series of electrical tests may be performed on the device. [0050] In FIG. 1, there is shown a test assembly 11 for testing an electronic device 13 such as one or more semiconductor chips on a large wafer 15. Three such devices (chips) 13 are shown, but understandably many more may form part of wafer 15. Assembly 11 includes a host circuitized substrate 17 (e.g., a printed circuit board) having a plurality of host conductor pads 19 on the upper surface thereof (see especially FIG. 2), and a housing 21 positioned on the host circuitized substrate 17 for substantially surrounding the plurality of host conductor pads 19. Housing 21 is preferably plastic (e.g., a highly-durable resin thermoplastic polycarbonate such as Lexan, a polyphenylene sulfide (PPS) such as Ryton), or a liquid crystal polymer (LCP) and includes an open portion (cavity) 23 therein designed to accommodate a first circuitized substrate 25 which also forms part of assembly 11. (Lexan and Ryton are trademarks of the General Electric Company and Chevron Phillips Chemical Company, respectively.) Cavity 23 is preferably of rectangular configuration when viewed from the top of housing 21. Substrate 25, preferably a multi-layered printed circuit board as defined in greater detail below, is movably positioned within the housing and includes a first plurality of contact pads 27 (see especially FIG. 2) on the undersurface thereof. Pads 27 are arranged in a pattern of a first density similar to that of the corresponding pads 19 on substrate 17. As seen in FIGS. 1 and 2, selected ones of this first plurality of contact pads 27 of substrate 25 are adapted for engaging respective ones of the host conductor pads 19 when substrate 25 is fully positioned within housing 21. Housing 21 is preferably aligned relative to the underlying substrate 17 using a plurality of alignment pins 28, two of these being shown in phantom in FIG. 1. At least four such pins are preferably used, one at each of the comers of the rectangular shaped housing. [0051] Assembly 11 further includes a second circuitized substrate 29 positioned on first circuitized substrate 25 and, as also defined in greater detail below, is electrically coupled thereto-However Chan does not disclose a first substrate having a coefficient of expansion that is the same or substantially the same as a coefficient of expansion of the burn-in board; a second substrate having a coefficient of expansion that is the same or substantially the same as a coefficient of expansion of the test device package.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NASIMA MONSUR whose telephone number is (571)272-8497. The examiner can normally be reached 10:00 am-6:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eman Alkafawi can be reached at (571) 272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NASIMA MONSUR/Primary Examiner, Art Unit 2858
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